qemu/hw/eccmemctl.c

   1 /*
   2  * QEMU Sparc Sun4m ECC memory controller emulation
   3  *
   4  * Copyright (c) 2007 Robert Reif
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "sysemu.h"
  27
  28 //#define DEBUG_ECC
  29
  30 #ifdef DEBUG_ECC
  31 #define DPRINTF(fmt, args...)                           \
  32     do { printf("ECC: " fmt , ##args); } while (0)
  33 #else
  34 #define DPRINTF(fmt, args...)
  35 #endif
  36
  37 /* There are 3 versions of this chip used in SMP sun4m systems:
  38  * MCC (version 0, implementation 0) SS-600MP
  39  * EMC (version 0, implementation 1) SS-10
  40  * SMC (version 0, implementation 2) SS-10SX and SS-20
  41  */
  42
  43 /* Register offsets */
  44 #define ECC_FCR_REG    0
  45 #define ECC_FSR_REG    8
  46 #define ECC_FAR0_REG   16
  47 #define ECC_FAR1_REG   20
  48 #define ECC_DIAG_REG   24
  49
  50 /* ECC fault control register */
  51 #define ECC_FCR_EE     0x00000001      /* Enable ECC checking */
  52 #define ECC_FCR_EI     0x00000010      /* Enable Interrupts on correctable errors */
  53 #define ECC_FCR_VER    0x0f000000      /* Version */
  54 #define ECC_FCR_IMPL   0xf0000000      /* Implementation */
  55
  56 /* ECC fault status register */
  57 #define ECC_FSR_CE     0x00000001      /* Correctable error */
  58 #define ECC_FSR_BS     0x00000002      /* C2 graphics bad slot access */
  59 #define ECC_FSR_TO     0x00000004      /* Timeout on write */
  60 #define ECC_FSR_UE     0x00000008      /* Uncorrectable error */
  61 #define ECC_FSR_DW     0x000000f0      /* Index of double word in block */
  62 #define ECC_FSR_SYND   0x0000ff00      /* Syndrome for correctable error */
  63 #define ECC_FSR_ME     0x00010000      /* Multiple errors */
  64 #define ECC_FSR_C2ERR  0x00020000      /* C2 graphics error */
  65
  66 /* ECC fault address register 0 */
  67 #define ECC_FAR0_PADDR 0x0000000f      /* PA[32-35] */
  68 #define ECC_FAR0_TYPE  0x000000f0      /* Transaction type */
  69 #define ECC_FAR0_SIZE  0x00000700      /* Transaction size */
  70 #define ECC_FAR0_CACHE 0x00000800      /* Mapped cacheable */
  71 #define ECC_FAR0_LOCK  0x00001000      /* Error occurred in atomic cycle */
  72 #define ECC_FAR0_BMODE 0x00002000      /* Boot mode */
  73 #define ECC_FAR0_VADDR 0x003fc000      /* VA[12-19] (superset bits) */
  74 #define ECC_FAR0_S     0x08000000      /* Supervisor mode */
  75 #define ECC_FARO_MID   0xf0000000      /* Module ID */
  76
  77 /* ECC diagnostic register */
  78 #define ECC_DIAG_CBX   0x00000001
  79 #define ECC_DIAG_CB0   0x00000002
  80 #define ECC_DIAG_CB1   0x00000004
  81 #define ECC_DIAG_CB2   0x00000008
  82 #define ECC_DIAG_CB4   0x00000010
  83 #define ECC_DIAG_CB8   0x00000020
  84 #define ECC_DIAG_CB16  0x00000040
  85 #define ECC_DIAG_CB32  0x00000080
  86 #define ECC_DIAG_DMODE 0x00000c00
  87
  88 #define ECC_NREGS      8
  89 #define ECC_SIZE       (ECC_NREGS * sizeof(uint32_t))
  90 #define ECC_ADDR_MASK  (ECC_SIZE - 1)
  91
  92 typedef struct ECCState {
  93     qemu_irq irq;
  94     uint32_t regs[ECC_NREGS];
  95 } ECCState;
  96
  97 static void ecc_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
  98 {
  99     ECCState *s = opaque;
 100
 101     switch (addr & ECC_ADDR_MASK) {
 102     case ECC_FCR_REG:
 103         s->regs[0] = (s->regs[0] & (ECC_FCR_VER | ECC_FCR_IMPL)) |
 104                      (val & ~(ECC_FCR_VER | ECC_FCR_IMPL));
 105         DPRINTF("Write fault control %08x\n", val);
 106         break;
 107     case 4:
 108         s->regs[1] =  val;
 109         DPRINTF("Write reg[1] %08x\n", val);
 110         break;
 111     case ECC_FSR_REG:
 112         s->regs[2] =  val;
 113         DPRINTF("Write fault status %08x\n", val);
 114         break;
 115     case 12:
 116         s->regs[3] =  val;
 117         DPRINTF("Write reg[3] %08x\n", val);
 118         break;
 119     case ECC_FAR0_REG:
 120         s->regs[4] =  val;
 121         DPRINTF("Write fault address 0 %08x\n", val);
 122         break;
 123     case ECC_FAR1_REG:
 124         s->regs[5] =  val;
 125         DPRINTF("Write fault address 1 %08x\n", val);
 126         break;
 127     case ECC_DIAG_REG:
 128         s->regs[6] =  val;
 129         DPRINTF("Write diag %08x\n", val);
 130         break;
 131     case 28:
 132         s->regs[7] =  val;
 133         DPRINTF("Write reg[7] %08x\n", val);
 134         break;
 135     }
 136 }
 137
 138 static uint32_t ecc_mem_readl(void *opaque, target_phys_addr_t addr)
 139 {
 140     ECCState *s = opaque;
 141     uint32_t ret = 0;
 142
 143     switch (addr & ECC_ADDR_MASK) {
 144     case ECC_FCR_REG:
 145         ret = s->regs[0];
 146         DPRINTF("Read enable %08x\n", ret);
 147         break;
 148     case 4:
 149         ret = s->regs[1];
 150         DPRINTF("Read register[1] %08x\n", ret);
 151         break;
 152     case ECC_FSR_REG:
 153         ret = s->regs[2];
 154         DPRINTF("Read fault status %08x\n", ret);
 155         break;
 156     case 12:
 157         ret = s->regs[3];
 158         DPRINTF("Read reg[3] %08x\n", ret);
 159         break;
 160     case ECC_FAR0_REG:
 161         ret = s->regs[4];
 162         DPRINTF("Read fault address 0 %08x\n", ret);
 163         break;
 164     case ECC_FAR1_REG:
 165         ret = s->regs[5];
 166         DPRINTF("Read fault address 1 %08x\n", ret);
 167         break;
 168     case ECC_DIAG_REG:
 169         ret = s->regs[6];
 170         DPRINTF("Read diag %08x\n", ret);
 171         break;
 172     case 28:
 173         ret = s->regs[7];
 174         DPRINTF("Read reg[7] %08x\n", ret);
 175         break;
 176     }
 177     return ret;
 178 }
 179
 180 static CPUReadMemoryFunc *ecc_mem_read[3] = {
 181     NULL,
 182     NULL,
 183     ecc_mem_readl,
 184 };
 185
 186 static CPUWriteMemoryFunc *ecc_mem_write[3] = {
 187     NULL,
 188     NULL,
 189     ecc_mem_writel,
 190 };
 191
 192 static int ecc_load(QEMUFile *f, void *opaque, int version_id)
 193 {
 194     ECCState *s = opaque;
 195     int i;
 196
 197     if (version_id != 1)
 198         return -EINVAL;
 199
 200     for (i = 0; i < ECC_NREGS; i++)
 201         qemu_get_be32s(f, &s->regs[i]);
 202
 203     return 0;
 204 }
 205
 206 static void ecc_save(QEMUFile *f, void *opaque)
 207 {
 208     ECCState *s = opaque;
 209     int i;
 210
 211     for (i = 0; i < ECC_NREGS; i++)
 212         qemu_put_be32s(f, &s->regs[i]);
 213 }
 214
 215 static void ecc_reset(void *opaque)
 216 {
 217     ECCState *s = opaque;
 218     int i;
 219
 220     s->regs[ECC_FCR_REG] &= (ECC_FCR_VER | ECC_FCR_IMPL);
 221
 222     for (i = 1; i < ECC_NREGS; i++)
 223         s->regs[i] = 0;
 224 }
 225
 226 void * ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
 227 {
 228     int ecc_io_memory;
 229     ECCState *s;
 230
 231     s = qemu_mallocz(sizeof(ECCState));
 232     if (!s)
 233         return NULL;
 234
 235     s->regs[0] = version;
 236     s->irq = irq;
 237
 238     ecc_io_memory = cpu_register_io_memory(0, ecc_mem_read, ecc_mem_write, s);
 239     cpu_register_physical_memory(base, ECC_SIZE, ecc_io_memory);
 240     register_savevm("ECC", base, 1, ecc_save, ecc_load, s);
 241     qemu_register_reset(ecc_reset, s);
 242     ecc_reset(s);
 243     return s;
 244 }