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kvm: qemu: pci hotplug GPE support
[kvm-userspace.git] / qemu / hw / slavio_serial.c
blobbd572b03fd7454baa8b6ff61cacf8e89e3aab94d
1 /*
2 * QEMU Sparc SLAVIO serial port emulation
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "sun4m.h"
26 #include "qemu-char.h"
27 #include "console.h"
28
29 /* debug serial */
30 //#define DEBUG_SERIAL
31
32 /* debug keyboard */
33 //#define DEBUG_KBD
34
35 /* debug mouse */
36 //#define DEBUG_MOUSE
37
38 /*
39 * This is the serial port, mouse and keyboard part of chip STP2001
40 * (Slave I/O), also produced as NCR89C105. See
41 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
42 *
43 * The serial ports implement full AMD AM8530 or Zilog Z8530 chips,
44 * mouse and keyboard ports don't implement all functions and they are
45 * only asynchronous. There is no DMA.
46 *
47 */
48
49 /*
50 * Modifications:
51 * 2006-Aug-10 Igor Kovalenko : Renamed KBDQueue to SERIOQueue, implemented
52 * serial mouse queue.
53 * Implemented serial mouse protocol.
54 */
55
56 #ifdef DEBUG_SERIAL
57 #define SER_DPRINTF(fmt, args...) \
58 do { printf("SER: " fmt , ##args); } while (0)
59 #else
60 #define SER_DPRINTF(fmt, args...)
61 #endif
62 #ifdef DEBUG_KBD
63 #define KBD_DPRINTF(fmt, args...) \
64 do { printf("KBD: " fmt , ##args); } while (0)
65 #else
66 #define KBD_DPRINTF(fmt, args...)
67 #endif
68 #ifdef DEBUG_MOUSE
69 #define MS_DPRINTF(fmt, args...) \
70 do { printf("MSC: " fmt , ##args); } while (0)
71 #else
72 #define MS_DPRINTF(fmt, args...)
73 #endif
74
75 typedef enum {
76 chn_a, chn_b,
77 } chn_id_t;
78
79 #define CHN_C(s) ((s)->chn == chn_b? 'b' : 'a')
80
81 typedef enum {
82 ser, kbd, mouse,
83 } chn_type_t;
84
85 #define SERIO_QUEUE_SIZE 256
86
87 typedef struct {
88 uint8_t data[SERIO_QUEUE_SIZE];
89 int rptr, wptr, count;
90 } SERIOQueue;
91
92 #define SERIAL_REGS 16
93 typedef struct ChannelState {
94 qemu_irq irq;
95 int reg;
96 int rxint, txint, rxint_under_svc, txint_under_svc;
97 chn_id_t chn; // this channel, A (base+4) or B (base+0)
98 chn_type_t type;
99 struct ChannelState *otherchn;
100 uint8_t rx, tx, wregs[SERIAL_REGS], rregs[SERIAL_REGS];
101 SERIOQueue queue;
102 CharDriverState *chr;
103 int e0_mode, led_mode, caps_lock_mode, num_lock_mode;
104 int disabled;
105 } ChannelState;
106
107 struct SerialState {
108 struct ChannelState chn[2];
109 };
110
111 #define SERIAL_MAXADDR 7
112 #define SERIAL_SIZE (SERIAL_MAXADDR + 1)
113 #define SERIAL_CTRL 0
114 #define SERIAL_DATA 1
115
116 #define W_CMD 0
117 #define CMD_PTR_MASK 0x07
118 #define CMD_CMD_MASK 0x38
119 #define CMD_HI 0x08
120 #define CMD_CLR_TXINT 0x28
121 #define CMD_CLR_IUS 0x38
122 #define W_INTR 1
123 #define INTR_INTALL 0x01
124 #define INTR_TXINT 0x02
125 #define INTR_RXMODEMSK 0x18
126 #define INTR_RXINT1ST 0x08
127 #define INTR_RXINTALL 0x10
128 #define W_IVEC 2
129 #define W_RXCTRL 3
130 #define RXCTRL_RXEN 0x01
131 #define W_TXCTRL1 4
132 #define TXCTRL1_PAREN 0x01
133 #define TXCTRL1_PAREV 0x02
134 #define TXCTRL1_1STOP 0x04
135 #define TXCTRL1_1HSTOP 0x08
136 #define TXCTRL1_2STOP 0x0c
137 #define TXCTRL1_STPMSK 0x0c
138 #define TXCTRL1_CLK1X 0x00
139 #define TXCTRL1_CLK16X 0x40
140 #define TXCTRL1_CLK32X 0x80
141 #define TXCTRL1_CLK64X 0xc0
142 #define TXCTRL1_CLKMSK 0xc0
143 #define W_TXCTRL2 5
144 #define TXCTRL2_TXEN 0x08
145 #define TXCTRL2_BITMSK 0x60
146 #define TXCTRL2_5BITS 0x00
147 #define TXCTRL2_7BITS 0x20
148 #define TXCTRL2_6BITS 0x40
149 #define TXCTRL2_8BITS 0x60
150 #define W_SYNC1 6
151 #define W_SYNC2 7
152 #define W_TXBUF 8
153 #define W_MINTR 9
154 #define MINTR_STATUSHI 0x10
155 #define MINTR_RST_MASK 0xc0
156 #define MINTR_RST_B 0x40
157 #define MINTR_RST_A 0x80
158 #define MINTR_RST_ALL 0xc0
159 #define W_MISC1 10
160 #define W_CLOCK 11
161 #define CLOCK_TRXC 0x08
162 #define W_BRGLO 12
163 #define W_BRGHI 13
164 #define W_MISC2 14
165 #define MISC2_PLLDIS 0x30
166 #define W_EXTINT 15
167 #define EXTINT_DCD 0x08
168 #define EXTINT_SYNCINT 0x10
169 #define EXTINT_CTSINT 0x20
170 #define EXTINT_TXUNDRN 0x40
171 #define EXTINT_BRKINT 0x80
172
173 #define R_STATUS 0
174 #define STATUS_RXAV 0x01
175 #define STATUS_ZERO 0x02
176 #define STATUS_TXEMPTY 0x04
177 #define STATUS_DCD 0x08
178 #define STATUS_SYNC 0x10
179 #define STATUS_CTS 0x20
180 #define STATUS_TXUNDRN 0x40
181 #define STATUS_BRK 0x80
182 #define R_SPEC 1
183 #define SPEC_ALLSENT 0x01
184 #define SPEC_BITS8 0x06
185 #define R_IVEC 2
186 #define IVEC_TXINTB 0x00
187 #define IVEC_LONOINT 0x06
188 #define IVEC_LORXINTA 0x0c
189 #define IVEC_LORXINTB 0x04
190 #define IVEC_LOTXINTA 0x08
191 #define IVEC_HINOINT 0x60
192 #define IVEC_HIRXINTA 0x30
193 #define IVEC_HIRXINTB 0x20
194 #define IVEC_HITXINTA 0x10
195 #define R_INTR 3
196 #define INTR_EXTINTB 0x01
197 #define INTR_TXINTB 0x02
198 #define INTR_RXINTB 0x04
199 #define INTR_EXTINTA 0x08
200 #define INTR_TXINTA 0x10
201 #define INTR_RXINTA 0x20
202 #define R_IPEN 4
203 #define R_TXCTRL1 5
204 #define R_TXCTRL2 6
205 #define R_BC 7
206 #define R_RXBUF 8
207 #define R_RXCTRL 9
208 #define R_MISC 10
209 #define R_MISC1 11
210 #define R_BRGLO 12
211 #define R_BRGHI 13
212 #define R_MISC1I 14
213 #define R_EXTINT 15
214
215 static void handle_kbd_command(ChannelState *s, int val);
216 static int serial_can_receive(void *opaque);
217 static void serial_receive_byte(ChannelState *s, int ch);
218
219 static void clear_queue(void *opaque)
220 {
221 ChannelState *s = opaque;
222 SERIOQueue *q = &s->queue;
223 q->rptr = q->wptr = q->count = 0;
224 }
225
226 static void put_queue(void *opaque, int b)
227 {
228 ChannelState *s = opaque;
229 SERIOQueue *q = &s->queue;
230
231 SER_DPRINTF("channel %c put: 0x%02x\n", CHN_C(s), b);
232 if (q->count >= SERIO_QUEUE_SIZE)
233 return;
234 q->data[q->wptr] = b;
235 if (++q->wptr == SERIO_QUEUE_SIZE)
236 q->wptr = 0;
237 q->count++;
238 serial_receive_byte(s, 0);
239 }
240
241 static uint32_t get_queue(void *opaque)
242 {
243 ChannelState *s = opaque;
244 SERIOQueue *q = &s->queue;
245 int val;
246
247 if (q->count == 0) {
248 return 0;
249 } else {
250 val = q->data[q->rptr];
251 if (++q->rptr == SERIO_QUEUE_SIZE)
252 q->rptr = 0;
253 q->count--;
254 }
255 SER_DPRINTF("channel %c get 0x%02x\n", CHN_C(s), val);
256 if (q->count > 0)
257 serial_receive_byte(s, 0);
258 return val;
259 }
260
261 static int slavio_serial_update_irq_chn(ChannelState *s)
262 {
263 if ((s->wregs[W_INTR] & INTR_INTALL) && // interrupts enabled
264 (((s->wregs[W_INTR] & INTR_TXINT) && s->txint == 1) ||
265 // tx ints enabled, pending
266 ((((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINT1ST) ||
267 ((s->wregs[W_INTR] & INTR_RXMODEMSK) == INTR_RXINTALL)) &&
268 s->rxint == 1) || // rx ints enabled, pending
269 ((s->wregs[W_EXTINT] & EXTINT_BRKINT) &&
270 (s->rregs[R_STATUS] & STATUS_BRK)))) { // break int e&p
271 return 1;
272 }
273 return 0;
274 }
275
276 static void slavio_serial_update_irq(ChannelState *s)
277 {
278 int irq;
279
280 irq = slavio_serial_update_irq_chn(s);
281 irq |= slavio_serial_update_irq_chn(s->otherchn);
282
283 SER_DPRINTF("IRQ = %d\n", irq);
284 qemu_set_irq(s->irq, irq);
285 }
286
287 static void slavio_serial_reset_chn(ChannelState *s)
288 {
289 int i;
290
291 s->reg = 0;
292 for (i = 0; i < SERIAL_SIZE; i++) {
293 s->rregs[i] = 0;
294 s->wregs[i] = 0;
295 }
296 s->wregs[W_TXCTRL1] = TXCTRL1_1STOP; // 1X divisor, 1 stop bit, no parity
297 s->wregs[W_MINTR] = MINTR_RST_ALL;
298 s->wregs[W_CLOCK] = CLOCK_TRXC; // Synch mode tx clock = TRxC
299 s->wregs[W_MISC2] = MISC2_PLLDIS; // PLL disabled
300 s->wregs[W_EXTINT] = EXTINT_DCD | EXTINT_SYNCINT | EXTINT_CTSINT |
301 EXTINT_TXUNDRN | EXTINT_BRKINT; // Enable most interrupts
302 if (s->disabled)
303 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_DCD | STATUS_SYNC |
304 STATUS_CTS | STATUS_TXUNDRN;
305 else
306 s->rregs[R_STATUS] = STATUS_TXEMPTY | STATUS_TXUNDRN;
307 s->rregs[R_SPEC] = SPEC_BITS8 | SPEC_ALLSENT;
308
309 s->rx = s->tx = 0;
310 s->rxint = s->txint = 0;
311 s->rxint_under_svc = s->txint_under_svc = 0;
312 s->e0_mode = s->led_mode = s->caps_lock_mode = s->num_lock_mode = 0;
313 clear_queue(s);
314 }
315
316 static void slavio_serial_reset(void *opaque)
317 {
318 SerialState *s = opaque;
319 slavio_serial_reset_chn(&s->chn[0]);
320 slavio_serial_reset_chn(&s->chn[1]);
321 }
322
323 static inline void set_rxint(ChannelState *s)
324 {
325 s->rxint = 1;
326 if (!s->txint_under_svc) {
327 s->rxint_under_svc = 1;
328 if (s->chn == chn_a) {
329 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
330 s->otherchn->rregs[R_IVEC] = IVEC_HIRXINTA;
331 else
332 s->otherchn->rregs[R_IVEC] = IVEC_LORXINTA;
333 } else {
334 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
335 s->rregs[R_IVEC] = IVEC_HIRXINTB;
336 else
337 s->rregs[R_IVEC] = IVEC_LORXINTB;
338 }
339 }
340 if (s->chn == chn_a)
341 s->rregs[R_INTR] |= INTR_RXINTA;
342 else
343 s->otherchn->rregs[R_INTR] |= INTR_RXINTB;
344 slavio_serial_update_irq(s);
345 }
346
347 static inline void set_txint(ChannelState *s)
348 {
349 s->txint = 1;
350 if (!s->rxint_under_svc) {
351 s->txint_under_svc = 1;
352 if (s->chn == chn_a) {
353 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
354 s->otherchn->rregs[R_IVEC] = IVEC_HITXINTA;
355 else
356 s->otherchn->rregs[R_IVEC] = IVEC_LOTXINTA;
357 } else {
358 s->rregs[R_IVEC] = IVEC_TXINTB;
359 }
360 }
361 if (s->chn == chn_a)
362 s->rregs[R_INTR] |= INTR_TXINTA;
363 else
364 s->otherchn->rregs[R_INTR] |= INTR_TXINTB;
365 slavio_serial_update_irq(s);
366 }
367
368 static inline void clr_rxint(ChannelState *s)
369 {
370 s->rxint = 0;
371 s->rxint_under_svc = 0;
372 if (s->chn == chn_a) {
373 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
374 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;
375 else
376 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;
377 s->rregs[R_INTR] &= ~INTR_RXINTA;
378 } else {
379 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
380 s->rregs[R_IVEC] = IVEC_HINOINT;
381 else
382 s->rregs[R_IVEC] = IVEC_LONOINT;
383 s->otherchn->rregs[R_INTR] &= ~INTR_RXINTB;
384 }
385 if (s->txint)
386 set_txint(s);
387 slavio_serial_update_irq(s);
388 }
389
390 static inline void clr_txint(ChannelState *s)
391 {
392 s->txint = 0;
393 s->txint_under_svc = 0;
394 if (s->chn == chn_a) {
395 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
396 s->otherchn->rregs[R_IVEC] = IVEC_HINOINT;
397 else
398 s->otherchn->rregs[R_IVEC] = IVEC_LONOINT;
399 s->rregs[R_INTR] &= ~INTR_TXINTA;
400 } else {
401 if (s->wregs[W_MINTR] & MINTR_STATUSHI)
402 s->rregs[R_IVEC] = IVEC_HINOINT;
403 else
404 s->rregs[R_IVEC] = IVEC_LONOINT;
405 s->otherchn->rregs[R_INTR] &= ~INTR_TXINTB;
406 }
407 if (s->rxint)
408 set_rxint(s);
409 slavio_serial_update_irq(s);
410 }
411
412 static void slavio_serial_update_parameters(ChannelState *s)
413 {
414 int speed, parity, data_bits, stop_bits;
415 QEMUSerialSetParams ssp;
416
417 if (!s->chr || s->type != ser)
418 return;
419
420 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREN) {
421 if (s->wregs[W_TXCTRL1] & TXCTRL1_PAREV)
422 parity = 'E';
423 else
424 parity = 'O';
425 } else {
426 parity = 'N';
427 }
428 if ((s->wregs[W_TXCTRL1] & TXCTRL1_STPMSK) == TXCTRL1_2STOP)
429 stop_bits = 2;
430 else
431 stop_bits = 1;
432 switch (s->wregs[W_TXCTRL2] & TXCTRL2_BITMSK) {
433 case TXCTRL2_5BITS:
434 data_bits = 5;
435 break;
436 case TXCTRL2_7BITS:
437 data_bits = 7;
438 break;
439 case TXCTRL2_6BITS:
440 data_bits = 6;
441 break;
442 default:
443 case TXCTRL2_8BITS:
444 data_bits = 8;
445 break;
446 }
447 speed = 2457600 / ((s->wregs[W_BRGLO] | (s->wregs[W_BRGHI] << 8)) + 2);
448 switch (s->wregs[W_TXCTRL1] & TXCTRL1_CLKMSK) {
449 case TXCTRL1_CLK1X:
450 break;
451 case TXCTRL1_CLK16X:
452 speed /= 16;
453 break;
454 case TXCTRL1_CLK32X:
455 speed /= 32;
456 break;
457 default:
458 case TXCTRL1_CLK64X:
459 speed /= 64;
460 break;
461 }
462 ssp.speed = speed;
463 ssp.parity = parity;
464 ssp.data_bits = data_bits;
465 ssp.stop_bits = stop_bits;
466 SER_DPRINTF("channel %c: speed=%d parity=%c data=%d stop=%d\n", CHN_C(s),
467 speed, parity, data_bits, stop_bits);
468 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
469 }
470
471 static void slavio_serial_mem_writeb(void *opaque, target_phys_addr_t addr,
472 uint32_t val)
473 {
474 SerialState *serial = opaque;
475 ChannelState *s;
476 uint32_t saddr;
477 int newreg, channel;
478
479 val &= 0xff;
480 saddr = (addr & 3) >> 1;
481 channel = (addr & SERIAL_MAXADDR) >> 2;
482 s = &serial->chn[channel];
483 switch (saddr) {
484 case SERIAL_CTRL:
485 SER_DPRINTF("Write channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg,
486 val & 0xff);
487 newreg = 0;
488 switch (s->reg) {
489 case W_CMD:
490 newreg = val & CMD_PTR_MASK;
491 val &= CMD_CMD_MASK;
492 switch (val) {
493 case CMD_HI:
494 newreg |= CMD_HI;
495 break;
496 case CMD_CLR_TXINT:
497 clr_txint(s);
498 break;
499 case CMD_CLR_IUS:
500 if (s->rxint_under_svc)
501 clr_rxint(s);
502 else if (s->txint_under_svc)
503 clr_txint(s);
504 break;
505 default:
506 break;
507 }
508 break;
509 case W_INTR ... W_RXCTRL:
510 case W_SYNC1 ... W_TXBUF:
511 case W_MISC1 ... W_CLOCK:
512 case W_MISC2 ... W_EXTINT:
513 s->wregs[s->reg] = val;
514 break;
515 case W_TXCTRL1:
516 case W_TXCTRL2:
517 case W_BRGLO:
518 case W_BRGHI:
519 s->wregs[s->reg] = val;
520 slavio_serial_update_parameters(s);
521 break;
522 case W_MINTR:
523 switch (val & MINTR_RST_MASK) {
524 case 0:
525 default:
526 break;
527 case MINTR_RST_B:
528 slavio_serial_reset_chn(&serial->chn[1]);
529 return;
530 case MINTR_RST_A:
531 slavio_serial_reset_chn(&serial->chn[0]);
532 return;
533 case MINTR_RST_ALL:
534 slavio_serial_reset(serial);
535 return;
536 }
537 break;
538 default:
539 break;
540 }
541 if (s->reg == 0)
542 s->reg = newreg;
543 else
544 s->reg = 0;
545 break;
546 case SERIAL_DATA:
547 SER_DPRINTF("Write channel %c, ch %d\n", CHN_C(s), val);
548 s->tx = val;
549 if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled
550 if (s->chr)
551 qemu_chr_write(s->chr, &s->tx, 1);
552 else if (s->type == kbd && !s->disabled) {
553 handle_kbd_command(s, val);
554 }
555 }
556 s->rregs[R_STATUS] |= STATUS_TXEMPTY; // Tx buffer empty
557 s->rregs[R_SPEC] |= SPEC_ALLSENT; // All sent
558 set_txint(s);
559 break;
560 default:
561 break;
562 }
563 }
564
565 static uint32_t slavio_serial_mem_readb(void *opaque, target_phys_addr_t addr)
566 {
567 SerialState *serial = opaque;
568 ChannelState *s;
569 uint32_t saddr;
570 uint32_t ret;
571 int channel;
572
573 saddr = (addr & 3) >> 1;
574 channel = (addr & SERIAL_MAXADDR) >> 2;
575 s = &serial->chn[channel];
576 switch (saddr) {
577 case SERIAL_CTRL:
578 SER_DPRINTF("Read channel %c, reg[%d] = %2.2x\n", CHN_C(s), s->reg,
579 s->rregs[s->reg]);
580 ret = s->rregs[s->reg];
581 s->reg = 0;
582 return ret;
583 case SERIAL_DATA:
584 s->rregs[R_STATUS] &= ~STATUS_RXAV;
585 clr_rxint(s);
586 if (s->type == kbd || s->type == mouse)
587 ret = get_queue(s);
588 else
589 ret = s->rx;
590 SER_DPRINTF("Read channel %c, ch %d\n", CHN_C(s), ret);
591 if (s->chr)
592 qemu_chr_accept_input(s->chr);
593 return ret;
594 default:
595 break;
596 }
597 return 0;
598 }
599
600 static int serial_can_receive(void *opaque)
601 {
602 ChannelState *s = opaque;
603 int ret;
604
605 if (((s->wregs[W_RXCTRL] & RXCTRL_RXEN) == 0) // Rx not enabled
606 || ((s->rregs[R_STATUS] & STATUS_RXAV) == STATUS_RXAV))
607 // char already available
608 ret = 0;
609 else
610 ret = 1;
611 return ret;
612 }
613
614 static void serial_receive_byte(ChannelState *s, int ch)
615 {
616 SER_DPRINTF("channel %c put ch %d\n", CHN_C(s), ch);
617 s->rregs[R_STATUS] |= STATUS_RXAV;
618 s->rx = ch;
619 set_rxint(s);
620 }
621
622 static void serial_receive_break(ChannelState *s)
623 {
624 s->rregs[R_STATUS] |= STATUS_BRK;
625 slavio_serial_update_irq(s);
626 }
627
628 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
629 {
630 ChannelState *s = opaque;
631 serial_receive_byte(s, buf[0]);
632 }
633
634 static void serial_event(void *opaque, int event)
635 {
636 ChannelState *s = opaque;
637 if (event == CHR_EVENT_BREAK)
638 serial_receive_break(s);
639 }
640
641 static CPUReadMemoryFunc *slavio_serial_mem_read[3] = {
642 slavio_serial_mem_readb,
643 NULL,
644 NULL,
645 };
646
647 static CPUWriteMemoryFunc *slavio_serial_mem_write[3] = {
648 slavio_serial_mem_writeb,
649 NULL,
650 NULL,
651 };
652
653 static void slavio_serial_save_chn(QEMUFile *f, ChannelState *s)
654 {
655 int tmp;
656 tmp = 0;
657 qemu_put_be32s(f, &tmp); /* unused, was IRQ. */
658 qemu_put_be32s(f, &s->reg);
659 qemu_put_be32s(f, &s->rxint);
660 qemu_put_be32s(f, &s->txint);
661 qemu_put_be32s(f, &s->rxint_under_svc);
662 qemu_put_be32s(f, &s->txint_under_svc);
663 qemu_put_8s(f, &s->rx);
664 qemu_put_8s(f, &s->tx);
665 qemu_put_buffer(f, s->wregs, SERIAL_REGS);
666 qemu_put_buffer(f, s->rregs, SERIAL_REGS);
667 }
668
669 static void slavio_serial_save(QEMUFile *f, void *opaque)
670 {
671 SerialState *s = opaque;
672
673 slavio_serial_save_chn(f, &s->chn[0]);
674 slavio_serial_save_chn(f, &s->chn[1]);
675 }
676
677 static int slavio_serial_load_chn(QEMUFile *f, ChannelState *s, int version_id)
678 {
679 int tmp;
680
681 if (version_id > 2)
682 return -EINVAL;
683
684 qemu_get_be32s(f, &tmp); /* unused */
685 qemu_get_be32s(f, &s->reg);
686 qemu_get_be32s(f, &s->rxint);
687 qemu_get_be32s(f, &s->txint);
688 if (version_id >= 2) {
689 qemu_get_be32s(f, &s->rxint_under_svc);
690 qemu_get_be32s(f, &s->txint_under_svc);
691 }
692 qemu_get_8s(f, &s->rx);
693 qemu_get_8s(f, &s->tx);
694 qemu_get_buffer(f, s->wregs, SERIAL_REGS);
695 qemu_get_buffer(f, s->rregs, SERIAL_REGS);
696 return 0;
697 }
698
699 static int slavio_serial_load(QEMUFile *f, void *opaque, int version_id)
700 {
701 SerialState *s = opaque;
702 int ret;
703
704 ret = slavio_serial_load_chn(f, &s->chn[0], version_id);
705 if (ret != 0)
706 return ret;
707 ret = slavio_serial_load_chn(f, &s->chn[1], version_id);
708 return ret;
709
710 }
711
712 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
713 CharDriverState *chr1, CharDriverState *chr2)
714 {
715 int slavio_serial_io_memory, i;
716 SerialState *s;
717
718 s = qemu_mallocz(sizeof(SerialState));
719 if (!s)
720 return NULL;
721
722 slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read,
723 slavio_serial_mem_write,
724 s);
725 cpu_register_physical_memory(base, SERIAL_SIZE, slavio_serial_io_memory);
726
727 s->chn[0].chr = chr1;
728 s->chn[1].chr = chr2;
729 s->chn[0].disabled = 0;
730 s->chn[1].disabled = 0;
731
732 for (i = 0; i < 2; i++) {
733 s->chn[i].irq = irq;
734 s->chn[i].chn = 1 - i;
735 s->chn[i].type = ser;
736 if (s->chn[i].chr) {
737 qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
738 serial_receive1, serial_event, &s->chn[i]);
739 }
740 }
741 s->chn[0].otherchn = &s->chn[1];
742 s->chn[1].otherchn = &s->chn[0];
743 register_savevm("slavio_serial", base, 2, slavio_serial_save,
744 slavio_serial_load, s);
745 qemu_register_reset(slavio_serial_reset, s);
746 slavio_serial_reset(s);
747 return s;
748 }
749
750 static const uint8_t keycodes[128] = {
751 127, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 43, 53,
752 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 89, 76, 77, 78,
753 79, 80, 81, 82, 83, 84, 85, 86, 87, 42, 99, 88, 100, 101, 102, 103,
754 104, 105, 106, 107, 108, 109, 110, 47, 19, 121, 119, 5, 6, 8, 10, 12,
755 14, 16, 17, 18, 7, 98, 23, 68, 69, 70, 71, 91, 92, 93, 125, 112,
756 113, 114, 94, 50, 0, 0, 124, 9, 11, 0, 0, 0, 0, 0, 0, 0,
757 90, 0, 46, 22, 13, 111, 52, 20, 96, 24, 28, 74, 27, 123, 44, 66,
758 0, 45, 2, 4, 48, 0, 0, 21, 0, 0, 0, 0, 0, 120, 122, 67,
759 };
760
761 static const uint8_t e0_keycodes[128] = {
762 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
763 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 90, 76, 0, 0,
764 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
765 0, 0, 0, 0, 0, 109, 0, 0, 13, 0, 0, 0, 0, 0, 0, 0,
766 0, 0, 0, 0, 0, 0, 0, 68, 69, 70, 0, 91, 0, 93, 0, 112,
767 113, 114, 94, 50, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
768 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
769 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
770 };
771
772 static void sunkbd_event(void *opaque, int ch)
773 {
774 ChannelState *s = opaque;
775 int release = ch & 0x80;
776
777 KBD_DPRINTF("Untranslated keycode %2.2x (%s)\n", ch, release? "release" :
778 "press");
779 switch (ch) {
780 case 58: // Caps lock press
781 s->caps_lock_mode ^= 1;
782 if (s->caps_lock_mode == 2)
783 return; // Drop second press
784 break;
785 case 69: // Num lock press
786 s->num_lock_mode ^= 1;
787 if (s->num_lock_mode == 2)
788 return; // Drop second press
789 break;
790 case 186: // Caps lock release
791 s->caps_lock_mode ^= 2;
792 if (s->caps_lock_mode == 3)
793 return; // Drop first release
794 break;
795 case 197: // Num lock release
796 s->num_lock_mode ^= 2;
797 if (s->num_lock_mode == 3)
798 return; // Drop first release
799 break;
800 case 0xe0:
801 s->e0_mode = 1;
802 return;
803 default:
804 break;
805 }
806 if (s->e0_mode) {
807 s->e0_mode = 0;
808 ch = e0_keycodes[ch & 0x7f];
809 } else {
810 ch = keycodes[ch & 0x7f];
811 }
812 KBD_DPRINTF("Translated keycode %2.2x\n", ch);
813 put_queue(s, ch | release);
814 }
815
816 static void handle_kbd_command(ChannelState *s, int val)
817 {
818 KBD_DPRINTF("Command %d\n", val);
819 if (s->led_mode) { // Ignore led byte
820 s->led_mode = 0;
821 return;
822 }
823 switch (val) {
824 case 1: // Reset, return type code
825 clear_queue(s);
826 put_queue(s, 0xff);
827 put_queue(s, 4); // Type 4
828 put_queue(s, 0x7f);
829 break;
830 case 0xe: // Set leds
831 s->led_mode = 1;
832 break;
833 case 7: // Query layout
834 case 0xf:
835 clear_queue(s);
836 put_queue(s, 0xfe);
837 put_queue(s, 0); // XXX, layout?
838 break;
839 default:
840 break;
841 }
842 }
843
844 static void sunmouse_event(void *opaque,
845 int dx, int dy, int dz, int buttons_state)
846 {
847 ChannelState *s = opaque;
848 int ch;
849
850 MS_DPRINTF("dx=%d dy=%d buttons=%01x\n", dx, dy, buttons_state);
851
852 ch = 0x80 | 0x7; /* protocol start byte, no buttons pressed */
853
854 if (buttons_state & MOUSE_EVENT_LBUTTON)
855 ch ^= 0x4;
856 if (buttons_state & MOUSE_EVENT_MBUTTON)
857 ch ^= 0x2;
858 if (buttons_state & MOUSE_EVENT_RBUTTON)
859 ch ^= 0x1;
860
861 put_queue(s, ch);
862
863 ch = dx;
864
865 if (ch > 127)
866 ch=127;
867 else if (ch < -127)
868 ch=-127;
869
870 put_queue(s, ch & 0xff);
871
872 ch = -dy;
873
874 if (ch > 127)
875 ch=127;
876 else if (ch < -127)
877 ch=-127;
878
879 put_queue(s, ch & 0xff);
880
881 // MSC protocol specify two extra motion bytes
882
883 put_queue(s, 0);
884 put_queue(s, 0);
885 }
886
887 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
888 int disabled)
889 {
890 int slavio_serial_io_memory, i;
891 SerialState *s;
892
893 s = qemu_mallocz(sizeof(SerialState));
894 if (!s)
895 return;
896 for (i = 0; i < 2; i++) {
897 s->chn[i].irq = irq;
898 s->chn[i].chn = 1 - i;
899 s->chn[i].chr = NULL;
900 }
901 s->chn[0].otherchn = &s->chn[1];
902 s->chn[1].otherchn = &s->chn[0];
903 s->chn[0].type = mouse;
904 s->chn[1].type = kbd;
905 s->chn[0].disabled = disabled;
906 s->chn[1].disabled = disabled;
907
908 slavio_serial_io_memory = cpu_register_io_memory(0, slavio_serial_mem_read,
909 slavio_serial_mem_write,
910 s);
911 cpu_register_physical_memory(base, SERIAL_SIZE, slavio_serial_io_memory);
912
913 qemu_add_mouse_event_handler(sunmouse_event, &s->chn[0], 0,
914 "QEMU Sun Mouse");
915 qemu_add_kbd_event_handler(sunkbd_event, &s->chn[1]);
916 register_savevm("slavio_serial_mouse", base, 2, slavio_serial_save,
917 slavio_serial_load, s);
918 qemu_register_reset(slavio_serial_reset, s);
919 slavio_serial_reset(s);
920 }
kvm userspace components