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kvm: qemu: pci hotplug GPE support
[kvm-userspace.git] / qemu / hw / sun4m.c
blob79130c13da30604d44e26691cfa2f7052448dfa6
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "scsi.h"
35
36 //#define DEBUG_IRQ
37
38 /*
39 * Sun4m architecture was used in the following machines:
40 *
41 * SPARCserver 6xxMP/xx
42 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10)
43 * SPARCstation LX/ZX (4/30)
44 * SPARCstation Voyager
45 * SPARCstation 10/xx, SPARCserver 10/xx
46 * SPARCstation 5, SPARCserver 5
47 * SPARCstation 20/xx, SPARCserver 20
48 * SPARCstation 4
49 *
50 * Sun4d architecture was used in the following machines:
51 *
52 * SPARCcenter 2000
53 * SPARCserver 1000
54 *
55 * Sun4c architecture was used in the following machines:
56 * SPARCstation 1/1+, SPARCserver 1/1+
57 * SPARCstation SLC
58 * SPARCstation IPC
59 * SPARCstation ELC
60 * SPARCstation IPX
61 *
62 * See for example: http://www.sunhelp.org/faq/sunref1.html
63 */
64
65 #ifdef DEBUG_IRQ
66 #define DPRINTF(fmt, args...) \
67 do { printf("CPUIRQ: " fmt , ##args); } while (0)
68 #else
69 #define DPRINTF(fmt, args...)
70 #endif
71
72 #define KERNEL_LOAD_ADDR 0x00004000
73 #define CMDLINE_ADDR 0x007ff000
74 #define INITRD_LOAD_ADDR 0x00800000
75 #define PROM_SIZE_MAX (512 * 1024)
76 #define PROM_VADDR 0xffd00000
77 #define PROM_FILENAME "openbios-sparc32"
78
79 #define MAX_CPUS 16
80 #define MAX_PILS 16
81
82 struct hwdef {
83 target_phys_addr_t iommu_base, slavio_base;
84 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
85 target_phys_addr_t serial_base, fd_base;
86 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
87 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
88 target_phys_addr_t ecc_base;
89 uint32_t ecc_version;
90 target_phys_addr_t sun4c_intctl_base, sun4c_counter_base;
91 long vram_size, nvram_size;
92 // IRQ numbers are not PIL ones, but master interrupt controller
93 // register bit numbers
94 int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq;
95 int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq, ecc_irq;
96 int machine_id; // For NVRAM
97 uint32_t iommu_version;
98 uint32_t intbit_to_level[32];
99 uint64_t max_mem;
100 const char * const default_cpu_model;
101 };
102
103 #define MAX_IOUNITS 5
104
105 struct sun4d_hwdef {
106 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
107 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
108 target_phys_addr_t serial_base;
109 target_phys_addr_t espdma_base, esp_base;
110 target_phys_addr_t ledma_base, le_base;
111 target_phys_addr_t tcx_base;
112 target_phys_addr_t sbi_base;
113 unsigned long vram_size, nvram_size;
114 // IRQ numbers are not PIL ones, but SBI register bit numbers
115 int esp_irq, le_irq, clock_irq, clock1_irq;
116 int ser_irq, ms_kb_irq, me_irq;
117 int machine_id; // For NVRAM
118 uint32_t iounit_version;
119 uint64_t max_mem;
120 const char * const default_cpu_model;
121 };
122
123 /* TSC handling */
124
125 uint64_t cpu_get_tsc()
126 {
127 return qemu_get_clock(vm_clock);
128 }
129
130 int DMA_get_channel_mode (int nchan)
131 {
132 return 0;
133 }
134 int DMA_read_memory (int nchan, void *buf, int pos, int size)
135 {
136 return 0;
137 }
138 int DMA_write_memory (int nchan, void *buf, int pos, int size)
139 {
140 return 0;
141 }
142 void DMA_hold_DREQ (int nchan) {}
143 void DMA_release_DREQ (int nchan) {}
144 void DMA_schedule(int nchan) {}
145 void DMA_run (void) {}
146 void DMA_init (int high_page_enable) {}
147 void DMA_register_channel (int nchan,
148 DMA_transfer_handler transfer_handler,
149 void *opaque)
150 {
151 }
152
153 extern int nographic;
154
155 static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline,
156 const char *boot_devices, uint32_t RAM_size,
157 uint32_t kernel_size,
158 int width, int height, int depth,
159 int machine_id, const char *arch)
160 {
161 unsigned int i;
162 uint32_t start, end;
163 uint8_t image[0x1ff0];
164 ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ
165 struct sparc_arch_cfg *sparc_header;
166 struct OpenBIOS_nvpart_v1 *part_header;
167
168 memset(image, '\0', sizeof(image));
169
170 // Try to match PPC NVRAM
171 strcpy(header->struct_ident, "QEMU_BIOS");
172 header->struct_version = cpu_to_be32(3); /* structure v3 */
173
174 header->nvram_size = cpu_to_be16(0x2000);
175 header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
176 header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
177 strcpy(header->arch, arch);
178 header->nb_cpus = smp_cpus & 0xff;
179 header->RAM0_base = 0;
180 header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
181 strcpy(header->boot_devices, boot_devices);
182 header->nboot_devices = strlen(boot_devices) & 0xff;
183 header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR);
184 header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
185 if (cmdline) {
186 strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);
187 header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
188 header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
189 }
190 // XXX add initrd_image, initrd_size
191 header->width = cpu_to_be16(width);
192 header->height = cpu_to_be16(height);
193 header->depth = cpu_to_be16(depth);
194 if (nographic)
195 header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
196
197 header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
198
199 // Architecture specific header
200 start = sizeof(ohwcfg_v3_t);
201 sparc_header = (struct sparc_arch_cfg *)&image[start];
202 sparc_header->valid = 0;
203 start += sizeof(struct sparc_arch_cfg);
204
205 // OpenBIOS nvram variables
206 // Variable partition
207 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
208 part_header->signature = OPENBIOS_PART_SYSTEM;
209 strcpy(part_header->name, "system");
210
211 end = start + sizeof(struct OpenBIOS_nvpart_v1);
212 for (i = 0; i < nb_prom_envs; i++)
213 end = OpenBIOS_set_var(image, end, prom_envs[i]);
214
215 // End marker
216 image[end++] = '\0';
217
218 end = start + ((end - start + 15) & ~15);
219 OpenBIOS_finish_partition(part_header, end - start);
220
221 // free partition
222 start = end;
223 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
224 part_header->signature = OPENBIOS_PART_FREE;
225 strcpy(part_header->name, "free");
226
227 end = 0x1fd0;
228 OpenBIOS_finish_partition(part_header, end - start);
229
230 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id);
231
232 for (i = 0; i < sizeof(image); i++)
233 m48t59_write(nvram, i, image[i]);
234 }
235
236 static void *slavio_intctl;
237
238 void pic_info()
239 {
240 if (slavio_intctl)
241 slavio_pic_info(slavio_intctl);
242 }
243
244 void irq_info()
245 {
246 if (slavio_intctl)
247 slavio_irq_info(slavio_intctl);
248 }
249
250 void cpu_check_irqs(CPUState *env)
251 {
252 if (env->pil_in && (env->interrupt_index == 0 ||
253 (env->interrupt_index & ~15) == TT_EXTINT)) {
254 unsigned int i;
255
256 for (i = 15; i > 0; i--) {
257 if (env->pil_in & (1 << i)) {
258 int old_interrupt = env->interrupt_index;
259
260 env->interrupt_index = TT_EXTINT | i;
261 if (old_interrupt != env->interrupt_index)
262 cpu_interrupt(env, CPU_INTERRUPT_HARD);
263 break;
264 }
265 }
266 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
267 env->interrupt_index = 0;
268 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
269 }
270 }
271
272 static void cpu_set_irq(void *opaque, int irq, int level)
273 {
274 CPUState *env = opaque;
275
276 if (level) {
277 DPRINTF("Raise CPU IRQ %d\n", irq);
278 env->halted = 0;
279 env->pil_in |= 1 << irq;
280 cpu_check_irqs(env);
281 } else {
282 DPRINTF("Lower CPU IRQ %d\n", irq);
283 env->pil_in &= ~(1 << irq);
284 cpu_check_irqs(env);
285 }
286 }
287
288 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
289 {
290 }
291
292 static void *slavio_misc;
293
294 void qemu_system_powerdown(void)
295 {
296 slavio_set_power_fail(slavio_misc, 1);
297 }
298
299 static void main_cpu_reset(void *opaque)
300 {
301 CPUState *env = opaque;
302
303 cpu_reset(env);
304 env->halted = 0;
305 }
306
307 static void secondary_cpu_reset(void *opaque)
308 {
309 CPUState *env = opaque;
310
311 cpu_reset(env);
312 env->halted = 1;
313 }
314
315 static unsigned long sun4m_load_kernel(const char *kernel_filename,
316 const char *kernel_cmdline,
317 const char *initrd_filename)
318 {
319 int linux_boot;
320 unsigned int i;
321 long initrd_size, kernel_size;
322
323 linux_boot = (kernel_filename != NULL);
324
325 kernel_size = 0;
326 if (linux_boot) {
327 kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL,
328 NULL);
329 if (kernel_size < 0)
330 kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
331 if (kernel_size < 0)
332 kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);
333 if (kernel_size < 0) {
334 fprintf(stderr, "qemu: could not load kernel '%s'\n",
335 kernel_filename);
336 exit(1);
337 }
338
339 /* load initrd */
340 initrd_size = 0;
341 if (initrd_filename) {
342 initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);
343 if (initrd_size < 0) {
344 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
345 initrd_filename);
346 exit(1);
347 }
348 }
349 if (initrd_size > 0) {
350 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
351 if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)
352 == 0x48647253) { // HdrS
353 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
354 stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);
355 break;
356 }
357 }
358 }
359 }
360 return kernel_size;
361 }
362
363 static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size,
364 const char *boot_device,
365 DisplayState *ds, const char *kernel_filename,
366 const char *kernel_cmdline,
367 const char *initrd_filename, const char *cpu_model)
368
369 {
370 CPUState *env, *envs[MAX_CPUS];
371 unsigned int i;
372 void *iommu, *espdma, *ledma, *main_esp, *nvram;
373 qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq,
374 *espdma_irq, *ledma_irq;
375 qemu_irq *esp_reset, *le_reset;
376 unsigned long prom_offset, kernel_size;
377 int ret;
378 char buf[1024];
379 BlockDriverState *fd[MAX_FD];
380 int index;
381
382 /* init CPUs */
383 if (!cpu_model)
384 cpu_model = hwdef->default_cpu_model;
385
386 for(i = 0; i < smp_cpus; i++) {
387 env = cpu_init(cpu_model);
388 if (!env) {
389 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
390 exit(1);
391 }
392 cpu_sparc_set_id(env, i);
393 envs[i] = env;
394 if (i == 0) {
395 qemu_register_reset(main_cpu_reset, env);
396 } else {
397 qemu_register_reset(secondary_cpu_reset, env);
398 env->halted = 1;
399 }
400 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
401 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
402 env->prom_addr = hwdef->slavio_base;
403 }
404
405 for (i = smp_cpus; i < MAX_CPUS; i++)
406 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
407
408
409 /* allocate RAM */
410 if ((uint64_t)RAM_size > hwdef->max_mem) {
411 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
412 (unsigned int)RAM_size / (1024 * 1024),
413 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
414 exit(1);
415 }
416 cpu_register_physical_memory(0, RAM_size, 0);
417
418 /* load boot prom */
419 prom_offset = RAM_size + hwdef->vram_size;
420 cpu_register_physical_memory(hwdef->slavio_base,
421 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
422 TARGET_PAGE_MASK,
423 prom_offset | IO_MEM_ROM);
424
425 if (bios_name == NULL)
426 bios_name = PROM_FILENAME;
427 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
428 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
429 if (ret < 0 || ret > PROM_SIZE_MAX)
430 ret = load_image(buf, phys_ram_base + prom_offset);
431 if (ret < 0 || ret > PROM_SIZE_MAX) {
432 fprintf(stderr, "qemu: could not load prom '%s'\n",
433 buf);
434 exit(1);
435 }
436 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
437
438 /* set up devices */
439 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
440 hwdef->intctl_base + 0x10000ULL,
441 &hwdef->intbit_to_level[0],
442 &slavio_irq, &slavio_cpu_irq,
443 cpu_irqs,
444 hwdef->clock_irq);
445
446 if (hwdef->idreg_base != (target_phys_addr_t)-1) {
447 stl_raw(phys_ram_base + prom_offset, 0xfe810103);
448
449 cpu_register_physical_memory(hwdef->idreg_base, sizeof(uint32_t),
450 prom_offset | IO_MEM_ROM);
451 }
452
453 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
454 slavio_irq[hwdef->me_irq]);
455
456 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
457 iommu, &espdma_irq, &esp_reset);
458
459 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
460 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
461 &le_reset);
462
463 if (graphic_depth != 8 && graphic_depth != 24) {
464 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
465 exit (1);
466 }
467 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
468 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
469
470 if (nd_table[0].model == NULL
471 || strcmp(nd_table[0].model, "lance") == 0) {
472 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
473 } else if (strcmp(nd_table[0].model, "?") == 0) {
474 fprintf(stderr, "qemu: Supported NICs: lance\n");
475 exit (1);
476 } else {
477 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
478 exit (1);
479 }
480
481 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
482 hwdef->nvram_size, 8);
483
484 slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq],
485 slavio_cpu_irq, smp_cpus);
486
487 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
488 nographic);
489 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
490 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
491 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
492 serial_hds[1], serial_hds[0]);
493
494 if (hwdef->fd_base != (target_phys_addr_t)-1) {
495 /* there is zero or one floppy drive */
496 memset(fd, 0, sizeof(fd));
497 index = drive_get_index(IF_FLOPPY, 0, 0);
498 if (index != -1)
499 fd[0] = drives_table[index].bdrv;
500
501 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd);
502 }
503
504 if (drive_get_max_bus(IF_SCSI) > 0) {
505 fprintf(stderr, "qemu: too many SCSI bus\n");
506 exit(1);
507 }
508
509 main_esp = esp_init(hwdef->esp_base,
510 espdma_memory_read, espdma_memory_write,
511 espdma, *espdma_irq, esp_reset);
512
513 for (i = 0; i < ESP_MAX_DEVS; i++) {
514 index = drive_get_index(IF_SCSI, 0, i);
515 if (index == -1)
516 continue;
517 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
518 }
519
520 slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->apc_base,
521 hwdef->aux1_base, hwdef->aux2_base,
522 slavio_irq[hwdef->me_irq], envs[0]);
523 if (hwdef->cs_base != (target_phys_addr_t)-1)
524 cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl);
525
526 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
527 initrd_filename);
528
529 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
530 boot_device, RAM_size, kernel_size, graphic_width,
531 graphic_height, graphic_depth, hwdef->machine_id, "Sun4m");
532
533 if (hwdef->ecc_base != (target_phys_addr_t)-1)
534 ecc_init(hwdef->ecc_base, slavio_irq[hwdef->ecc_irq],
535 hwdef->ecc_version);
536 }
537
538 static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size,
539 const char *boot_device,
540 DisplayState *ds, const char *kernel_filename,
541 const char *kernel_cmdline,
542 const char *initrd_filename, const char *cpu_model)
543 {
544 CPUState *env;
545 unsigned int i;
546 void *iommu, *espdma, *ledma, *main_esp, *nvram;
547 qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq;
548 qemu_irq *esp_reset, *le_reset;
549 unsigned long prom_offset, kernel_size;
550 int ret;
551 char buf[1024];
552 BlockDriverState *fd[MAX_FD];
553 int index;
554
555 /* init CPU */
556 if (!cpu_model)
557 cpu_model = hwdef->default_cpu_model;
558
559 env = cpu_init(cpu_model);
560 if (!env) {
561 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
562 exit(1);
563 }
564
565 cpu_sparc_set_id(env, 0);
566
567 qemu_register_reset(main_cpu_reset, env);
568 register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
569 cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
570 env->prom_addr = hwdef->slavio_base;
571
572 /* allocate RAM */
573 if ((uint64_t)RAM_size > hwdef->max_mem) {
574 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
575 (unsigned int)RAM_size / (1024 * 1024),
576 (unsigned int)hwdef->max_mem / (1024 * 1024));
577 exit(1);
578 }
579 cpu_register_physical_memory(0, RAM_size, 0);
580
581 /* load boot prom */
582 prom_offset = RAM_size + hwdef->vram_size;
583 cpu_register_physical_memory(hwdef->slavio_base,
584 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
585 TARGET_PAGE_MASK,
586 prom_offset | IO_MEM_ROM);
587
588 if (bios_name == NULL)
589 bios_name = PROM_FILENAME;
590 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
591 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
592 if (ret < 0 || ret > PROM_SIZE_MAX)
593 ret = load_image(buf, phys_ram_base + prom_offset);
594 if (ret < 0 || ret > PROM_SIZE_MAX) {
595 fprintf(stderr, "qemu: could not load prom '%s'\n",
596 buf);
597 exit(1);
598 }
599 prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
600
601 /* set up devices */
602 slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base,
603 &slavio_irq, cpu_irqs);
604
605 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
606 slavio_irq[hwdef->me_irq]);
607
608 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq],
609 iommu, &espdma_irq, &esp_reset);
610
611 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
612 slavio_irq[hwdef->le_irq], iommu, &ledma_irq,
613 &le_reset);
614
615 if (graphic_depth != 8 && graphic_depth != 24) {
616 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
617 exit (1);
618 }
619 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
620 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
621
622 if (nd_table[0].model == NULL
623 || strcmp(nd_table[0].model, "lance") == 0) {
624 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
625 } else if (strcmp(nd_table[0].model, "?") == 0) {
626 fprintf(stderr, "qemu: Supported NICs: lance\n");
627 exit (1);
628 } else {
629 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
630 exit (1);
631 }
632
633 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0,
634 hwdef->nvram_size, 2);
635
636 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq],
637 nographic);
638 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
639 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
640 slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq],
641 serial_hds[1], serial_hds[0]);
642
643 if (hwdef->fd_base != (target_phys_addr_t)-1) {
644 /* there is zero or one floppy drive */
645 fd[1] = fd[0] = NULL;
646 index = drive_get_index(IF_FLOPPY, 0, 0);
647 if (index != -1)
648 fd[0] = drives_table[index].bdrv;
649
650 sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd);
651 }
652
653 if (drive_get_max_bus(IF_SCSI) > 0) {
654 fprintf(stderr, "qemu: too many SCSI bus\n");
655 exit(1);
656 }
657
658 main_esp = esp_init(hwdef->esp_base,
659 espdma_memory_read, espdma_memory_write,
660 espdma, *espdma_irq, esp_reset);
661
662 for (i = 0; i < ESP_MAX_DEVS; i++) {
663 index = drive_get_index(IF_SCSI, 0, i);
664 if (index == -1)
665 continue;
666 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
667 }
668
669 slavio_misc = slavio_misc_init(-1, hwdef->apc_base,
670 hwdef->aux1_base, hwdef->aux2_base,
671 slavio_irq[hwdef->me_irq], env);
672
673 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
674 initrd_filename);
675
676 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
677 boot_device, RAM_size, kernel_size, graphic_width,
678 graphic_height, graphic_depth, hwdef->machine_id, "Sun4c");
679 }
680
681 static const struct hwdef hwdefs[] = {
682 /* SS-5 */
683 {
684 .iommu_base = 0x10000000,
685 .tcx_base = 0x50000000,
686 .cs_base = 0x6c000000,
687 .slavio_base = 0x70000000,
688 .ms_kb_base = 0x71000000,
689 .serial_base = 0x71100000,
690 .nvram_base = 0x71200000,
691 .fd_base = 0x71400000,
692 .counter_base = 0x71d00000,
693 .intctl_base = 0x71e00000,
694 .idreg_base = 0x78000000,
695 .dma_base = 0x78400000,
696 .esp_base = 0x78800000,
697 .le_base = 0x78c00000,
698 .apc_base = 0x6a000000,
699 .aux1_base = 0x71900000,
700 .aux2_base = 0x71910000,
701 .ecc_base = -1,
702 .sun4c_intctl_base = -1,
703 .sun4c_counter_base = -1,
704 .vram_size = 0x00100000,
705 .nvram_size = 0x2000,
706 .esp_irq = 18,
707 .le_irq = 16,
708 .clock_irq = 7,
709 .clock1_irq = 19,
710 .ms_kb_irq = 14,
711 .ser_irq = 15,
712 .fd_irq = 22,
713 .me_irq = 30,
714 .cs_irq = 5,
715 .machine_id = 0x80,
716 .iommu_version = 0x05000000,
717 .intbit_to_level = {
718 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
719 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
720 },
721 .max_mem = 0x10000000,
722 .default_cpu_model = "Fujitsu MB86904",
723 },
724 /* SS-10 */
725 {
726 .iommu_base = 0xfe0000000ULL,
727 .tcx_base = 0xe20000000ULL,
728 .cs_base = -1,
729 .slavio_base = 0xff0000000ULL,
730 .ms_kb_base = 0xff1000000ULL,
731 .serial_base = 0xff1100000ULL,
732 .nvram_base = 0xff1200000ULL,
733 .fd_base = 0xff1700000ULL,
734 .counter_base = 0xff1300000ULL,
735 .intctl_base = 0xff1400000ULL,
736 .idreg_base = 0xef0000000ULL,
737 .dma_base = 0xef0400000ULL,
738 .esp_base = 0xef0800000ULL,
739 .le_base = 0xef0c00000ULL,
740 .apc_base = 0xefa000000ULL, // XXX should not exist
741 .aux1_base = 0xff1800000ULL,
742 .aux2_base = 0xff1a01000ULL,
743 .ecc_base = 0xf00000000ULL,
744 .ecc_version = 0x10000000, // version 0, implementation 1
745 .sun4c_intctl_base = -1,
746 .sun4c_counter_base = -1,
747 .vram_size = 0x00100000,
748 .nvram_size = 0x2000,
749 .esp_irq = 18,
750 .le_irq = 16,
751 .clock_irq = 7,
752 .clock1_irq = 19,
753 .ms_kb_irq = 14,
754 .ser_irq = 15,
755 .fd_irq = 22,
756 .me_irq = 30,
757 .cs_irq = -1,
758 .ecc_irq = 28,
759 .machine_id = 0x72,
760 .iommu_version = 0x03000000,
761 .intbit_to_level = {
762 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
763 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
764 },
765 .max_mem = 0xffffffff, // XXX actually first 62GB ok
766 .default_cpu_model = "TI SuperSparc II",
767 },
768 /* SS-600MP */
769 {
770 .iommu_base = 0xfe0000000ULL,
771 .tcx_base = 0xe20000000ULL,
772 .cs_base = -1,
773 .slavio_base = 0xff0000000ULL,
774 .ms_kb_base = 0xff1000000ULL,
775 .serial_base = 0xff1100000ULL,
776 .nvram_base = 0xff1200000ULL,
777 .fd_base = -1,
778 .counter_base = 0xff1300000ULL,
779 .intctl_base = 0xff1400000ULL,
780 .idreg_base = -1,
781 .dma_base = 0xef0081000ULL,
782 .esp_base = 0xef0080000ULL,
783 .le_base = 0xef0060000ULL,
784 .apc_base = 0xefa000000ULL, // XXX should not exist
785 .aux1_base = 0xff1800000ULL,
786 .aux2_base = 0xff1a01000ULL, // XXX should not exist
787 .ecc_base = 0xf00000000ULL,
788 .ecc_version = 0x00000000, // version 0, implementation 0
789 .sun4c_intctl_base = -1,
790 .sun4c_counter_base = -1,
791 .vram_size = 0x00100000,
792 .nvram_size = 0x2000,
793 .esp_irq = 18,
794 .le_irq = 16,
795 .clock_irq = 7,
796 .clock1_irq = 19,
797 .ms_kb_irq = 14,
798 .ser_irq = 15,
799 .fd_irq = 22,
800 .me_irq = 30,
801 .cs_irq = -1,
802 .ecc_irq = 28,
803 .machine_id = 0x71,
804 .iommu_version = 0x01000000,
805 .intbit_to_level = {
806 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
807 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
808 },
809 .max_mem = 0xffffffff, // XXX actually first 62GB ok
810 .default_cpu_model = "TI SuperSparc II",
811 },
812 /* SS-20 */
813 {
814 .iommu_base = 0xfe0000000ULL,
815 .tcx_base = 0xe20000000ULL,
816 .cs_base = -1,
817 .slavio_base = 0xff0000000ULL,
818 .ms_kb_base = 0xff1000000ULL,
819 .serial_base = 0xff1100000ULL,
820 .nvram_base = 0xff1200000ULL,
821 .fd_base = 0xff1700000ULL,
822 .counter_base = 0xff1300000ULL,
823 .intctl_base = 0xff1400000ULL,
824 .idreg_base = 0xef0000000ULL,
825 .dma_base = 0xef0400000ULL,
826 .esp_base = 0xef0800000ULL,
827 .le_base = 0xef0c00000ULL,
828 .apc_base = 0xefa000000ULL, // XXX should not exist
829 .aux1_base = 0xff1800000ULL,
830 .aux2_base = 0xff1a01000ULL,
831 .ecc_base = 0xf00000000ULL,
832 .ecc_version = 0x20000000, // version 0, implementation 2
833 .sun4c_intctl_base = -1,
834 .sun4c_counter_base = -1,
835 .vram_size = 0x00100000,
836 .nvram_size = 0x2000,
837 .esp_irq = 18,
838 .le_irq = 16,
839 .clock_irq = 7,
840 .clock1_irq = 19,
841 .ms_kb_irq = 14,
842 .ser_irq = 15,
843 .fd_irq = 22,
844 .me_irq = 30,
845 .cs_irq = -1,
846 .ecc_irq = 28,
847 .machine_id = 0x72,
848 .iommu_version = 0x13000000,
849 .intbit_to_level = {
850 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12,
851 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0,
852 },
853 .max_mem = 0xffffffff, // XXX actually first 62GB ok
854 .default_cpu_model = "TI SuperSparc II",
855 },
856 /* SS-2 */
857 {
858 .iommu_base = 0xf8000000,
859 .tcx_base = 0xfe000000,
860 .cs_base = -1,
861 .slavio_base = 0xf6000000,
862 .ms_kb_base = 0xf0000000,
863 .serial_base = 0xf1000000,
864 .nvram_base = 0xf2000000,
865 .fd_base = 0xf7200000,
866 .counter_base = -1,
867 .intctl_base = -1,
868 .dma_base = 0xf8400000,
869 .esp_base = 0xf8800000,
870 .le_base = 0xf8c00000,
871 .apc_base = -1,
872 .aux1_base = 0xf7400003,
873 .aux2_base = -1,
874 .sun4c_intctl_base = 0xf5000000,
875 .sun4c_counter_base = 0xf3000000,
876 .vram_size = 0x00100000,
877 .nvram_size = 0x800,
878 .esp_irq = 2,
879 .le_irq = 3,
880 .clock_irq = 5,
881 .clock1_irq = 7,
882 .ms_kb_irq = 1,
883 .ser_irq = 1,
884 .fd_irq = 1,
885 .me_irq = 1,
886 .cs_irq = -1,
887 .machine_id = 0x55,
888 .max_mem = 0x10000000,
889 .default_cpu_model = "Cypress CY7C601",
890 },
891 };
892
893 /* SPARCstation 5 hardware initialisation */
894 static void ss5_init(int RAM_size, int vga_ram_size,
895 const char *boot_device, DisplayState *ds,
896 const char *kernel_filename, const char *kernel_cmdline,
897 const char *initrd_filename, const char *cpu_model)
898 {
899 sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
900 kernel_cmdline, initrd_filename, cpu_model);
901 }
902
903 /* SPARCstation 10 hardware initialisation */
904 static void ss10_init(int RAM_size, int vga_ram_size,
905 const char *boot_device, DisplayState *ds,
906 const char *kernel_filename, const char *kernel_cmdline,
907 const char *initrd_filename, const char *cpu_model)
908 {
909 sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
910 kernel_cmdline, initrd_filename, cpu_model);
911 }
912
913 /* SPARCserver 600MP hardware initialisation */
914 static void ss600mp_init(int RAM_size, int vga_ram_size,
915 const char *boot_device, DisplayState *ds,
916 const char *kernel_filename, const char *kernel_cmdline,
917 const char *initrd_filename, const char *cpu_model)
918 {
919 sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename,
920 kernel_cmdline, initrd_filename, cpu_model);
921 }
922
923 /* SPARCstation 20 hardware initialisation */
924 static void ss20_init(int RAM_size, int vga_ram_size,
925 const char *boot_device, DisplayState *ds,
926 const char *kernel_filename, const char *kernel_cmdline,
927 const char *initrd_filename, const char *cpu_model)
928 {
929 sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename,
930 kernel_cmdline, initrd_filename, cpu_model);
931 }
932
933 /* SPARCstation 2 hardware initialisation */
934 static void ss2_init(int RAM_size, int vga_ram_size,
935 const char *boot_device, DisplayState *ds,
936 const char *kernel_filename, const char *kernel_cmdline,
937 const char *initrd_filename, const char *cpu_model)
938 {
939 sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename,
940 kernel_cmdline, initrd_filename, cpu_model);
941 }
942
943 QEMUMachine ss5_machine = {
944 "SS-5",
945 "Sun4m platform, SPARCstation 5",
946 ss5_init,
947 };
948
949 QEMUMachine ss10_machine = {
950 "SS-10",
951 "Sun4m platform, SPARCstation 10",
952 ss10_init,
953 };
954
955 QEMUMachine ss600mp_machine = {
956 "SS-600MP",
957 "Sun4m platform, SPARCserver 600MP",
958 ss600mp_init,
959 };
960
961 QEMUMachine ss20_machine = {
962 "SS-20",
963 "Sun4m platform, SPARCstation 20",
964 ss20_init,
965 };
966
967 QEMUMachine ss2_machine = {
968 "SS-2",
969 "Sun4c platform, SPARCstation 2",
970 ss2_init,
971 };
972
973 static const struct sun4d_hwdef sun4d_hwdefs[] = {
974 /* SS-1000 */
975 {
976 .iounit_bases = {
977 0xfe0200000ULL,
978 0xfe1200000ULL,
979 0xfe2200000ULL,
980 0xfe3200000ULL,
981 -1,
982 },
983 .tcx_base = 0x820000000ULL,
984 .slavio_base = 0xf00000000ULL,
985 .ms_kb_base = 0xf00240000ULL,
986 .serial_base = 0xf00200000ULL,
987 .nvram_base = 0xf00280000ULL,
988 .counter_base = 0xf00300000ULL,
989 .espdma_base = 0x800081000ULL,
990 .esp_base = 0x800080000ULL,
991 .ledma_base = 0x800040000ULL,
992 .le_base = 0x800060000ULL,
993 .sbi_base = 0xf02800000ULL,
994 .vram_size = 0x00100000,
995 .nvram_size = 0x2000,
996 .esp_irq = 3,
997 .le_irq = 4,
998 .clock_irq = 14,
999 .clock1_irq = 10,
1000 .ms_kb_irq = 12,
1001 .ser_irq = 12,
1002 .machine_id = 0x80,
1003 .iounit_version = 0x03000000,
1004 .max_mem = 0xffffffff, // XXX actually first 62GB ok
1005 .default_cpu_model = "TI SuperSparc II",
1006 },
1007 /* SS-2000 */
1008 {
1009 .iounit_bases = {
1010 0xfe0200000ULL,
1011 0xfe1200000ULL,
1012 0xfe2200000ULL,
1013 0xfe3200000ULL,
1014 0xfe4200000ULL,
1015 },
1016 .tcx_base = 0x820000000ULL,
1017 .slavio_base = 0xf00000000ULL,
1018 .ms_kb_base = 0xf00240000ULL,
1019 .serial_base = 0xf00200000ULL,
1020 .nvram_base = 0xf00280000ULL,
1021 .counter_base = 0xf00300000ULL,
1022 .espdma_base = 0x800081000ULL,
1023 .esp_base = 0x800080000ULL,
1024 .ledma_base = 0x800040000ULL,
1025 .le_base = 0x800060000ULL,
1026 .sbi_base = 0xf02800000ULL,
1027 .vram_size = 0x00100000,
1028 .nvram_size = 0x2000,
1029 .esp_irq = 3,
1030 .le_irq = 4,
1031 .clock_irq = 14,
1032 .clock1_irq = 10,
1033 .ms_kb_irq = 12,
1034 .ser_irq = 12,
1035 .machine_id = 0x80,
1036 .iounit_version = 0x03000000,
1037 .max_mem = 0xffffffff, // XXX actually first 62GB ok
1038 .default_cpu_model = "TI SuperSparc II",
1039 },
1040 };
1041
1042 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size,
1043 const char *boot_device,
1044 DisplayState *ds, const char *kernel_filename,
1045 const char *kernel_cmdline,
1046 const char *initrd_filename, const char *cpu_model)
1047 {
1048 CPUState *env, *envs[MAX_CPUS];
1049 unsigned int i;
1050 void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi;
1051 qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq,
1052 *espdma_irq, *ledma_irq;
1053 qemu_irq *esp_reset, *le_reset;
1054 unsigned long prom_offset, kernel_size;
1055 int ret;
1056 char buf[1024];
1057 int index;
1058
1059 /* init CPUs */
1060 if (!cpu_model)
1061 cpu_model = hwdef->default_cpu_model;
1062
1063 for (i = 0; i < smp_cpus; i++) {
1064 env = cpu_init(cpu_model);
1065 if (!env) {
1066 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
1067 exit(1);
1068 }
1069 cpu_sparc_set_id(env, i);
1070 envs[i] = env;
1071 if (i == 0) {
1072 qemu_register_reset(main_cpu_reset, env);
1073 } else {
1074 qemu_register_reset(secondary_cpu_reset, env);
1075 env->halted = 1;
1076 }
1077 register_savevm("cpu", i, 3, cpu_save, cpu_load, env);
1078 cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS);
1079 env->prom_addr = hwdef->slavio_base;
1080 }
1081
1082 for (i = smp_cpus; i < MAX_CPUS; i++)
1083 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1084
1085 /* allocate RAM */
1086 if ((uint64_t)RAM_size > hwdef->max_mem) {
1087 fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n",
1088 (unsigned int)RAM_size / (1024 * 1024),
1089 (unsigned int)(hwdef->max_mem / (1024 * 1024)));
1090 exit(1);
1091 }
1092 cpu_register_physical_memory(0, RAM_size, 0);
1093
1094 /* load boot prom */
1095 prom_offset = RAM_size + hwdef->vram_size;
1096 cpu_register_physical_memory(hwdef->slavio_base,
1097 (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) &
1098 TARGET_PAGE_MASK,
1099 prom_offset | IO_MEM_ROM);
1100
1101 if (bios_name == NULL)
1102 bios_name = PROM_FILENAME;
1103 snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
1104 ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL);
1105 if (ret < 0 || ret > PROM_SIZE_MAX)
1106 ret = load_image(buf, phys_ram_base + prom_offset);
1107 if (ret < 0 || ret > PROM_SIZE_MAX) {
1108 fprintf(stderr, "qemu: could not load prom '%s'\n",
1109 buf);
1110 exit(1);
1111 }
1112
1113 /* set up devices */
1114 sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs);
1115
1116 for (i = 0; i < MAX_IOUNITS; i++)
1117 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1118 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1119 hwdef->iounit_version,
1120 sbi_irq[hwdef->me_irq]);
1121
1122 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq],
1123 iounits[0], &espdma_irq, &esp_reset);
1124
1125 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq],
1126 iounits[0], &ledma_irq, &le_reset);
1127
1128 if (graphic_depth != 8 && graphic_depth != 24) {
1129 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1130 exit (1);
1131 }
1132 tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size,
1133 hwdef->vram_size, graphic_width, graphic_height, graphic_depth);
1134
1135 if (nd_table[0].model == NULL
1136 || strcmp(nd_table[0].model, "lance") == 0) {
1137 lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset);
1138 } else if (strcmp(nd_table[0].model, "?") == 0) {
1139 fprintf(stderr, "qemu: Supported NICs: lance\n");
1140 exit (1);
1141 } else {
1142 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
1143 exit (1);
1144 }
1145
1146 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0,
1147 hwdef->nvram_size, 8);
1148
1149 slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq],
1150 sbi_cpu_irq, smp_cpus);
1151
1152 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq],
1153 nographic);
1154 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1155 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1156 slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq],
1157 serial_hds[1], serial_hds[0]);
1158
1159 if (drive_get_max_bus(IF_SCSI) > 0) {
1160 fprintf(stderr, "qemu: too many SCSI bus\n");
1161 exit(1);
1162 }
1163
1164 main_esp = esp_init(hwdef->esp_base,
1165 espdma_memory_read, espdma_memory_write,
1166 espdma, *espdma_irq, esp_reset);
1167
1168 for (i = 0; i < ESP_MAX_DEVS; i++) {
1169 index = drive_get_index(IF_SCSI, 0, i);
1170 if (index == -1)
1171 continue;
1172 esp_scsi_attach(main_esp, drives_table[index].bdrv, i);
1173 }
1174
1175 kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline,
1176 initrd_filename);
1177
1178 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1179 boot_device, RAM_size, kernel_size, graphic_width,
1180 graphic_height, graphic_depth, hwdef->machine_id, "Sun4d");
1181 }
1182
1183 /* SPARCserver 1000 hardware initialisation */
1184 static void ss1000_init(int RAM_size, int vga_ram_size,
1185 const char *boot_device, DisplayState *ds,
1186 const char *kernel_filename, const char *kernel_cmdline,
1187 const char *initrd_filename, const char *cpu_model)
1188 {
1189 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename,
1190 kernel_cmdline, initrd_filename, cpu_model);
1191 }
1192
1193 /* SPARCcenter 2000 hardware initialisation */
1194 static void ss2000_init(int RAM_size, int vga_ram_size,
1195 const char *boot_device, DisplayState *ds,
1196 const char *kernel_filename, const char *kernel_cmdline,
1197 const char *initrd_filename, const char *cpu_model)
1198 {
1199 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename,
1200 kernel_cmdline, initrd_filename, cpu_model);
1201 }
1202
1203 QEMUMachine ss1000_machine = {
1204 "SS-1000",
1205 "Sun4d platform, SPARCserver 1000",
1206 ss1000_init,
1207 };
1208
1209 QEMUMachine ss2000_machine = {
1210 "SS-2000",
1211 "Sun4d platform, SPARCcenter 2000",
1212 ss2000_init,
1213 };
kvm userspace components