qemu/cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #define CPU_NO_GLOBAL_REGS
  22 #include "exec.h"
  23 #include "disas.h"
  24 #if !defined(TARGET_IA64)
  25 #include "tcg.h"
  26 #endif
  27
  28 #if !defined(CONFIG_SOFTMMU)
  29 #undef EAX
  30 #undef ECX
  31 #undef EDX
  32 #undef EBX
  33 #undef ESP
  34 #undef EBP
  35 #undef ESI
  36 #undef EDI
  37 #undef EIP
  38 #include <signal.h>
  39 #ifdef __linux__
  40 #include <sys/ucontext.h>
  41 #endif
  42 #endif
  43
  44 #include "qemu-kvm.h"
  45
  46 #if defined(__sparc__) && !defined(HOST_SOLARIS)
  47 // Work around ugly bugs in glibc that mangle global register contents
  48 #undef env
  49 #define env cpu_single_env
  50 #endif
  51
  52 int tb_invalidated_flag;
  53
  54 //#define DEBUG_EXEC
  55 //#define DEBUG_SIGNAL
  56
  57 void cpu_loop_exit(void)
  58 {
  59     /* NOTE: the register at this point must be saved by hand because
  60        longjmp restore them */
  61     regs_to_env();
  62     longjmp(env->jmp_env, 1);
  63 }
  64
  65 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
  66 #define reg_T2
  67 #endif
  68
  69 /* exit the current TB from a signal handler. The host registers are
  70    restored in a state compatible with the CPU emulator
  71  */
  72 void cpu_resume_from_signal(CPUState *env1, void *puc)
  73 {
  74 #if !defined(CONFIG_SOFTMMU)
  75 #ifdef __linux__
  76     struct ucontext *uc = puc;
  77 #elif defined(__OpenBSD__)
  78     struct sigcontext *uc = puc;
  79 #endif
  80 #endif
  81
  82     env = env1;
  83
  84     /* XXX: restore cpu registers saved in host registers */
  85
  86 #if !defined(CONFIG_SOFTMMU)
  87     if (puc) {
  88         /* XXX: use siglongjmp ? */
  89 #ifdef __linux__
  90         sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
  91 #elif defined(__OpenBSD__)
  92         sigprocmask(SIG_SETMASK, &uc->sc_mask, NULL);
  93 #endif
  94     }
  95 #endif
  96     longjmp(env->jmp_env, 1);
  97 }
  98
  99 /* Execute the code without caching the generated code. An interpreter
 100    could be used if available. */
 101 static void cpu_exec_nocache(int max_cycles, TranslationBlock *orig_tb)
 102 {
 103     unsigned long next_tb;
 104     TranslationBlock *tb;
 105
 106     /* Should never happen.
 107        We only end up here when an existing TB is too long.  */
 108     if (max_cycles > CF_COUNT_MASK)
 109         max_cycles = CF_COUNT_MASK;
 110
 111     tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
 112                      max_cycles);
 113     env->current_tb = tb;
 114     /* execute the generated code */
 115     next_tb = tcg_qemu_tb_exec(tb->tc_ptr);
 116
 117     if ((next_tb & 3) == 2) {
 118         /* Restore PC.  This may happen if async event occurs before
 119            the TB starts executing.  */
 120         CPU_PC_FROM_TB(env, tb);
 121     }
 122     tb_phys_invalidate(tb, -1);
 123     tb_free(tb);
 124 }
 125
 126 static TranslationBlock *tb_find_slow(target_ulong pc,
 127                                       target_ulong cs_base,
 128                                       uint64_t flags)
 129 {
 130     TranslationBlock *tb, **ptb1;
 131     unsigned int h;
 132     target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
 133
 134     tb_invalidated_flag = 0;
 135
 136     regs_to_env(); /* XXX: do it just before cpu_gen_code() */
 137
 138     /* find translated block using physical mappings */
 139     phys_pc = get_phys_addr_code(env, pc);
 140     phys_page1 = phys_pc & TARGET_PAGE_MASK;
 141     phys_page2 = -1;
 142     h = tb_phys_hash_func(phys_pc);
 143     ptb1 = &tb_phys_hash[h];
 144     for(;;) {
 145         tb = *ptb1;
 146         if (!tb)
 147             goto not_found;
 148         if (tb->pc == pc &&
 149             tb->page_addr[0] == phys_page1 &&
 150             tb->cs_base == cs_base &&
 151             tb->flags == flags) {
 152             /* check next page if needed */
 153             if (tb->page_addr[1] != -1) {
 154                 virt_page2 = (pc & TARGET_PAGE_MASK) +
 155                     TARGET_PAGE_SIZE;
 156                 phys_page2 = get_phys_addr_code(env, virt_page2);
 157                 if (tb->page_addr[1] == phys_page2)
 158                     goto found;
 159             } else {
 160                 goto found;
 161             }
 162         }
 163         ptb1 = &tb->phys_hash_next;
 164     }
 165  not_found:
 166    /* if no translated code available, then translate it now */
 167     tb = tb_gen_code(env, pc, cs_base, flags, 0);
 168
 169  found:
 170     /* we add the TB in the virtual pc hash table */
 171     env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
 172     return tb;
 173 }
 174
 175 static inline TranslationBlock *tb_find_fast(void)
 176 {
 177     TranslationBlock *tb;
 178     target_ulong cs_base, pc;
 179     uint64_t flags;
 180
 181     /* we record a subset of the CPU state. It will
 182        always be the same before a given translated block
 183        is executed. */
 184 #if defined(TARGET_I386)
 185     flags = env->hflags;
 186     flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
 187     cs_base = env->segs[R_CS].base;
 188     pc = cs_base + env->eip;
 189 #elif defined(TARGET_ARM)
 190     flags = env->thumb | (env->vfp.vec_len << 1)
 191             | (env->vfp.vec_stride << 4);
 192     if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
 193         flags |= (1 << 6);
 194     if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
 195         flags |= (1 << 7);
 196     flags |= (env->condexec_bits << 8);
 197     cs_base = 0;
 198     pc = env->regs[15];
 199 #elif defined(TARGET_SPARC)
 200 #ifdef TARGET_SPARC64
 201     // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
 202     flags = ((env->pstate & PS_AM) << 2)
 203         | (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
 204         | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
 205 #else
 206     // FPU enable . Supervisor
 207     flags = (env->psref << 4) | env->psrs;
 208 #endif
 209     cs_base = env->npc;
 210     pc = env->pc;
 211 #elif defined(TARGET_PPC)
 212     flags = env->hflags;
 213     cs_base = 0;
 214     pc = env->nip;
 215 #elif defined(TARGET_MIPS)
 216     flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
 217     cs_base = 0;
 218     pc = env->active_tc.PC;
 219 #elif defined(TARGET_M68K)
 220     flags = (env->fpcr & M68K_FPCR_PREC)  /* Bit  6 */
 221             | (env->sr & SR_S)            /* Bit  13 */
 222             | ((env->macsr >> 4) & 0xf);  /* Bits 0-3 */
 223     cs_base = 0;
 224     pc = env->pc;
 225 #elif defined(TARGET_SH4)
 226     flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
 227                     | DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME))   /* Bits  0- 3 */
 228             | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR))  /* Bits 19-21 */
 229             | (env->sr & (SR_MD | SR_RB));                     /* Bits 29-30 */
 230     cs_base = 0;
 231     pc = env->pc;
 232 #elif defined(TARGET_ALPHA)
 233     flags = env->ps;
 234     cs_base = 0;
 235     pc = env->pc;
 236 #elif defined(TARGET_CRIS)
 237     flags = env->pregs[PR_CCS] & (S_FLAG | P_FLAG | U_FLAG | X_FLAG);
 238     flags |= env->dslot;
 239     cs_base = 0;
 240     pc = env->pc;
 241 #elif defined(TARGET_IA64)
 242     flags = 0;
 243     cs_base = 0;         /* XXXXX */
 244     pc = 0;
 245 #else
 246 #error unsupported CPU
 247 #endif
 248     tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
 249     if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
 250                  tb->flags != flags)) {
 251         tb = tb_find_slow(pc, cs_base, flags);
 252     }
 253     return tb;
 254 }
 255
 256 /* main execution loop */
 257
 258 int cpu_exec(CPUState *env1)
 259 {
 260 #define DECLARE_HOST_REGS 1
 261 #include "hostregs_helper.h"
 262     int ret, interrupt_request;
 263     TranslationBlock *tb;
 264     uint8_t *tc_ptr;
 265     unsigned long next_tb;
 266
 267     if (cpu_halted(env1) == EXCP_HALTED)
 268         return EXCP_HALTED;
 269
 270     cpu_single_env = env1;
 271
 272     /* first we save global registers */
 273 #define SAVE_HOST_REGS 1
 274 #include "hostregs_helper.h"
 275     env = env1;
 276
 277     env_to_regs();
 278 #if defined(TARGET_I386)
 279     /* put eflags in CPU temporary format */
 280     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 281     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 282     CC_OP = CC_OP_EFLAGS;
 283     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 284 #elif defined(TARGET_SPARC)
 285 #elif defined(TARGET_M68K)
 286     env->cc_op = CC_OP_FLAGS;
 287     env->cc_dest = env->sr & 0xf;
 288     env->cc_x = (env->sr >> 4) & 1;
 289 #elif defined(TARGET_ALPHA)
 290 #elif defined(TARGET_ARM)
 291 #elif defined(TARGET_PPC)
 292 #elif defined(TARGET_MIPS)
 293 #elif defined(TARGET_SH4)
 294 #elif defined(TARGET_CRIS)
 295 #elif defined(TARGET_IA64)
 296     /* XXXXX */
 297 #else
 298 #error unsupported target CPU
 299 #endif
 300     env->exception_index = -1;
 301
 302     /* prepare setjmp context for exception handling */
 303     for(;;) {
 304         if (setjmp(env->jmp_env) == 0) {
 305             env->current_tb = NULL;
 306             /* if an exception is pending, we execute it here */
 307             if (env->exception_index >= 0) {
 308                 if (env->exception_index >= EXCP_INTERRUPT) {
 309                     /* exit request from the cpu execution loop */
 310                     ret = env->exception_index;
 311                     break;
 312                 } else if (env->user_mode_only) {
 313                     /* if user mode only, we simulate a fake exception
 314                        which will be handled outside the cpu execution
 315                        loop */
 316 #if defined(TARGET_I386)
 317                     do_interrupt_user(env->exception_index,
 318                                       env->exception_is_int,
 319                                       env->error_code,
 320                                       env->exception_next_eip);
 321                     /* successfully delivered */
 322                     env->old_exception = -1;
 323 #endif
 324                     ret = env->exception_index;
 325                     break;
 326                 } else {
 327 #if defined(TARGET_I386)
 328                     /* simulate a real cpu exception. On i386, it can
 329                        trigger new exceptions, but we do not handle
 330                        double or triple faults yet. */
 331                     do_interrupt(env->exception_index,
 332                                  env->exception_is_int,
 333                                  env->error_code,
 334                                  env->exception_next_eip, 0);
 335                     /* successfully delivered */
 336                     env->old_exception = -1;
 337 #elif defined(TARGET_PPC)
 338                     do_interrupt(env);
 339 #elif defined(TARGET_MIPS)
 340                     do_interrupt(env);
 341 #elif defined(TARGET_SPARC)
 342                     do_interrupt(env);
 343 #elif defined(TARGET_ARM)
 344                     do_interrupt(env);
 345 #elif defined(TARGET_SH4)
 346                     do_interrupt(env);
 347 #elif defined(TARGET_ALPHA)
 348                     do_interrupt(env);
 349 #elif defined(TARGET_CRIS)
 350                     do_interrupt(env);
 351 #elif defined(TARGET_M68K)
 352                     do_interrupt(0);
 353 #elif defined(TARGET_IA64)
 354                     do_interrupt(env);
 355 #endif
 356                 }
 357                 env->exception_index = -1;
 358             }
 359 #ifdef USE_KQEMU
 360             if (kqemu_is_ok(env) && env->interrupt_request == 0) {
 361                 int ret;
 362                 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 363                 ret = kqemu_cpu_exec(env);
 364                 /* put eflags in CPU temporary format */
 365                 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 366                 DF = 1 - (2 * ((env->eflags >> 10) & 1));
 367                 CC_OP = CC_OP_EFLAGS;
 368                 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 369                 if (ret == 1) {
 370                     /* exception */
 371                     longjmp(env->jmp_env, 1);
 372                 } else if (ret == 2) {
 373                     /* softmmu execution needed */
 374                 } else {
 375                     if (env->interrupt_request != 0) {
 376                         /* hardware interrupt will be executed just after */
 377                     } else {
 378                         /* otherwise, we restart */
 379                         longjmp(env->jmp_env, 1);
 380                     }
 381                 }
 382             }
 383 #endif
 384
 385             if (kvm_enabled()) {
 386                 kvm_cpu_exec(env);
 387                 longjmp(env->jmp_env, 1);
 388             }
 389             next_tb = 0; /* force lookup of first TB */
 390             for(;;) {
 391                 interrupt_request = env->interrupt_request;
 392                 if (unlikely(interrupt_request) &&
 393                     likely(!(env->singlestep_enabled & SSTEP_NOIRQ))) {
 394                     if (interrupt_request & CPU_INTERRUPT_DEBUG) {
 395                         env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
 396                         env->exception_index = EXCP_DEBUG;
 397                         cpu_loop_exit();
 398                     }
 399 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
 400     defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS)
 401                     if (interrupt_request & CPU_INTERRUPT_HALT) {
 402                         env->interrupt_request &= ~CPU_INTERRUPT_HALT;
 403                         env->halted = 1;
 404                         env->exception_index = EXCP_HLT;
 405                         cpu_loop_exit();
 406                     }
 407 #endif
 408 #if defined(TARGET_I386)
 409                     if (env->hflags2 & HF2_GIF_MASK) {
 410                         if ((interrupt_request & CPU_INTERRUPT_SMI) &&
 411                             !(env->hflags & HF_SMM_MASK)) {
 412                             svm_check_intercept(SVM_EXIT_SMI);
 413                             env->interrupt_request &= ~CPU_INTERRUPT_SMI;
 414                             do_smm_enter();
 415                             next_tb = 0;
 416                         } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
 417                                    !(env->hflags2 & HF2_NMI_MASK)) {
 418                             env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 419                             env->hflags2 |= HF2_NMI_MASK;
 420                             do_interrupt(EXCP02_NMI, 0, 0, 0, 1);
 421                             next_tb = 0;
 422                         } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 423                                    (((env->hflags2 & HF2_VINTR_MASK) &&
 424                                      (env->hflags2 & HF2_HIF_MASK)) ||
 425                                     (!(env->hflags2 & HF2_VINTR_MASK) &&
 426                                      (env->eflags & IF_MASK &&
 427                                       !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
 428                             int intno;
 429                             svm_check_intercept(SVM_EXIT_INTR);
 430                             env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
 431                             intno = cpu_get_pic_interrupt(env);
 432                             if (loglevel & CPU_LOG_TB_IN_ASM) {
 433                                 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
 434                             }
 435                             do_interrupt(intno, 0, 0, 0, 1);
 436                             /* ensure that no TB jump will be modified as
 437                                the program flow was changed */
 438                             next_tb = 0;
 439 #if !defined(CONFIG_USER_ONLY)
 440                         } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
 441                                    (env->eflags & IF_MASK) &&
 442                                    !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 443                             int intno;
 444                             /* FIXME: this should respect TPR */
 445                             svm_check_intercept(SVM_EXIT_VINTR);
 446                             env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
 447                             intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
 448                             if (loglevel & CPU_LOG_TB_IN_ASM)
 449                                 fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno);
 450                             do_interrupt(intno, 0, 0, 0, 1);
 451                             next_tb = 0;
 452 #endif
 453                         }
 454                     }
 455 #elif defined(TARGET_PPC)
 456 #if 0
 457                     if ((interrupt_request & CPU_INTERRUPT_RESET)) {
 458                         cpu_ppc_reset(env);
 459                     }
 460 #endif
 461                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 462                         ppc_hw_interrupt(env);
 463                         if (env->pending_interrupts == 0)
 464                             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 465                         next_tb = 0;
 466                     }
 467 #elif defined(TARGET_MIPS)
 468                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 469                         (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
 470                         (env->CP0_Status & (1 << CP0St_IE)) &&
 471                         !(env->CP0_Status & (1 << CP0St_EXL)) &&
 472                         !(env->CP0_Status & (1 << CP0St_ERL)) &&
 473                         !(env->hflags & MIPS_HFLAG_DM)) {
 474                         /* Raise it */
 475                         env->exception_index = EXCP_EXT_INTERRUPT;
 476                         env->error_code = 0;
 477                         do_interrupt(env);
 478                         next_tb = 0;
 479                     }
 480 #elif defined(TARGET_SPARC)
 481                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 482                         (env->psret != 0)) {
 483                         int pil = env->interrupt_index & 15;
 484                         int type = env->interrupt_index & 0xf0;
 485
 486                         if (((type == TT_EXTINT) &&
 487                              (pil == 15 || pil > env->psrpil)) ||
 488                             type != TT_EXTINT) {
 489                             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 490                             env->exception_index = env->interrupt_index;
 491                             do_interrupt(env);
 492                             env->interrupt_index = 0;
 493 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 494                             cpu_check_irqs(env);
 495 #endif
 496                         next_tb = 0;
 497                         }
 498                     } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
 499                         //do_interrupt(0, 0, 0, 0, 0);
 500                         env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
 501                     }
 502 #elif defined(TARGET_ARM)
 503                     if (interrupt_request & CPU_INTERRUPT_FIQ
 504                         && !(env->uncached_cpsr & CPSR_F)) {
 505                         env->exception_index = EXCP_FIQ;
 506                         do_interrupt(env);
 507                         next_tb = 0;
 508                     }
 509                     /* ARMv7-M interrupt return works by loading a magic value
 510                        into the PC.  On real hardware the load causes the
 511                        return to occur.  The qemu implementation performs the
 512                        jump normally, then does the exception return when the
 513                        CPU tries to execute code at the magic address.
 514                        This will cause the magic PC value to be pushed to
 515                        the stack if an interrupt occured at the wrong time.
 516                        We avoid this by disabling interrupts when
 517                        pc contains a magic address.  */
 518                     if (interrupt_request & CPU_INTERRUPT_HARD
 519                         && ((IS_M(env) && env->regs[15] < 0xfffffff0)
 520                             || !(env->uncached_cpsr & CPSR_I))) {
 521                         env->exception_index = EXCP_IRQ;
 522                         do_interrupt(env);
 523                         next_tb = 0;
 524                     }
 525 #elif defined(TARGET_SH4)
 526                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 527                         do_interrupt(env);
 528                         next_tb = 0;
 529                     }
 530 #elif defined(TARGET_ALPHA)
 531                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 532                         do_interrupt(env);
 533                         next_tb = 0;
 534                     }
 535 #elif defined(TARGET_CRIS)
 536                     if (interrupt_request & CPU_INTERRUPT_HARD
 537                         && (env->pregs[PR_CCS] & I_FLAG)) {
 538                         env->exception_index = EXCP_IRQ;
 539                         do_interrupt(env);
 540                         next_tb = 0;
 541                     }
 542                     if (interrupt_request & CPU_INTERRUPT_NMI
 543                         && (env->pregs[PR_CCS] & M_FLAG)) {
 544                         env->exception_index = EXCP_NMI;
 545                         do_interrupt(env);
 546                         next_tb = 0;
 547                     }
 548 #elif defined(TARGET_M68K)
 549                     if (interrupt_request & CPU_INTERRUPT_HARD
 550                         && ((env->sr & SR_I) >> SR_I_SHIFT)
 551                             < env->pending_level) {
 552                         /* Real hardware gets the interrupt vector via an
 553                            IACK cycle at this point.  Current emulated
 554                            hardware doesn't rely on this, so we
 555                            provide/save the vector when the interrupt is
 556                            first signalled.  */
 557                         env->exception_index = env->pending_vector;
 558                         do_interrupt(1);
 559                         next_tb = 0;
 560                     }
 561 #endif
 562                    /* Don't use the cached interupt_request value,
 563                       do_interrupt may have updated the EXITTB flag. */
 564                     if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
 565                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
 566                         /* ensure that no TB jump will be modified as
 567                            the program flow was changed */
 568                         next_tb = 0;
 569                     }
 570                     if (interrupt_request & CPU_INTERRUPT_EXIT) {
 571                         env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
 572                         env->exception_index = EXCP_INTERRUPT;
 573                         cpu_loop_exit();
 574                     }
 575                 }
 576 #ifdef DEBUG_EXEC
 577                 if ((loglevel & CPU_LOG_TB_CPU)) {
 578                     /* restore flags in standard format */
 579                     regs_to_env();
 580 #if defined(TARGET_I386)
 581                     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 582                     cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
 583                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 584 #elif defined(TARGET_ARM)
 585                     cpu_dump_state(env, logfile, fprintf, 0);
 586 #elif defined(TARGET_SPARC)
 587                     cpu_dump_state(env, logfile, fprintf, 0);
 588 #elif defined(TARGET_PPC)
 589                     cpu_dump_state(env, logfile, fprintf, 0);
 590 #elif defined(TARGET_M68K)
 591                     cpu_m68k_flush_flags(env, env->cc_op);
 592                     env->cc_op = CC_OP_FLAGS;
 593                     env->sr = (env->sr & 0xffe0)
 594                               | env->cc_dest | (env->cc_x << 4);
 595                     cpu_dump_state(env, logfile, fprintf, 0);
 596 #elif defined(TARGET_MIPS)
 597                     cpu_dump_state(env, logfile, fprintf, 0);
 598 #elif defined(TARGET_SH4)
 599                     cpu_dump_state(env, logfile, fprintf, 0);
 600 #elif defined(TARGET_ALPHA)
 601                     cpu_dump_state(env, logfile, fprintf, 0);
 602 #elif defined(TARGET_CRIS)
 603                     cpu_dump_state(env, logfile, fprintf, 0);
 604 #else
 605 #error unsupported target CPU
 606 #endif
 607                 }
 608 #endif
 609                 spin_lock(&tb_lock);
 610                 tb = tb_find_fast();
 611                 /* Note: we do it here to avoid a gcc bug on Mac OS X when
 612                    doing it in tb_find_slow */
 613                 if (tb_invalidated_flag) {
 614                     /* as some TB could have been invalidated because
 615                        of memory exceptions while generating the code, we
 616                        must recompute the hash index here */
 617                     next_tb = 0;
 618                     tb_invalidated_flag = 0;
 619                 }
 620 #ifdef DEBUG_EXEC
 621                 if ((loglevel & CPU_LOG_EXEC)) {
 622                     fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
 623                             (long)tb->tc_ptr, tb->pc,
 624                             lookup_symbol(tb->pc));
 625                 }
 626 #endif
 627                 /* see if we can patch the calling TB. When the TB
 628                    spans two pages, we cannot safely do a direct
 629                    jump. */
 630                 {
 631                     if (next_tb != 0 &&
 632 #ifdef USE_KQEMU
 633                         (env->kqemu_enabled != 2) &&
 634 #endif
 635                         tb->page_addr[1] == -1) {
 636                     tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
 637                 }
 638                 }
 639                 spin_unlock(&tb_lock);
 640                 env->current_tb = tb;
 641                 while (env->current_tb) {
 642                     tc_ptr = tb->tc_ptr;
 643                 /* execute the generated code */
 644 #if defined(__sparc__) && !defined(HOST_SOLARIS)
 645 #undef env
 646                     env = cpu_single_env;
 647 #define env cpu_single_env
 648 #endif
 649                     next_tb = tcg_qemu_tb_exec(tc_ptr);
 650                     env->current_tb = NULL;
 651                     if ((next_tb & 3) == 2) {
 652                         /* Instruction counter expired.  */
 653                         int insns_left;
 654                         tb = (TranslationBlock *)(long)(next_tb & ~3);
 655                         /* Restore PC.  */
 656                         CPU_PC_FROM_TB(env, tb);
 657                         insns_left = env->icount_decr.u32;
 658                         if (env->icount_extra && insns_left >= 0) {
 659                             /* Refill decrementer and continue execution.  */
 660                             env->icount_extra += insns_left;
 661                             if (env->icount_extra > 0xffff) {
 662                                 insns_left = 0xffff;
 663                             } else {
 664                                 insns_left = env->icount_extra;
 665                             }
 666                             env->icount_extra -= insns_left;
 667                             env->icount_decr.u16.low = insns_left;
 668                         } else {
 669                             if (insns_left > 0) {
 670                                 /* Execute remaining instructions.  */
 671                                 cpu_exec_nocache(insns_left, tb);
 672                             }
 673                             env->exception_index = EXCP_INTERRUPT;
 674                             next_tb = 0;
 675                             cpu_loop_exit();
 676                         }
 677                     }
 678                 }
 679                 /* reset soft MMU for next block (it can currently
 680                    only be set by a memory fault) */
 681 #if defined(USE_KQEMU)
 682 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
 683                 if (kqemu_is_ok(env) &&
 684                     (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
 685                     cpu_loop_exit();
 686                 }
 687 #endif
 688             } /* for(;;) */
 689         } else {
 690             env_to_regs();
 691         }
 692     } /* for(;;) */
 693
 694
 695 #if defined(TARGET_I386)
 696     /* restore flags in standard format */
 697     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 698 #elif defined(TARGET_ARM)
 699     /* XXX: Save/restore host fpu exception state?.  */
 700 #elif defined(TARGET_SPARC)
 701 #elif defined(TARGET_PPC)
 702 #elif defined(TARGET_M68K)
 703     cpu_m68k_flush_flags(env, env->cc_op);
 704     env->cc_op = CC_OP_FLAGS;
 705     env->sr = (env->sr & 0xffe0)
 706               | env->cc_dest | (env->cc_x << 4);
 707 #elif defined(TARGET_MIPS)
 708 #elif defined(TARGET_SH4)
 709 #elif defined(TARGET_IA64)
 710 #elif defined(TARGET_ALPHA)
 711 #elif defined(TARGET_CRIS)
 712     /* XXXXX */
 713 #else
 714 #error unsupported target CPU
 715 #endif
 716
 717     /* restore global registers */
 718 #include "hostregs_helper.h"
 719
 720     /* fail safe : never use cpu_single_env outside cpu_exec() */
 721     cpu_single_env = NULL;
 722     return ret;
 723 }
 724
 725 /* must only be called from the generated code as an exception can be
 726    generated */
 727 void tb_invalidate_page_range(target_ulong start, target_ulong end)
 728 {
 729     /* XXX: cannot enable it yet because it yields to MMU exception
 730        where NIP != read address on PowerPC */
 731 #if 0
 732     target_ulong phys_addr;
 733     phys_addr = get_phys_addr_code(env, start);
 734     tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
 735 #endif
 736 }
 737
 738 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
 739
 740 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 741 {
 742     CPUX86State *saved_env;
 743
 744     saved_env = env;
 745     env = s;
 746     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 747         selector &= 0xffff;
 748         cpu_x86_load_seg_cache(env, seg_reg, selector,
 749                                (selector << 4), 0xffff, 0);
 750     } else {
 751         helper_load_seg(seg_reg, selector);
 752     }
 753     env = saved_env;
 754 }
 755
 756 void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32)
 757 {
 758     CPUX86State *saved_env;
 759
 760     saved_env = env;
 761     env = s;
 762
 763     helper_fsave(ptr, data32);
 764
 765     env = saved_env;
 766 }
 767
 768 void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32)
 769 {
 770     CPUX86State *saved_env;
 771
 772     saved_env = env;
 773     env = s;
 774
 775     helper_frstor(ptr, data32);
 776
 777     env = saved_env;
 778 }
 779
 780 #endif /* TARGET_I386 */
 781
 782 #if !defined(CONFIG_SOFTMMU)
 783
 784 #if defined(TARGET_I386)
 785
 786 /* 'pc' is the host PC at which the exception was raised. 'address' is
 787    the effective address of the memory exception. 'is_write' is 1 if a
 788    write caused the exception and otherwise 0'. 'old_set' is the
 789    signal set which should be restored */
 790 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 791                                     int is_write, sigset_t *old_set,
 792                                     void *puc)
 793 {
 794     TranslationBlock *tb;
 795     int ret;
 796
 797     if (cpu_single_env)
 798         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 799 #if defined(DEBUG_SIGNAL)
 800     qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 801                 pc, address, is_write, *(unsigned long *)old_set);
 802 #endif
 803     /* XXX: locking issue */
 804     if (is_write && page_unprotect(h2g(address), pc, puc)) {
 805         return 1;
 806     }
 807
 808     /* see if it is an MMU fault */
 809     ret = cpu_x86_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 810     if (ret < 0)
 811         return 0; /* not an MMU fault */
 812     if (ret == 0)
 813         return 1; /* the MMU fault was handled without causing real CPU fault */
 814     /* now we have a real cpu fault */
 815     tb = tb_find_pc(pc);
 816     if (tb) {
 817         /* the PC is inside the translated code. It means that we have
 818            a virtual CPU fault */
 819         cpu_restore_state(tb, env, pc, puc);
 820     }
 821     if (ret == 1) {
 822 #if 0
 823         printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
 824                env->eip, env->cr[2], env->error_code);
 825 #endif
 826         /* we restore the process signal mask as the sigreturn should
 827            do it (XXX: use sigsetjmp) */
 828         sigprocmask(SIG_SETMASK, old_set, NULL);
 829         raise_exception_err(env->exception_index, env->error_code);
 830     } else {
 831         /* activate soft MMU for this block */
 832         env->hflags |= HF_SOFTMMU_MASK;
 833         cpu_resume_from_signal(env, puc);
 834     }
 835     /* never comes here */
 836     return 1;
 837 }
 838
 839 #elif defined(TARGET_ARM)
 840 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 841                                     int is_write, sigset_t *old_set,
 842                                     void *puc)
 843 {
 844     TranslationBlock *tb;
 845     int ret;
 846
 847     if (cpu_single_env)
 848         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 849 #if defined(DEBUG_SIGNAL)
 850     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 851            pc, address, is_write, *(unsigned long *)old_set);
 852 #endif
 853     /* XXX: locking issue */
 854     if (is_write && page_unprotect(h2g(address), pc, puc)) {
 855         return 1;
 856     }
 857     /* see if it is an MMU fault */
 858     ret = cpu_arm_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 859     if (ret < 0)
 860         return 0; /* not an MMU fault */
 861     if (ret == 0)
 862         return 1; /* the MMU fault was handled without causing real CPU fault */
 863     /* now we have a real cpu fault */
 864     tb = tb_find_pc(pc);
 865     if (tb) {
 866         /* the PC is inside the translated code. It means that we have
 867            a virtual CPU fault */
 868         cpu_restore_state(tb, env, pc, puc);
 869     }
 870     /* we restore the process signal mask as the sigreturn should
 871        do it (XXX: use sigsetjmp) */
 872     sigprocmask(SIG_SETMASK, old_set, NULL);
 873     cpu_loop_exit();
 874     /* never comes here */
 875     return 1;
 876 }
 877 #elif defined(TARGET_SPARC)
 878 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 879                                     int is_write, sigset_t *old_set,
 880                                     void *puc)
 881 {
 882     TranslationBlock *tb;
 883     int ret;
 884
 885     if (cpu_single_env)
 886         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 887 #if defined(DEBUG_SIGNAL)
 888     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 889            pc, address, is_write, *(unsigned long *)old_set);
 890 #endif
 891     /* XXX: locking issue */
 892     if (is_write && page_unprotect(h2g(address), pc, puc)) {
 893         return 1;
 894     }
 895     /* see if it is an MMU fault */
 896     ret = cpu_sparc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 897     if (ret < 0)
 898         return 0; /* not an MMU fault */
 899     if (ret == 0)
 900         return 1; /* the MMU fault was handled without causing real CPU fault */
 901     /* now we have a real cpu fault */
 902     tb = tb_find_pc(pc);
 903     if (tb) {
 904         /* the PC is inside the translated code. It means that we have
 905            a virtual CPU fault */
 906         cpu_restore_state(tb, env, pc, puc);
 907     }
 908     /* we restore the process signal mask as the sigreturn should
 909        do it (XXX: use sigsetjmp) */
 910     sigprocmask(SIG_SETMASK, old_set, NULL);
 911     cpu_loop_exit();
 912     /* never comes here */
 913     return 1;
 914 }
 915 #elif defined (TARGET_PPC)
 916 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 917                                     int is_write, sigset_t *old_set,
 918                                     void *puc)
 919 {
 920     TranslationBlock *tb;
 921     int ret;
 922
 923     if (cpu_single_env)
 924         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 925 #if defined(DEBUG_SIGNAL)
 926     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 927            pc, address, is_write, *(unsigned long *)old_set);
 928 #endif
 929     /* XXX: locking issue */
 930     if (is_write && page_unprotect(h2g(address), pc, puc)) {
 931         return 1;
 932     }
 933
 934     /* see if it is an MMU fault */
 935     ret = cpu_ppc_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 936     if (ret < 0)
 937         return 0; /* not an MMU fault */
 938     if (ret == 0)
 939         return 1; /* the MMU fault was handled without causing real CPU fault */
 940
 941     /* now we have a real cpu fault */
 942     tb = tb_find_pc(pc);
 943     if (tb) {
 944         /* the PC is inside the translated code. It means that we have
 945            a virtual CPU fault */
 946         cpu_restore_state(tb, env, pc, puc);
 947     }
 948     if (ret == 1) {
 949 #if 0
 950         printf("PF exception: NIP=0x%08x error=0x%x %p\n",
 951                env->nip, env->error_code, tb);
 952 #endif
 953     /* we restore the process signal mask as the sigreturn should
 954        do it (XXX: use sigsetjmp) */
 955         sigprocmask(SIG_SETMASK, old_set, NULL);
 956         do_raise_exception_err(env->exception_index, env->error_code);
 957     } else {
 958         /* activate soft MMU for this block */
 959         cpu_resume_from_signal(env, puc);
 960     }
 961     /* never comes here */
 962     return 1;
 963 }
 964
 965 #elif defined(TARGET_M68K)
 966 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 967                                     int is_write, sigset_t *old_set,
 968                                     void *puc)
 969 {
 970     TranslationBlock *tb;
 971     int ret;
 972
 973     if (cpu_single_env)
 974         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 975 #if defined(DEBUG_SIGNAL)
 976     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 977            pc, address, is_write, *(unsigned long *)old_set);
 978 #endif
 979     /* XXX: locking issue */
 980     if (is_write && page_unprotect(address, pc, puc)) {
 981         return 1;
 982     }
 983     /* see if it is an MMU fault */
 984     ret = cpu_m68k_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
 985     if (ret < 0)
 986         return 0; /* not an MMU fault */
 987     if (ret == 0)
 988         return 1; /* the MMU fault was handled without causing real CPU fault */
 989     /* now we have a real cpu fault */
 990     tb = tb_find_pc(pc);
 991     if (tb) {
 992         /* the PC is inside the translated code. It means that we have
 993            a virtual CPU fault */
 994         cpu_restore_state(tb, env, pc, puc);
 995     }
 996     /* we restore the process signal mask as the sigreturn should
 997        do it (XXX: use sigsetjmp) */
 998     sigprocmask(SIG_SETMASK, old_set, NULL);
 999     cpu_loop_exit();
1000     /* never comes here */
1001     return 1;
1002 }
1003
1004 #elif defined (TARGET_MIPS)
1005 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1006                                     int is_write, sigset_t *old_set,
1007                                     void *puc)
1008 {
1009     TranslationBlock *tb;
1010     int ret;
1011
1012     if (cpu_single_env)
1013         env = cpu_single_env; /* XXX: find a correct solution for multithread */
1014 #if defined(DEBUG_SIGNAL)
1015     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1016            pc, address, is_write, *(unsigned long *)old_set);
1017 #endif
1018     /* XXX: locking issue */
1019     if (is_write && page_unprotect(h2g(address), pc, puc)) {
1020         return 1;
1021     }
1022
1023     /* see if it is an MMU fault */
1024     ret = cpu_mips_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1025     if (ret < 0)
1026         return 0; /* not an MMU fault */
1027     if (ret == 0)
1028         return 1; /* the MMU fault was handled without causing real CPU fault */
1029
1030     /* now we have a real cpu fault */
1031     tb = tb_find_pc(pc);
1032     if (tb) {
1033         /* the PC is inside the translated code. It means that we have
1034            a virtual CPU fault */
1035         cpu_restore_state(tb, env, pc, puc);
1036     }
1037     if (ret == 1) {
1038 #if 0
1039         printf("PF exception: PC=0x" TARGET_FMT_lx " error=0x%x %p\n",
1040                env->PC, env->error_code, tb);
1041 #endif
1042     /* we restore the process signal mask as the sigreturn should
1043        do it (XXX: use sigsetjmp) */
1044         sigprocmask(SIG_SETMASK, old_set, NULL);
1045         do_raise_exception_err(env->exception_index, env->error_code);
1046     } else {
1047         /* activate soft MMU for this block */
1048         cpu_resume_from_signal(env, puc);
1049     }
1050     /* never comes here */
1051     return 1;
1052 }
1053
1054 #elif defined (TARGET_SH4)
1055 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1056                                     int is_write, sigset_t *old_set,
1057                                     void *puc)
1058 {
1059     TranslationBlock *tb;
1060     int ret;
1061
1062     if (cpu_single_env)
1063         env = cpu_single_env; /* XXX: find a correct solution for multithread */
1064 #if defined(DEBUG_SIGNAL)
1065     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1066            pc, address, is_write, *(unsigned long *)old_set);
1067 #endif
1068     /* XXX: locking issue */
1069     if (is_write && page_unprotect(h2g(address), pc, puc)) {
1070         return 1;
1071     }
1072
1073     /* see if it is an MMU fault */
1074     ret = cpu_sh4_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1075     if (ret < 0)
1076         return 0; /* not an MMU fault */
1077     if (ret == 0)
1078         return 1; /* the MMU fault was handled without causing real CPU fault */
1079
1080     /* now we have a real cpu fault */
1081     tb = tb_find_pc(pc);
1082     if (tb) {
1083         /* the PC is inside the translated code. It means that we have
1084            a virtual CPU fault */
1085         cpu_restore_state(tb, env, pc, puc);
1086     }
1087 #if 0
1088         printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1089                env->nip, env->error_code, tb);
1090 #endif
1091     /* we restore the process signal mask as the sigreturn should
1092        do it (XXX: use sigsetjmp) */
1093     sigprocmask(SIG_SETMASK, old_set, NULL);
1094     cpu_loop_exit();
1095     /* never comes here */
1096     return 1;
1097 }
1098
1099 #elif defined (TARGET_ALPHA)
1100 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1101                                     int is_write, sigset_t *old_set,
1102                                     void *puc)
1103 {
1104     TranslationBlock *tb;
1105     int ret;
1106
1107     if (cpu_single_env)
1108         env = cpu_single_env; /* XXX: find a correct solution for multithread */
1109 #if defined(DEBUG_SIGNAL)
1110     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1111            pc, address, is_write, *(unsigned long *)old_set);
1112 #endif
1113     /* XXX: locking issue */
1114     if (is_write && page_unprotect(h2g(address), pc, puc)) {
1115         return 1;
1116     }
1117
1118     /* see if it is an MMU fault */
1119     ret = cpu_alpha_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1120     if (ret < 0)
1121         return 0; /* not an MMU fault */
1122     if (ret == 0)
1123         return 1; /* the MMU fault was handled without causing real CPU fault */
1124
1125     /* now we have a real cpu fault */
1126     tb = tb_find_pc(pc);
1127     if (tb) {
1128         /* the PC is inside the translated code. It means that we have
1129            a virtual CPU fault */
1130         cpu_restore_state(tb, env, pc, puc);
1131     }
1132 #if 0
1133         printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1134                env->nip, env->error_code, tb);
1135 #endif
1136     /* we restore the process signal mask as the sigreturn should
1137        do it (XXX: use sigsetjmp) */
1138     sigprocmask(SIG_SETMASK, old_set, NULL);
1139     cpu_loop_exit();
1140     /* never comes here */
1141     return 1;
1142 }
1143 #elif defined (TARGET_CRIS)
1144 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1145                                     int is_write, sigset_t *old_set,
1146                                     void *puc)
1147 {
1148     TranslationBlock *tb;
1149     int ret;
1150
1151     if (cpu_single_env)
1152         env = cpu_single_env; /* XXX: find a correct solution for multithread */
1153 #if defined(DEBUG_SIGNAL)
1154     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1155            pc, address, is_write, *(unsigned long *)old_set);
1156 #endif
1157     /* XXX: locking issue */
1158     if (is_write && page_unprotect(h2g(address), pc, puc)) {
1159         return 1;
1160     }
1161
1162     /* see if it is an MMU fault */
1163     ret = cpu_cris_handle_mmu_fault(env, address, is_write, MMU_USER_IDX, 0);
1164     if (ret < 0)
1165         return 0; /* not an MMU fault */
1166     if (ret == 0)
1167         return 1; /* the MMU fault was handled without causing real CPU fault */
1168
1169     /* now we have a real cpu fault */
1170     tb = tb_find_pc(pc);
1171     if (tb) {
1172         /* the PC is inside the translated code. It means that we have
1173            a virtual CPU fault */
1174         cpu_restore_state(tb, env, pc, puc);
1175     }
1176     /* we restore the process signal mask as the sigreturn should
1177        do it (XXX: use sigsetjmp) */
1178     sigprocmask(SIG_SETMASK, old_set, NULL);
1179     cpu_loop_exit();
1180     /* never comes here */
1181     return 1;
1182 }
1183
1184 #else
1185 #error unsupported target CPU
1186 #endif
1187
1188 #if defined(__i386__)
1189
1190 #if defined(__APPLE__)
1191 # include <sys/ucontext.h>
1192
1193 # define EIP_sig(context)  (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1194 # define TRAP_sig(context)    ((context)->uc_mcontext->es.trapno)
1195 # define ERROR_sig(context)   ((context)->uc_mcontext->es.err)
1196 #else
1197 # define EIP_sig(context)     ((context)->uc_mcontext.gregs[REG_EIP])
1198 # define TRAP_sig(context)    ((context)->uc_mcontext.gregs[REG_TRAPNO])
1199 # define ERROR_sig(context)   ((context)->uc_mcontext.gregs[REG_ERR])
1200 #endif
1201
1202 int cpu_signal_handler(int host_signum, void *pinfo,
1203                        void *puc)
1204 {
1205     siginfo_t *info = pinfo;
1206     struct ucontext *uc = puc;
1207     unsigned long pc;
1208     int trapno;
1209
1210 #ifndef REG_EIP
1211 /* for glibc 2.1 */
1212 #define REG_EIP    EIP
1213 #define REG_ERR    ERR
1214 #define REG_TRAPNO TRAPNO
1215 #endif
1216     pc = EIP_sig(uc);
1217     trapno = TRAP_sig(uc);
1218     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1219                              trapno == 0xe ?
1220                              (ERROR_sig(uc) >> 1) & 1 : 0,
1221                              &uc->uc_sigmask, puc);
1222 }
1223
1224 #elif defined(__x86_64__)
1225
1226 int cpu_signal_handler(int host_signum, void *pinfo,
1227                        void *puc)
1228 {
1229     siginfo_t *info = pinfo;
1230     struct ucontext *uc = puc;
1231     unsigned long pc;
1232
1233     pc = uc->uc_mcontext.gregs[REG_RIP];
1234     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1235                              uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1236                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1237                              &uc->uc_sigmask, puc);
1238 }
1239
1240 #elif defined(__powerpc__)
1241
1242 /***********************************************************************
1243  * signal context platform-specific definitions
1244  * From Wine
1245  */
1246 #ifdef linux
1247 /* All Registers access - only for local access */
1248 # define REG_sig(reg_name, context)             ((context)->uc_mcontext.regs->reg_name)
1249 /* Gpr Registers access  */
1250 # define GPR_sig(reg_num, context)              REG_sig(gpr[reg_num], context)
1251 # define IAR_sig(context)                       REG_sig(nip, context)   /* Program counter */
1252 # define MSR_sig(context)                       REG_sig(msr, context)   /* Machine State Register (Supervisor) */
1253 # define CTR_sig(context)                       REG_sig(ctr, context)   /* Count register */
1254 # define XER_sig(context)                       REG_sig(xer, context) /* User's integer exception register */
1255 # define LR_sig(context)                        REG_sig(link, context) /* Link register */
1256 # define CR_sig(context)                        REG_sig(ccr, context) /* Condition register */
1257 /* Float Registers access  */
1258 # define FLOAT_sig(reg_num, context)            (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1259 # define FPSCR_sig(context)                     (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1260 /* Exception Registers access */
1261 # define DAR_sig(context)                       REG_sig(dar, context)
1262 # define DSISR_sig(context)                     REG_sig(dsisr, context)
1263 # define TRAP_sig(context)                      REG_sig(trap, context)
1264 #endif /* linux */
1265
1266 #ifdef __APPLE__
1267 # include <sys/ucontext.h>
1268 typedef struct ucontext SIGCONTEXT;
1269 /* All Registers access - only for local access */
1270 # define REG_sig(reg_name, context)             ((context)->uc_mcontext->ss.reg_name)
1271 # define FLOATREG_sig(reg_name, context)        ((context)->uc_mcontext->fs.reg_name)
1272 # define EXCEPREG_sig(reg_name, context)        ((context)->uc_mcontext->es.reg_name)
1273 # define VECREG_sig(reg_name, context)          ((context)->uc_mcontext->vs.reg_name)
1274 /* Gpr Registers access */
1275 # define GPR_sig(reg_num, context)              REG_sig(r##reg_num, context)
1276 # define IAR_sig(context)                       REG_sig(srr0, context)  /* Program counter */
1277 # define MSR_sig(context)                       REG_sig(srr1, context)  /* Machine State Register (Supervisor) */
1278 # define CTR_sig(context)                       REG_sig(ctr, context)
1279 # define XER_sig(context)                       REG_sig(xer, context) /* Link register */
1280 # define LR_sig(context)                        REG_sig(lr, context)  /* User's integer exception register */
1281 # define CR_sig(context)                        REG_sig(cr, context)  /* Condition register */
1282 /* Float Registers access */
1283 # define FLOAT_sig(reg_num, context)            FLOATREG_sig(fpregs[reg_num], context)
1284 # define FPSCR_sig(context)                     ((double)FLOATREG_sig(fpscr, context))
1285 /* Exception Registers access */
1286 # define DAR_sig(context)                       EXCEPREG_sig(dar, context)     /* Fault registers for coredump */
1287 # define DSISR_sig(context)                     EXCEPREG_sig(dsisr, context)
1288 # define TRAP_sig(context)                      EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1289 #endif /* __APPLE__ */
1290
1291 int cpu_signal_handler(int host_signum, void *pinfo,
1292                        void *puc)
1293 {
1294     siginfo_t *info = pinfo;
1295     struct ucontext *uc = puc;
1296     unsigned long pc;
1297     int is_write;
1298
1299     pc = IAR_sig(uc);
1300     is_write = 0;
1301 #if 0
1302     /* ppc 4xx case */
1303     if (DSISR_sig(uc) & 0x00800000)
1304         is_write = 1;
1305 #else
1306     if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1307         is_write = 1;
1308 #endif
1309     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1310                              is_write, &uc->uc_sigmask, puc);
1311 }
1312
1313 #elif defined(__alpha__)
1314
1315 int cpu_signal_handler(int host_signum, void *pinfo,
1316                            void *puc)
1317 {
1318     siginfo_t *info = pinfo;
1319     struct ucontext *uc = puc;
1320     uint32_t *pc = uc->uc_mcontext.sc_pc;
1321     uint32_t insn = *pc;
1322     int is_write = 0;
1323
1324     /* XXX: need kernel patch to get write flag faster */
1325     switch (insn >> 26) {
1326     case 0x0d: // stw
1327     case 0x0e: // stb
1328     case 0x0f: // stq_u
1329     case 0x24: // stf
1330     case 0x25: // stg
1331     case 0x26: // sts
1332     case 0x27: // stt
1333     case 0x2c: // stl
1334     case 0x2d: // stq
1335     case 0x2e: // stl_c
1336     case 0x2f: // stq_c
1337         is_write = 1;
1338     }
1339
1340     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1341                              is_write, &uc->uc_sigmask, puc);
1342 }
1343 #elif defined(__sparc__)
1344
1345 int cpu_signal_handler(int host_signum, void *pinfo,
1346                        void *puc)
1347 {
1348     siginfo_t *info = pinfo;
1349     int is_write;
1350     uint32_t insn;
1351 #if !defined(__arch64__) || defined(HOST_SOLARIS)
1352     uint32_t *regs = (uint32_t *)(info + 1);
1353     void *sigmask = (regs + 20);
1354     /* XXX: is there a standard glibc define ? */
1355     unsigned long pc = regs[1];
1356 #else
1357 #ifdef __linux__
1358     struct sigcontext *sc = puc;
1359     unsigned long pc = sc->sigc_regs.tpc;
1360     void *sigmask = (void *)sc->sigc_mask;
1361 #elif defined(__OpenBSD__)
1362     struct sigcontext *uc = puc;
1363     unsigned long pc = uc->sc_pc;
1364     void *sigmask = (void *)(long)uc->sc_mask;
1365 #endif
1366 #endif
1367
1368     /* XXX: need kernel patch to get write flag faster */
1369     is_write = 0;
1370     insn = *(uint32_t *)pc;
1371     if ((insn >> 30) == 3) {
1372       switch((insn >> 19) & 0x3f) {
1373       case 0x05: // stb
1374       case 0x06: // sth
1375       case 0x04: // st
1376       case 0x07: // std
1377       case 0x24: // stf
1378       case 0x27: // stdf
1379       case 0x25: // stfsr
1380         is_write = 1;
1381         break;
1382       }
1383     }
1384     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1385                              is_write, sigmask, NULL);
1386 }
1387
1388 #elif defined(__arm__)
1389
1390 int cpu_signal_handler(int host_signum, void *pinfo,
1391                        void *puc)
1392 {
1393     siginfo_t *info = pinfo;
1394     struct ucontext *uc = puc;
1395     unsigned long pc;
1396     int is_write;
1397
1398 #if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
1399     pc = uc->uc_mcontext.gregs[R15];
1400 #else
1401     pc = uc->uc_mcontext.arm_pc;
1402 #endif
1403     /* XXX: compute is_write */
1404     is_write = 0;
1405     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1406                              is_write,
1407                              &uc->uc_sigmask, puc);
1408 }
1409
1410 #elif defined(__mc68000)
1411
1412 int cpu_signal_handler(int host_signum, void *pinfo,
1413                        void *puc)
1414 {
1415     siginfo_t *info = pinfo;
1416     struct ucontext *uc = puc;
1417     unsigned long pc;
1418     int is_write;
1419
1420     pc = uc->uc_mcontext.gregs[16];
1421     /* XXX: compute is_write */
1422     is_write = 0;
1423     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1424                              is_write,
1425                              &uc->uc_sigmask, puc);
1426 }
1427
1428 #elif defined(__ia64)
1429
1430 #ifndef __ISR_VALID
1431   /* This ought to be in <bits/siginfo.h>... */
1432 # define __ISR_VALID    1
1433 #endif
1434
1435 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
1436 {
1437     siginfo_t *info = pinfo;
1438     struct ucontext *uc = puc;
1439     unsigned long ip;
1440     int is_write = 0;
1441
1442     ip = uc->uc_mcontext.sc_ip;
1443     switch (host_signum) {
1444       case SIGILL:
1445       case SIGFPE:
1446       case SIGSEGV:
1447       case SIGBUS:
1448       case SIGTRAP:
1449           if (info->si_code && (info->si_segvflags & __ISR_VALID))
1450               /* ISR.W (write-access) is bit 33:  */
1451               is_write = (info->si_isr >> 33) & 1;
1452           break;
1453
1454       default:
1455           break;
1456     }
1457     return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1458                              is_write,
1459                              &uc->uc_sigmask, puc);
1460 }
1461
1462 #elif defined(__s390__)
1463
1464 int cpu_signal_handler(int host_signum, void *pinfo,
1465                        void *puc)
1466 {
1467     siginfo_t *info = pinfo;
1468     struct ucontext *uc = puc;
1469     unsigned long pc;
1470     int is_write;
1471
1472     pc = uc->uc_mcontext.psw.addr;
1473     /* XXX: compute is_write */
1474     is_write = 0;
1475     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1476                              is_write, &uc->uc_sigmask, puc);
1477 }
1478
1479 #elif defined(__mips__)
1480
1481 int cpu_signal_handler(int host_signum, void *pinfo,
1482                        void *puc)
1483 {
1484     siginfo_t *info = pinfo;
1485     struct ucontext *uc = puc;
1486     greg_t pc = uc->uc_mcontext.pc;
1487     int is_write;
1488
1489     /* XXX: compute is_write */
1490     is_write = 0;
1491     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1492                              is_write, &uc->uc_sigmask, puc);
1493 }
1494
1495 #elif defined(__hppa__)
1496
1497 int cpu_signal_handler(int host_signum, void *pinfo,
1498                        void *puc)
1499 {
1500     struct siginfo *info = pinfo;
1501     struct ucontext *uc = puc;
1502     unsigned long pc;
1503     int is_write;
1504
1505     pc = uc->uc_mcontext.sc_iaoq[0];
1506     /* FIXME: compute is_write */
1507     is_write = 0;
1508     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1509                              is_write,
1510                              &uc->uc_sigmask, puc);
1511 }
1512
1513 #else
1514
1515 #error host CPU specific signal handler needed
1516
1517 #endif
1518
1519 #endif /* !defined(CONFIG_SOFTMMU) */