qemu/sh4-dis.c

   1 /* Disassemble SH instructions.
   2    Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003, 2004
   3    Free Software Foundation, Inc.
   4
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 2 of the License, or
   8    (at your option) any later version.
   9
  10    This program is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with this program; if not, write to the Free Software
  17    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  18
  19 #include <stdio.h>
  20 #include "dis-asm.h"
  21
  22 #define DEFINE_TABLE
  23
  24 typedef enum
  25   {
  26     HEX_0,
  27     HEX_1,
  28     HEX_2,
  29     HEX_3,
  30     HEX_4,
  31     HEX_5,
  32     HEX_6,
  33     HEX_7,
  34     HEX_8,
  35     HEX_9,
  36     HEX_A,
  37     HEX_B,
  38     HEX_C,
  39     HEX_D,
  40     HEX_E,
  41     HEX_F,
  42     HEX_XX00,
  43     HEX_00YY,
  44     REG_N,
  45     REG_N_D,     /* nnn0 */
  46     REG_N_B01,   /* nn01 */
  47     REG_M,
  48     SDT_REG_N,
  49     REG_NM,
  50     REG_B,
  51     BRANCH_12,
  52     BRANCH_8,
  53     IMM0_4,
  54     IMM0_4BY2,
  55     IMM0_4BY4,
  56     IMM1_4,
  57     IMM1_4BY2,
  58     IMM1_4BY4,
  59     PCRELIMM_8BY2,
  60     PCRELIMM_8BY4,
  61     IMM0_8,
  62     IMM0_8BY2,
  63     IMM0_8BY4,
  64     IMM1_8,
  65     IMM1_8BY2,
  66     IMM1_8BY4,
  67     PPI,
  68     NOPX,
  69     NOPY,
  70     MOVX,
  71     MOVY,
  72     MOVX_NOPY,
  73     MOVY_NOPX,
  74     PSH,
  75     PMUL,
  76     PPI3,
  77     PPI3NC,
  78     PDC,
  79     PPIC,
  80     REPEAT,
  81     IMM0_3c,    /* xxxx 0iii */
  82     IMM0_3s,    /* xxxx 1iii */
  83     IMM0_3Uc,   /* 0iii xxxx */
  84     IMM0_3Us,   /* 1iii xxxx */
  85     IMM0_20_4,
  86     IMM0_20,    /* follows IMM0_20_4 */
  87     IMM0_20BY8, /* follows IMM0_20_4 */
  88     DISP0_12,
  89     DISP0_12BY2,
  90     DISP0_12BY4,
  91     DISP0_12BY8,
  92     DISP1_12,
  93     DISP1_12BY2,
  94     DISP1_12BY4,
  95     DISP1_12BY8
  96   }
  97 sh_nibble_type;
  98
  99 typedef enum
 100   {
 101     A_END,
 102     A_BDISP12,
 103     A_BDISP8,
 104     A_DEC_M,
 105     A_DEC_N,
 106     A_DISP_GBR,
 107     A_PC,
 108     A_DISP_PC,
 109     A_DISP_PC_ABS,
 110     A_DISP_REG_M,
 111     A_DISP_REG_N,
 112     A_GBR,
 113     A_IMM,
 114     A_INC_M,
 115     A_INC_N,
 116     A_IND_M,
 117     A_IND_N,
 118     A_IND_R0_REG_M,
 119     A_IND_R0_REG_N,
 120     A_MACH,
 121     A_MACL,
 122     A_PR,
 123     A_R0,
 124     A_R0_GBR,
 125     A_REG_M,
 126     A_REG_N,
 127     A_REG_B,
 128     A_SR,
 129     A_VBR,
 130     A_TBR,
 131     A_DISP_TBR,
 132     A_DISP2_TBR,
 133     A_DEC_R15,
 134     A_INC_R15,
 135     A_MOD,
 136     A_RE,
 137     A_RS,
 138     A_DSR,
 139     DSP_REG_M,
 140     DSP_REG_N,
 141     DSP_REG_X,
 142     DSP_REG_Y,
 143     DSP_REG_E,
 144     DSP_REG_F,
 145     DSP_REG_G,
 146     DSP_REG_A_M,
 147     DSP_REG_AX,
 148     DSP_REG_XY,
 149     DSP_REG_AY,
 150     DSP_REG_YX,
 151     AX_INC_N,
 152     AY_INC_N,
 153     AXY_INC_N,
 154     AYX_INC_N,
 155     AX_IND_N,
 156     AY_IND_N,
 157     AXY_IND_N,
 158     AYX_IND_N,
 159     AX_PMOD_N,
 160     AXY_PMOD_N,
 161     AY_PMOD_N,
 162     AYX_PMOD_N,
 163     AS_DEC_N,
 164     AS_INC_N,
 165     AS_IND_N,
 166     AS_PMOD_N,
 167     A_A0,
 168     A_X0,
 169     A_X1,
 170     A_Y0,
 171     A_Y1,
 172     A_SSR,
 173     A_SPC,
 174     A_SGR,
 175     A_DBR,
 176     F_REG_N,
 177     F_REG_M,
 178     D_REG_N,
 179     D_REG_M,
 180     X_REG_N, /* Only used for argument parsing.  */
 181     X_REG_M, /* Only used for argument parsing.  */
 182     DX_REG_N,
 183     DX_REG_M,
 184     V_REG_N,
 185     V_REG_M,
 186     XMTRX_M4,
 187     F_FR0,
 188     FPUL_N,
 189     FPUL_M,
 190     FPSCR_N,
 191     FPSCR_M
 192   }
 193 sh_arg_type;
 194
 195 typedef enum
 196   {
 197     A_A1_NUM =   5,
 198     A_A0_NUM =   7,
 199     A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM,
 200     A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM
 201   }
 202 sh_dsp_reg_nums;
 203
 204 #define arch_sh1_base   0x0001
 205 #define arch_sh2_base   0x0002
 206 #define arch_sh3_base   0x0004
 207 #define arch_sh4_base   0x0008
 208 #define arch_sh4a_base  0x0010
 209 #define arch_sh2a_base  0x0020
 210
 211 /* This is an annotation on instruction types, but we abuse the arch
 212    field in instructions to denote it.  */
 213 #define arch_op32       0x00100000 /* This is a 32-bit opcode.  */
 214
 215 #define arch_sh_no_mmu  0x04000000
 216 #define arch_sh_has_mmu 0x08000000
 217 #define arch_sh_no_co   0x10000000 /* neither FPU nor DSP co-processor */
 218 #define arch_sh_sp_fpu  0x20000000 /* single precision FPU */
 219 #define arch_sh_dp_fpu  0x40000000 /* double precision FPU */
 220 #define arch_sh_has_dsp 0x80000000
 221
 222
 223 #define arch_sh_base_mask 0x0000003f
 224 #define arch_opann_mask   0x00100000
 225 #define arch_sh_mmu_mask  0x0c000000
 226 #define arch_sh_co_mask   0xf0000000
 227
 228
 229 #define arch_sh1        (arch_sh1_base|arch_sh_no_mmu|arch_sh_no_co)
 230 #define arch_sh2        (arch_sh2_base|arch_sh_no_mmu|arch_sh_no_co)
 231 #define arch_sh2a       (arch_sh2a_base|arch_sh_no_mmu|arch_sh_dp_fpu)
 232 #define arch_sh2a_nofpu (arch_sh2a_base|arch_sh_no_mmu|arch_sh_no_co)
 233 #define arch_sh2e       (arch_sh2_base|arch_sh2a_base|arch_sh_no_mmu|arch_sh_sp_fpu)
 234 #define arch_sh_dsp     (arch_sh2_base|arch_sh_no_mmu|arch_sh_has_dsp)
 235 #define arch_sh3_nommu  (arch_sh3_base|arch_sh_no_mmu|arch_sh_no_co)
 236 #define arch_sh3        (arch_sh3_base|arch_sh_has_mmu|arch_sh_no_co)
 237 #define arch_sh3e       (arch_sh3_base|arch_sh_has_mmu|arch_sh_sp_fpu)
 238 #define arch_sh3_dsp    (arch_sh3_base|arch_sh_has_mmu|arch_sh_has_dsp)
 239 #define arch_sh4        (arch_sh4_base|arch_sh_has_mmu|arch_sh_dp_fpu)
 240 #define arch_sh4a       (arch_sh4a_base|arch_sh_has_mmu|arch_sh_dp_fpu)
 241 #define arch_sh4al_dsp  (arch_sh4a_base|arch_sh_has_mmu|arch_sh_has_dsp)
 242 #define arch_sh4_nofpu  (arch_sh4_base|arch_sh_has_mmu|arch_sh_no_co)
 243 #define arch_sh4a_nofpu (arch_sh4a_base|arch_sh_has_mmu|arch_sh_no_co)
 244 #define arch_sh4_nommu_nofpu (arch_sh4_base|arch_sh_no_mmu|arch_sh_no_co)
 245
 246 #define SH_MERGE_ARCH_SET(SET1, SET2) ((SET1) & (SET2))
 247 #define SH_VALID_BASE_ARCH_SET(SET) (((SET) & arch_sh_base_mask) != 0)
 248 #define SH_VALID_MMU_ARCH_SET(SET)  (((SET) & arch_sh_mmu_mask) != 0)
 249 #define SH_VALID_CO_ARCH_SET(SET)   (((SET) & arch_sh_co_mask) != 0)
 250 #define SH_VALID_ARCH_SET(SET) \
 251   (SH_VALID_BASE_ARCH_SET (SET) \
 252    && SH_VALID_MMU_ARCH_SET (SET) \
 253    && SH_VALID_CO_ARCH_SET (SET))
 254 #define SH_MERGE_ARCH_SET_VALID(SET1, SET2) \
 255   SH_VALID_ARCH_SET (SH_MERGE_ARCH_SET (SET1, SET2))
 256
 257 #define SH_ARCH_SET_HAS_FPU(SET) \
 258   (((SET) & (arch_sh_sp_fpu | arch_sh_dp_fpu)) != 0)
 259 #define SH_ARCH_SET_HAS_DSP(SET) \
 260   (((SET) & arch_sh_has_dsp) != 0)
 261
 262 /* This is returned from the functions below when an error occurs
 263    (in addition to a call to BFD_FAIL). The value should allow
 264    the tools to continue to function in most cases - there may
 265    be some confusion between DSP and FPU etc.  */
 266 #define SH_ARCH_UNKNOWN_ARCH 0xffffffff
 267
 268 /* These are defined in bfd/cpu-sh.c .  */
 269 unsigned int sh_get_arch_from_bfd_mach (unsigned long mach);
 270 unsigned int sh_get_arch_up_from_bfd_mach (unsigned long mach);
 271 unsigned long sh_get_bfd_mach_from_arch_set (unsigned int arch_set);
 272 /* bfd_boolean sh_merge_bfd_arch (bfd *ibfd, bfd *obfd); */
 273
 274 /* Below are the 'architecture sets'.
 275    They describe the following inheritance graph:
 276
 277                 SH1
 278                  |
 279                 SH2
 280    .------------'|`--------------------.
 281   /              |                      \
 282 SH-DSP          SH3-nommu               SH2E
 283  |               |`--------.             |
 284  |               |          \            |
 285  |              SH3     SH4-nommu-nofpu  |
 286  |               |           |           |
 287  | .------------'|`----------+---------. |
 288  |/                         /           \|
 289  |               | .-------'             |
 290  |               |/                      |
 291 SH3-dsp         SH4-nofpu               SH3E
 292  |               |`--------------------. |
 293  |               |                      \|
 294  |              SH4A-nofpu              SH4
 295  | .------------' `--------------------. |
 296  |/                                     \|
 297 SH4AL-dsp                               SH4A
 298
 299 */
 300
 301 /* Central branches */
 302 #define arch_sh1_up       (arch_sh1 | arch_sh2_up)
 303 #define arch_sh2_up       (arch_sh2 | arch_sh2e_up | arch_sh2a_nofpu_up | arch_sh3_nommu_up | arch_sh_dsp_up)
 304 #define arch_sh3_nommu_up (arch_sh3_nommu | arch_sh3_up | arch_sh4_nommu_nofpu_up)
 305 #define arch_sh3_up       (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up | arch_sh4_nofp_up)
 306 #define arch_sh4_nommu_nofpu_up (arch_sh4_nommu_nofpu | arch_sh4_nofp_up)
 307 #define arch_sh4_nofp_up  (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up)
 308 #define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up)
 309
 310 /* Right branch */
 311 #define arch_sh2e_up (arch_sh2e | arch_sh2a_up | arch_sh3e_up)
 312 #define arch_sh3e_up (arch_sh3e | arch_sh4_up)
 313 #define arch_sh4_up  (arch_sh4 | arch_sh4a_up)
 314 #define arch_sh4a_up (arch_sh4a)
 315
 316 /* Left branch */
 317 #define arch_sh_dsp_up    (arch_sh_dsp | arch_sh3_dsp_up)
 318 #define arch_sh3_dsp_up   (arch_sh3_dsp | arch_sh4al_dsp_up)
 319 #define arch_sh4al_dsp_up (arch_sh4al_dsp)
 320
 321 /* SH 2a branched off SH2e, adding a lot but not all of SH4 and SH4a.  */
 322 #define arch_sh2a_up        (arch_sh2a)
 323 #define arch_sh2a_nofpu_up  (arch_sh2a_nofpu | arch_sh2a_up)
 324
 325
 326 typedef struct
 327 {
 328   const char *name;
 329   sh_arg_type arg[4];
 330   sh_nibble_type nibbles[9];
 331   unsigned int arch;
 332 } sh_opcode_info;
 333
 334 #ifdef DEFINE_TABLE
 335
 336 const sh_opcode_info sh_table[] =
 337   {
 338 /* 0111nnnni8*1.... add #<imm>,<REG_N>  */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up},
 339
 340 /* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up},
 341
 342 /* 0011nnnnmmmm1110 addc <REG_M>,<REG_N>*/{"addc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_E}, arch_sh1_up},
 343
 344 /* 0011nnnnmmmm1111 addv <REG_M>,<REG_N>*/{"addv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_F}, arch_sh1_up},
 345
 346 /* 11001001i8*1.... and #<imm>,R0       */{"and",{A_IMM,A_R0},{HEX_C,HEX_9,IMM0_8}, arch_sh1_up},
 347
 348 /* 0010nnnnmmmm1001 and <REG_M>,<REG_N> */{"and",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_9}, arch_sh1_up},
 349
 350 /* 11001101i8*1.... and.b #<imm>,@(R0,GBR)*/{"and.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_D,IMM0_8}, arch_sh1_up},
 351
 352 /* 1010i12......... bra <bdisp12>       */{"bra",{A_BDISP12},{HEX_A,BRANCH_12}, arch_sh1_up},
 353
 354 /* 1011i12......... bsr <bdisp12>       */{"bsr",{A_BDISP12},{HEX_B,BRANCH_12}, arch_sh1_up},
 355
 356 /* 10001001i8p1.... bt <bdisp8>         */{"bt",{A_BDISP8},{HEX_8,HEX_9,BRANCH_8}, arch_sh1_up},
 357
 358 /* 10001011i8p1.... bf <bdisp8>         */{"bf",{A_BDISP8},{HEX_8,HEX_B,BRANCH_8}, arch_sh1_up},
 359
 360 /* 10001101i8p1.... bt.s <bdisp8>       */{"bt.s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},
 361
 362 /* 10001101i8p1.... bt/s <bdisp8>       */{"bt/s",{A_BDISP8},{HEX_8,HEX_D,BRANCH_8}, arch_sh2_up},
 363
 364 /* 10001111i8p1.... bf.s <bdisp8>       */{"bf.s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
 365
 366 /* 10001111i8p1.... bf/s <bdisp8>       */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up},
 367
 368 /* 0000000010001000 clrdmxy             */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up},
 369
 370 /* 0000000000101000 clrmac              */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up},
 371
 372 /* 0000000001001000 clrs                */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up},
 373
 374 /* 0000000000001000 clrt                */{"clrt",{0},{HEX_0,HEX_0,HEX_0,HEX_8}, arch_sh1_up},
 375
 376 /* 10001000i8*1.... cmp/eq #<imm>,R0    */{"cmp/eq",{A_IMM,A_R0},{HEX_8,HEX_8,IMM0_8}, arch_sh1_up},
 377
 378 /* 0011nnnnmmmm0000 cmp/eq <REG_M>,<REG_N>*/{"cmp/eq",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_0}, arch_sh1_up},
 379
 380 /* 0011nnnnmmmm0011 cmp/ge <REG_M>,<REG_N>*/{"cmp/ge",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_3}, arch_sh1_up},
 381
 382 /* 0011nnnnmmmm0111 cmp/gt <REG_M>,<REG_N>*/{"cmp/gt",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_7}, arch_sh1_up},
 383
 384 /* 0011nnnnmmmm0110 cmp/hi <REG_M>,<REG_N>*/{"cmp/hi",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_6}, arch_sh1_up},
 385
 386 /* 0011nnnnmmmm0010 cmp/hs <REG_M>,<REG_N>*/{"cmp/hs",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_2}, arch_sh1_up},
 387
 388 /* 0100nnnn00010101 cmp/pl <REG_N>      */{"cmp/pl",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_5}, arch_sh1_up},
 389
 390 /* 0100nnnn00010001 cmp/pz <REG_N>      */{"cmp/pz",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_1}, arch_sh1_up},
 391
 392 /* 0010nnnnmmmm1100 cmp/str <REG_M>,<REG_N>*/{"cmp/str",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_C}, arch_sh1_up},
 393
 394 /* 0010nnnnmmmm0111 div0s <REG_M>,<REG_N>*/{"div0s",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_7}, arch_sh1_up},
 395
 396 /* 0000000000011001 div0u               */{"div0u",{0},{HEX_0,HEX_0,HEX_1,HEX_9}, arch_sh1_up},
 397
 398 /* 0011nnnnmmmm0100 div1 <REG_M>,<REG_N>*/{"div1",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_4}, arch_sh1_up},
 399
 400 /* 0110nnnnmmmm1110 exts.b <REG_M>,<REG_N>*/{"exts.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_E}, arch_sh1_up},
 401
 402 /* 0110nnnnmmmm1111 exts.w <REG_M>,<REG_N>*/{"exts.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_F}, arch_sh1_up},
 403
 404 /* 0110nnnnmmmm1100 extu.b <REG_M>,<REG_N>*/{"extu.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_C}, arch_sh1_up},
 405
 406 /* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up},
 407
 408 /* 0000nnnn11100011 icbi @<REG_N>       */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up},
 409
 410 /* 0100nnnn00101011 jmp @<REG_N>        */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up},
 411
 412 /* 0100nnnn00001011 jsr @<REG_N>        */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up},
 413
 414 /* 0100nnnn00001110 ldc <REG_N>,SR      */{"ldc",{A_REG_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_E}, arch_sh1_up},
 415
 416 /* 0100nnnn00011110 ldc <REG_N>,GBR     */{"ldc",{A_REG_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_E}, arch_sh1_up},
 417
 418 /* 0100nnnn00111010 ldc <REG_N>,SGR     */{"ldc",{A_REG_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
 419
 420 /* 0100mmmm01001010 ldc <REG_M>,TBR     */{"ldc",{A_REG_M,A_TBR},{HEX_4,REG_M,HEX_4,HEX_A}, arch_sh2a_nofpu_up},
 421
 422 /* 0100nnnn00101110 ldc <REG_N>,VBR     */{"ldc",{A_REG_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_E}, arch_sh1_up},
 423
 424 /* 0100nnnn01011110 ldc <REG_N>,MOD     */{"ldc",{A_REG_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_E}, arch_sh_dsp_up},
 425
 426 /* 0100nnnn01111110 ldc <REG_N>,RE     */{"ldc",{A_REG_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_E}, arch_sh_dsp_up},
 427
 428 /* 0100nnnn01101110 ldc <REG_N>,RS     */{"ldc",{A_REG_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_E}, arch_sh_dsp_up},
 429
 430 /* 0100nnnn00111110 ldc <REG_N>,SSR     */{"ldc",{A_REG_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_E}, arch_sh3_nommu_up},
 431
 432 /* 0100nnnn01001110 ldc <REG_N>,SPC     */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_nommu_up},
 433
 434 /* 0100nnnn11111010 ldc <REG_N>,DBR     */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
 435
 436 /* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_nommu_up},
 437
 438 /* 0100nnnn00000111 ldc.l @<REG_N>+,SR  */{"ldc.l",{A_INC_N,A_SR},{HEX_4,REG_N,HEX_0,HEX_7}, arch_sh1_up},
 439
 440 /* 0100nnnn00010111 ldc.l @<REG_N>+,GBR */{"ldc.l",{A_INC_N,A_GBR},{HEX_4,REG_N,HEX_1,HEX_7}, arch_sh1_up},
 441
 442 /* 0100nnnn00100111 ldc.l @<REG_N>+,VBR */{"ldc.l",{A_INC_N,A_VBR},{HEX_4,REG_N,HEX_2,HEX_7}, arch_sh1_up},
 443
 444 /* 0100nnnn00110110 ldc.l @<REG_N>+,SGR */{"ldc.l",{A_INC_N,A_SGR},{HEX_4,REG_N,HEX_3,HEX_6}, arch_sh4_nommu_nofpu_up},
 445
 446 /* 0100nnnn01010111 ldc.l @<REG_N>+,MOD */{"ldc.l",{A_INC_N,A_MOD},{HEX_4,REG_N,HEX_5,HEX_7}, arch_sh_dsp_up},
 447
 448 /* 0100nnnn01110111 ldc.l @<REG_N>+,RE */{"ldc.l",{A_INC_N,A_RE},{HEX_4,REG_N,HEX_7,HEX_7}, arch_sh_dsp_up},
 449
 450 /* 0100nnnn01100111 ldc.l @<REG_N>+,RS */{"ldc.l",{A_INC_N,A_RS},{HEX_4,REG_N,HEX_6,HEX_7}, arch_sh_dsp_up},
 451
 452 /* 0100nnnn00110111 ldc.l @<REG_N>+,SSR */{"ldc.l",{A_INC_N,A_SSR},{HEX_4,REG_N,HEX_3,HEX_7}, arch_sh3_nommu_up},
 453
 454 /* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_nommu_up},
 455
 456 /* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nommu_nofpu_up},
 457
 458 /* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_nommu_up},
 459
 460 /* 0100mmmm00110100 ldrc <REG_M>        */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up},
 461 /* 10001010i8*1.... ldrc #<imm>         */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up},
 462
 463 /* 10001110i8p2.... ldre @(<disp>,PC)   */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up},
 464
 465 /* 10001100i8p2.... ldrs @(<disp>,PC)   */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up},
 466
 467 /* 0100nnnn00001010 lds <REG_N>,MACH    */{"lds",{A_REG_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_A}, arch_sh1_up},
 468
 469 /* 0100nnnn00011010 lds <REG_N>,MACL    */{"lds",{A_REG_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_A}, arch_sh1_up},
 470
 471 /* 0100nnnn00101010 lds <REG_N>,PR      */{"lds",{A_REG_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_A}, arch_sh1_up},
 472
 473 /* 0100nnnn01101010 lds <REG_N>,DSR     */{"lds",{A_REG_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},
 474
 475 /* 0100nnnn01111010 lds <REG_N>,A0      */{"lds",{A_REG_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},
 476
 477 /* 0100nnnn10001010 lds <REG_N>,X0      */{"lds",{A_REG_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},
 478
 479 /* 0100nnnn10011010 lds <REG_N>,X1      */{"lds",{A_REG_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},
 480
 481 /* 0100nnnn10101010 lds <REG_N>,Y0      */{"lds",{A_REG_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},
 482
 483 /* 0100nnnn10111010 lds <REG_N>,Y1      */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
 484
 485 /* 0100nnnn01011010 lds <REG_N>,FPUL    */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up},
 486
 487 /* 0100nnnn01101010 lds <REG_M>,FPSCR   */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up},
 488
 489 /* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up},
 490
 491 /* 0100nnnn00010110 lds.l @<REG_N>+,MACL*/{"lds.l",{A_INC_N,A_MACL},{HEX_4,REG_N,HEX_1,HEX_6}, arch_sh1_up},
 492
 493 /* 0100nnnn00100110 lds.l @<REG_N>+,PR  */{"lds.l",{A_INC_N,A_PR},{HEX_4,REG_N,HEX_2,HEX_6}, arch_sh1_up},
 494
 495 /* 0100nnnn01100110 lds.l @<REG_N>+,DSR */{"lds.l",{A_INC_N,A_DSR},{HEX_4,REG_N,HEX_6,HEX_6}, arch_sh_dsp_up},
 496
 497 /* 0100nnnn01110110 lds.l @<REG_N>+,A0  */{"lds.l",{A_INC_N,A_A0},{HEX_4,REG_N,HEX_7,HEX_6}, arch_sh_dsp_up},
 498
 499 /* 0100nnnn10000110 lds.l @<REG_N>+,X0  */{"lds.l",{A_INC_N,A_X0},{HEX_4,REG_N,HEX_8,HEX_6}, arch_sh_dsp_up},
 500
 501 /* 0100nnnn10010110 lds.l @<REG_N>+,X1  */{"lds.l",{A_INC_N,A_X1},{HEX_4,REG_N,HEX_9,HEX_6}, arch_sh_dsp_up},
 502
 503 /* 0100nnnn10100110 lds.l @<REG_N>+,Y0  */{"lds.l",{A_INC_N,A_Y0},{HEX_4,REG_N,HEX_A,HEX_6}, arch_sh_dsp_up},
 504
 505 /* 0100nnnn10110110 lds.l @<REG_N>+,Y1  */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up},
 506
 507 /* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up},
 508
 509 /* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up},
 510
 511 /* 0000000000111000 ldtlb               */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up},
 512
 513 /* 0100nnnnmmmm1111 mac.w @<REG_M>+,@<REG_N>+*/{"mac.w",{A_INC_M,A_INC_N},{HEX_4,REG_N,REG_M,HEX_F}, arch_sh1_up},
 514
 515 /* 1110nnnni8*1.... mov #<imm>,<REG_N>  */{"mov",{A_IMM,A_REG_N},{HEX_E,REG_N,IMM0_8}, arch_sh1_up},
 516
 517 /* 0110nnnnmmmm0011 mov <REG_M>,<REG_N> */{"mov",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_3}, arch_sh1_up},
 518
 519 /* 0000nnnnmmmm0100 mov.b <REG_M>,@(R0,<REG_N>)*/{"mov.b",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_4}, arch_sh1_up},
 520
 521 /* 0010nnnnmmmm0100 mov.b <REG_M>,@-<REG_N>*/{"mov.b",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_4}, arch_sh1_up},
 522
 523 /* 0010nnnnmmmm0000 mov.b <REG_M>,@<REG_N>*/{"mov.b",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_0}, arch_sh1_up},
 524
 525 /* 10000100mmmmi4*1 mov.b @(<disp>,<REG_M>),R0*/{"mov.b",{A_DISP_REG_M,A_R0},{HEX_8,HEX_4,REG_M,IMM0_4}, arch_sh1_up},
 526
 527 /* 11000100i8*1.... mov.b @(<disp>,GBR),R0*/{"mov.b",{A_DISP_GBR,A_R0},{HEX_C,HEX_4,IMM0_8}, arch_sh1_up},
 528
 529 /* 0000nnnnmmmm1100 mov.b @(R0,<REG_M>),<REG_N>*/{"mov.b",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_C}, arch_sh1_up},
 530
 531 /* 0110nnnnmmmm0100 mov.b @<REG_M>+,<REG_N>*/{"mov.b",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_4}, arch_sh1_up},
 532
 533 /* 0110nnnnmmmm0000 mov.b @<REG_M>,<REG_N>*/{"mov.b",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_0}, arch_sh1_up},
 534
 535 /* 10000000mmmmi4*1 mov.b R0,@(<disp>,<REG_M>)*/{"mov.b",{A_R0,A_DISP_REG_M},{HEX_8,HEX_0,REG_M,IMM1_4}, arch_sh1_up},
 536
 537 /* 11000000i8*1.... mov.b R0,@(<disp>,GBR)*/{"mov.b",{A_R0,A_DISP_GBR},{HEX_C,HEX_0,IMM1_8}, arch_sh1_up},
 538
 539 /* 0100nnnn10001011 mov.b R0,@<REG_N>+ */{"mov.b",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_8,HEX_B}, arch_sh2a_nofpu_up},
 540 /* 0100nnnn11001011 mov.b @-<REG_M>,R0 */{"mov.b",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_C,HEX_B}, arch_sh2a_nofpu_up},
 541 /* 0011nnnnmmmm0001 0000dddddddddddd mov.b <REG_M>,@(<DISP12>,<REG_N>) */
 542 {"mov.b",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
 543 /* 0011nnnnmmmm0001 0100dddddddddddd mov.b @(<DISP12>,<REG_M>),<REG_N> */
 544 {"mov.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_4,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
 545 /* 0001nnnnmmmmi4*4 mov.l <REG_M>,@(<disp>,<REG_N>)*/{"mov.l",{ A_REG_M,A_DISP_REG_N},{HEX_1,REG_N,REG_M,IMM1_4BY4}, arch_sh1_up},
 546
 547 /* 0000nnnnmmmm0110 mov.l <REG_M>,@(R0,<REG_N>)*/{"mov.l",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_6}, arch_sh1_up},
 548
 549 /* 0010nnnnmmmm0110 mov.l <REG_M>,@-<REG_N>*/{"mov.l",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_6}, arch_sh1_up},
 550
 551 /* 0010nnnnmmmm0010 mov.l <REG_M>,@<REG_N>*/{"mov.l",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_2}, arch_sh1_up},
 552
 553 /* 0101nnnnmmmmi4*4 mov.l @(<disp>,<REG_M>),<REG_N>*/{"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_5,REG_N,REG_M,IMM0_4BY4}, arch_sh1_up},
 554
 555 /* 11000110i8*4.... mov.l @(<disp>,GBR),R0*/{"mov.l",{A_DISP_GBR,A_R0},{HEX_C,HEX_6,IMM0_8BY4}, arch_sh1_up},
 556
 557 /* 1101nnnni8p4.... mov.l @(<disp>,PC),<REG_N>*/{"mov.l",{A_DISP_PC,A_REG_N},{HEX_D,REG_N,PCRELIMM_8BY4}, arch_sh1_up},
 558
 559 /* 0000nnnnmmmm1110 mov.l @(R0,<REG_M>),<REG_N>*/{"mov.l",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_E}, arch_sh1_up},
 560
 561 /* 0110nnnnmmmm0110 mov.l @<REG_M>+,<REG_N>*/{"mov.l",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_6}, arch_sh1_up},
 562
 563 /* 0110nnnnmmmm0010 mov.l @<REG_M>,<REG_N>*/{"mov.l",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_2}, arch_sh1_up},
 564
 565 /* 11000010i8*4.... mov.l R0,@(<disp>,GBR)*/{"mov.l",{A_R0,A_DISP_GBR},{HEX_C,HEX_2,IMM1_8BY4}, arch_sh1_up},
 566
 567 /* 0100nnnn10101011 mov.l R0,@<REG_N>+ */{"mov.l",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_A,HEX_B}, arch_sh2a_nofpu_up},
 568 /* 0100nnnn11001011 mov.l @-<REG_M>,R0 */{"mov.l",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_B}, arch_sh2a_nofpu_up},
 569 /* 0011nnnnmmmm0001 0010dddddddddddd mov.l <REG_M>,@(<DISP12>,<REG_N>) */
 570 {"mov.l",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_2,DISP1_12BY4}, arch_sh2a_nofpu_up | arch_op32},
 571 /* 0011nnnnmmmm0001 0110dddddddddddd mov.l @(<DISP12>,<REG_M>),<REG_N> */
 572 {"mov.l",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_6,DISP0_12BY4}, arch_sh2a_nofpu_up | arch_op32},
 573 /* 0000nnnnmmmm0101 mov.w <REG_M>,@(R0,<REG_N>)*/{"mov.w",{ A_REG_M,A_IND_R0_REG_N},{HEX_0,REG_N,REG_M,HEX_5}, arch_sh1_up},
 574
 575 /* 0010nnnnmmmm0101 mov.w <REG_M>,@-<REG_N>*/{"mov.w",{ A_REG_M,A_DEC_N},{HEX_2,REG_N,REG_M,HEX_5}, arch_sh1_up},
 576
 577 /* 0010nnnnmmmm0001 mov.w <REG_M>,@<REG_N>*/{"mov.w",{ A_REG_M,A_IND_N},{HEX_2,REG_N,REG_M,HEX_1}, arch_sh1_up},
 578
 579 /* 10000101mmmmi4*2 mov.w @(<disp>,<REG_M>),R0*/{"mov.w",{A_DISP_REG_M,A_R0},{HEX_8,HEX_5,REG_M,IMM0_4BY2}, arch_sh1_up},
 580
 581 /* 11000101i8*2.... mov.w @(<disp>,GBR),R0*/{"mov.w",{A_DISP_GBR,A_R0},{HEX_C,HEX_5,IMM0_8BY2}, arch_sh1_up},
 582
 583 /* 1001nnnni8p2.... mov.w @(<disp>,PC),<REG_N>*/{"mov.w",{A_DISP_PC,A_REG_N},{HEX_9,REG_N,PCRELIMM_8BY2}, arch_sh1_up},
 584
 585 /* 0000nnnnmmmm1101 mov.w @(R0,<REG_M>),<REG_N>*/{"mov.w",{A_IND_R0_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_D}, arch_sh1_up},
 586
 587 /* 0110nnnnmmmm0101 mov.w @<REG_M>+,<REG_N>*/{"mov.w",{A_INC_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_5}, arch_sh1_up},
 588
 589 /* 0110nnnnmmmm0001 mov.w @<REG_M>,<REG_N>*/{"mov.w",{A_IND_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_1}, arch_sh1_up},
 590
 591 /* 10000001mmmmi4*2 mov.w R0,@(<disp>,<REG_M>)*/{"mov.w",{A_R0,A_DISP_REG_M},{HEX_8,HEX_1,REG_M,IMM1_4BY2}, arch_sh1_up},
 592
 593 /* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up},
 594
 595 /* 0100nnnn10011011 mov.w R0,@<REG_N>+ */{"mov.w",{A_R0,A_INC_N},{HEX_4,REG_N,HEX_9,HEX_B}, arch_sh2a_nofpu_up},
 596 /* 0100nnnn11011011 mov.w @-<REG_M>,R0 */{"mov.w",{A_DEC_M,A_R0},{HEX_4,REG_M,HEX_D,HEX_B}, arch_sh2a_nofpu_up},
 597 /* 0011nnnnmmmm0001 0001dddddddddddd mov.w <REG_M>,@(<DISP12>,<REG_N>) */
 598 {"mov.w",{A_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_1,DISP1_12BY2}, arch_sh2a_nofpu_up | arch_op32},
 599 /* 0011nnnnmmmm0001 0101dddddddddddd mov.w @(<DISP12>,<REG_M>),<REG_N> */
 600 {"mov.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_5,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
 601 /* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up},
 602 /* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nommu_nofpu_up},
 603
 604 /* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up},
 605 /* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up},
 606
 607 /* 0000nnnn00101001 movt <REG_N>        */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up},
 608
 609 /* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up},
 610 /* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up},
 611
 612 /* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
 613 /* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up},
 614
 615 /* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh2_up},
 616
 617 /* 0010nnnnmmmm1110 mulu.w <REG_M>,<REG_N>*/{"mulu.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up},
 618 /* 0010nnnnmmmm1110 mulu <REG_M>,<REG_N>*/{"mulu",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_E}, arch_sh1_up},
 619
 620 /* 0110nnnnmmmm1011 neg <REG_M>,<REG_N> */{"neg",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_B}, arch_sh1_up},
 621
 622 /* 0110nnnnmmmm1010 negc <REG_M>,<REG_N>*/{"negc",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_A}, arch_sh1_up},
 623
 624 /* 0000000000001001 nop                 */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up},
 625
 626 /* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up},
 627 /* 0000nnnn10010011 ocbi @<REG_N>       */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nommu_nofpu_up},
 628
 629 /* 0000nnnn10100011 ocbp @<REG_N>       */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nommu_nofpu_up},
 630
 631 /* 0000nnnn10110011 ocbwb @<REG_N>      */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nommu_nofpu_up},
 632
 633
 634 /* 11001011i8*1.... or #<imm>,R0        */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up},
 635
 636 /* 0010nnnnmmmm1011 or <REG_M>,<REG_N>  */{"or",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_B}, arch_sh1_up},
 637
 638 /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up},
 639
 640 /* 0000nnnn10000011 pref @<REG_N>       */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nommu_nofpu_up | arch_sh2a_nofpu_up},
 641
 642 /* 0000nnnn11010011 prefi @<REG_N>      */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up},
 643
 644 /* 0100nnnn00100100 rotcl <REG_N>       */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up},
 645
 646 /* 0100nnnn00100101 rotcr <REG_N>       */{"rotcr",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_5}, arch_sh1_up},
 647
 648 /* 0100nnnn00000100 rotl <REG_N>        */{"rotl",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_4}, arch_sh1_up},
 649
 650 /* 0100nnnn00000101 rotr <REG_N>        */{"rotr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_5}, arch_sh1_up},
 651
 652 /* 0000000000101011 rte                 */{"rte",{0},{HEX_0,HEX_0,HEX_2,HEX_B}, arch_sh1_up},
 653
 654 /* 0000000000001011 rts                 */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up},
 655
 656 /* 0000000010011000 setdmx              */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up},
 657 /* 0000000011001000 setdmy              */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up},
 658
 659 /* 0000000001011000 sets                */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up},
 660 /* 0000000000011000 sett                */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up},
 661
 662 /* 0100nnnn00010100 setrc <REG_N>       */{"setrc",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
 663
 664 /* 10000010i8*1.... setrc #<imm>        */{"setrc",{A_IMM},{HEX_8,HEX_2,IMM0_8}, arch_sh_dsp_up},
 665
 666 /* repeat start end <REG_N>             */{"repeat",{A_DISP_PC,A_DISP_PC,A_REG_N},{REPEAT,REG_N,HEX_1,HEX_4}, arch_sh_dsp_up},
 667
 668 /* repeat start end #<imm>              */{"repeat",{A_DISP_PC,A_DISP_PC,A_IMM},{REPEAT,HEX_2,IMM0_8,HEX_8}, arch_sh_dsp_up},
 669
 670 /* 0100nnnnmmmm1100 shad <REG_M>,<REG_N>*/{"shad",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_C}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
 671
 672 /* 0100nnnnmmmm1101 shld <REG_M>,<REG_N>*/{"shld",{ A_REG_M,A_REG_N},{HEX_4,REG_N,REG_M,HEX_D}, arch_sh3_nommu_up | arch_sh2a_nofpu_up},
 673
 674 /* 0100nnnn00100000 shal <REG_N>        */{"shal",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_0}, arch_sh1_up},
 675
 676 /* 0100nnnn00100001 shar <REG_N>        */{"shar",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_1}, arch_sh1_up},
 677
 678 /* 0100nnnn00000000 shll <REG_N>        */{"shll",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_0}, arch_sh1_up},
 679
 680 /* 0100nnnn00101000 shll16 <REG_N>      */{"shll16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_8}, arch_sh1_up},
 681
 682 /* 0100nnnn00001000 shll2 <REG_N>       */{"shll2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_8}, arch_sh1_up},
 683
 684 /* 0100nnnn00011000 shll8 <REG_N>       */{"shll8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_8}, arch_sh1_up},
 685
 686 /* 0100nnnn00000001 shlr <REG_N>        */{"shlr",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_1}, arch_sh1_up},
 687
 688 /* 0100nnnn00101001 shlr16 <REG_N>      */{"shlr16",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_9}, arch_sh1_up},
 689
 690 /* 0100nnnn00001001 shlr2 <REG_N>       */{"shlr2",{A_REG_N},{HEX_4,REG_N,HEX_0,HEX_9}, arch_sh1_up},
 691
 692 /* 0100nnnn00011001 shlr8 <REG_N>       */{"shlr8",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_9}, arch_sh1_up},
 693
 694 /* 0000000000011011 sleep               */{"sleep",{0},{HEX_0,HEX_0,HEX_1,HEX_B}, arch_sh1_up},
 695
 696 /* 0000nnnn00000010 stc SR,<REG_N>      */{"stc",{A_SR,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_2}, arch_sh1_up},
 697
 698 /* 0000nnnn00010010 stc GBR,<REG_N>     */{"stc",{A_GBR,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_2}, arch_sh1_up},
 699
 700 /* 0000nnnn00100010 stc VBR,<REG_N>     */{"stc",{A_VBR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_2}, arch_sh1_up},
 701
 702 /* 0000nnnn01010010 stc MOD,<REG_N>     */{"stc",{A_MOD,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_2}, arch_sh_dsp_up},
 703
 704 /* 0000nnnn01110010 stc RE,<REG_N>     */{"stc",{A_RE,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up},
 705
 706 /* 0000nnnn01100010 stc RS,<REG_N>     */{"stc",{A_RS,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up},
 707
 708 /* 0000nnnn00110010 stc SSR,<REG_N>     */{"stc",{A_SSR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_2}, arch_sh3_nommu_up},
 709
 710 /* 0000nnnn01000010 stc SPC,<REG_N>     */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_nommu_up},
 711
 712 /* 0000nnnn00111010 stc SGR,<REG_N>     */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nommu_nofpu_up},
 713
 714 /* 0000nnnn11111010 stc DBR,<REG_N>     */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nommu_nofpu_up},
 715
 716 /* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_nommu_up},
 717
 718 /* 0000nnnn01001010 stc TBR,<REG_N> */ {"stc",{A_TBR,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_A}, arch_sh2a_nofpu_up},
 719
 720 /* 0100nnnn00000011 stc.l SR,@-<REG_N>  */{"stc.l",{A_SR,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_3}, arch_sh1_up},
 721
 722 /* 0100nnnn00100011 stc.l VBR,@-<REG_N> */{"stc.l",{A_VBR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_3}, arch_sh1_up},
 723
 724 /* 0100nnnn01010011 stc.l MOD,@-<REG_N> */{"stc.l",{A_MOD,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_3}, arch_sh_dsp_up},
 725
 726 /* 0100nnnn01110011 stc.l RE,@-<REG_N>  */{"stc.l",{A_RE,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_3}, arch_sh_dsp_up},
 727
 728 /* 0100nnnn01100011 stc.l RS,@-<REG_N>  */{"stc.l",{A_RS,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_3}, arch_sh_dsp_up},
 729
 730 /* 0100nnnn00110011 stc.l SSR,@-<REG_N> */{"stc.l",{A_SSR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_3}, arch_sh3_nommu_up},
 731
 732 /* 0100nnnn01000011 stc.l SPC,@-<REG_N> */{"stc.l",{A_SPC,A_DEC_N},{HEX_4,REG_N,HEX_4,HEX_3}, arch_sh3_nommu_up},
 733
 734 /* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up},
 735
 736 /* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nommu_nofpu_up},
 737
 738 /* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nommu_nofpu_up},
 739
 740 /* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_nommu_up},
 741
 742 /* 0000nnnn00001010 sts MACH,<REG_N>    */{"sts",{A_MACH,A_REG_N},{HEX_0,REG_N,HEX_0,HEX_A}, arch_sh1_up},
 743
 744 /* 0000nnnn00011010 sts MACL,<REG_N>    */{"sts",{A_MACL,A_REG_N},{HEX_0,REG_N,HEX_1,HEX_A}, arch_sh1_up},
 745
 746 /* 0000nnnn00101010 sts PR,<REG_N>      */{"sts",{A_PR,A_REG_N},{HEX_0,REG_N,HEX_2,HEX_A}, arch_sh1_up},
 747
 748 /* 0000nnnn01101010 sts DSR,<REG_N>     */{"sts",{A_DSR,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh_dsp_up},
 749
 750 /* 0000nnnn01111010 sts A0,<REG_N>      */{"sts",{A_A0,A_REG_N},{HEX_0,REG_N,HEX_7,HEX_A}, arch_sh_dsp_up},
 751
 752 /* 0000nnnn10001010 sts X0,<REG_N>      */{"sts",{A_X0,A_REG_N},{HEX_0,REG_N,HEX_8,HEX_A}, arch_sh_dsp_up},
 753
 754 /* 0000nnnn10011010 sts X1,<REG_N>      */{"sts",{A_X1,A_REG_N},{HEX_0,REG_N,HEX_9,HEX_A}, arch_sh_dsp_up},
 755
 756 /* 0000nnnn10101010 sts Y0,<REG_N>      */{"sts",{A_Y0,A_REG_N},{HEX_0,REG_N,HEX_A,HEX_A}, arch_sh_dsp_up},
 757
 758 /* 0000nnnn10111010 sts Y1,<REG_N>      */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up},
 759
 760 /* 0000nnnn01011010 sts FPUL,<REG_N>    */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up},
 761
 762 /* 0000nnnn01101010 sts FPSCR,<REG_N>   */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up},
 763
 764 /* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up},
 765
 766 /* 0100nnnn00010010 sts.l MACL,@-<REG_N>*/{"sts.l",{A_MACL,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_2}, arch_sh1_up},
 767
 768 /* 0100nnnn00100010 sts.l PR,@-<REG_N>  */{"sts.l",{A_PR,A_DEC_N},{HEX_4,REG_N,HEX_2,HEX_2}, arch_sh1_up},
 769
 770 /* 0100nnnn01100110 sts.l DSR,@-<REG_N> */{"sts.l",{A_DSR,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh_dsp_up},
 771
 772 /* 0100nnnn01110110 sts.l A0,@-<REG_N>  */{"sts.l",{A_A0,A_DEC_N},{HEX_4,REG_N,HEX_7,HEX_2}, arch_sh_dsp_up},
 773
 774 /* 0100nnnn10000110 sts.l X0,@-<REG_N>  */{"sts.l",{A_X0,A_DEC_N},{HEX_4,REG_N,HEX_8,HEX_2}, arch_sh_dsp_up},
 775
 776 /* 0100nnnn10010110 sts.l X1,@-<REG_N>  */{"sts.l",{A_X1,A_DEC_N},{HEX_4,REG_N,HEX_9,HEX_2}, arch_sh_dsp_up},
 777
 778 /* 0100nnnn10100110 sts.l Y0,@-<REG_N>  */{"sts.l",{A_Y0,A_DEC_N},{HEX_4,REG_N,HEX_A,HEX_2}, arch_sh_dsp_up},
 779
 780 /* 0100nnnn10110110 sts.l Y1,@-<REG_N>  */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up},
 781
 782 /* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up},
 783
 784 /* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up},
 785
 786 /* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up},
 787
 788 /* 0011nnnnmmmm1010 subc <REG_M>,<REG_N>*/{"subc",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_A}, arch_sh1_up},
 789
 790 /* 0011nnnnmmmm1011 subv <REG_M>,<REG_N>*/{"subv",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_B}, arch_sh1_up},
 791
 792 /* 0110nnnnmmmm1000 swap.b <REG_M>,<REG_N>*/{"swap.b",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_8}, arch_sh1_up},
 793
 794 /* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up},
 795
 796 /* 0000000010101011 synco               */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up},
 797
 798 /* 0100nnnn00011011 tas.b @<REG_N>      */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up},
 799
 800 /* 11000011i8*1.... trapa #<imm>        */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up},
 801
 802 /* 11001000i8*1.... tst #<imm>,R0       */{"tst",{A_IMM,A_R0},{HEX_C,HEX_8,IMM0_8}, arch_sh1_up},
 803
 804 /* 0010nnnnmmmm1000 tst <REG_M>,<REG_N> */{"tst",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_8}, arch_sh1_up},
 805
 806 /* 11001100i8*1.... tst.b #<imm>,@(R0,GBR)*/{"tst.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_C,IMM0_8}, arch_sh1_up},
 807
 808 /* 11001010i8*1.... xor #<imm>,R0       */{"xor",{A_IMM,A_R0},{HEX_C,HEX_A,IMM0_8}, arch_sh1_up},
 809
 810 /* 0010nnnnmmmm1010 xor <REG_M>,<REG_N> */{"xor",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_A}, arch_sh1_up},
 811
 812 /* 11001110i8*1.... xor.b #<imm>,@(R0,GBR)*/{"xor.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_E,IMM0_8}, arch_sh1_up},
 813
 814 /* 0010nnnnmmmm1101 xtrct <REG_M>,<REG_N>*/{"xtrct",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_D}, arch_sh1_up},
 815
 816 /* 0000nnnnmmmm0111 mul.l <REG_M>,<REG_N>*/{"mul.l",{ A_REG_M,A_REG_N},{HEX_0,REG_N,REG_M,HEX_7}, arch_sh1_up},
 817
 818 /* 0100nnnn00010000 dt <REG_N>          */{"dt",{A_REG_N},{HEX_4,REG_N,HEX_1,HEX_0}, arch_sh2_up},
 819
 820 /* 0011nnnnmmmm1101 dmuls.l <REG_M>,<REG_N>*/{"dmuls.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_D}, arch_sh2_up},
 821
 822 /* 0011nnnnmmmm0101 dmulu.l <REG_M>,<REG_N>*/{"dmulu.l",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_5}, arch_sh2_up},
 823
 824 /* 0000nnnnmmmm1111 mac.l @<REG_M>+,@<REG_N>+*/{"mac.l",{A_INC_M,A_INC_N},{HEX_0,REG_N,REG_M,HEX_F}, arch_sh2_up},
 825
 826 /* 0000nnnn00100011 braf <REG_N>       */{"braf",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_3}, arch_sh2_up},
 827
 828 /* 0000nnnn00000011 bsrf <REG_N>       */{"bsrf",{A_REG_N},{HEX_0,REG_N,HEX_0,HEX_3}, arch_sh2_up},
 829
 830 /* 111101nnmmmm0000 movs.w @-<REG_N>,<DSP_REG_M> */   {"movs.w",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_0}, arch_sh_dsp_up},
 831
 832 /* 111101nnmmmm0001 movs.w @<REG_N>,<DSP_REG_M> */    {"movs.w",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_4}, arch_sh_dsp_up},
 833
 834 /* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */   {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up},
 835
 836 /* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up},
 837
 838 /* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */   {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up},
 839
 840 /* 111101nnmmmm0101 movs.w <DSP_REG_M>,@<REG_N> */    {"movs.w",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_5}, arch_sh_dsp_up},
 841
 842 /* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */   {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up},
 843
 844 /* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up},
 845
 846 /* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */   {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up},
 847
 848 /* 111101nnmmmm1001 movs.l @<REG_N>,<DSP_REG_M> */    {"movs.l",{A_IND_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_6}, arch_sh_dsp_up},
 849
 850 /* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */   {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up},
 851
 852 /* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up},
 853
 854 /* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */   {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up},
 855
 856 /* 111101nnmmmm1101 movs.l <DSP_REG_M>,@<REG_N> */    {"movs.l",{DSP_REG_M,A_IND_N},{HEX_F,SDT_REG_N,REG_M,HEX_7}, arch_sh_dsp_up},
 857
 858 /* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */   {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up},
 859
 860 /* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up},
 861
 862 /* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up},
 863 /* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up},
 864 /* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */    {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up},
 865 /* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */   {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up},
 866 /* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up},
 867 /* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */    {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up},
 868 /* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */   {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up},
 869 /* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up},
 870
 871 /* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up},
 872 /* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up},
 873 /* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up},
 874 /* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up},
 875 /* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up},
 876 /* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up},
 877
 878 /* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up},
 879 /* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up},
 880 /* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up},
 881 /* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up},
 882 /* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up},
 883 /* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up},
 884
 885 /* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */    {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up},
 886 /* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */   {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up},
 887 /* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up},
 888 /* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */    {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up},
 889 /* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */   {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up},
 890 /* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up},
 891
 892 /* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up},
 893 /* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up},
 894 /* nnmm000011 movy.w @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up},
 895 /* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up},
 896 /* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up},
 897 /* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up},
 898
 899 /* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up},
 900 /* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up},
 901 /* nnmm100011 movy.l @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up},
 902 /* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up},
 903 /* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up},
 904 /* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up},
 905
 906 /* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up},
 907 /* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 908 {"psubc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_0}, arch_sh_dsp_up},
 909 /* 10110000xxyynnnn paddc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 910 {"paddc",{DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_0}, arch_sh_dsp_up},
 911 /* 10000100xxyynnnn pcmp <DSP_REG_X>,<DSP_REG_Y> */
 912 {"pcmp", {DSP_REG_X,DSP_REG_Y},{PPI,PPI3,HEX_8,HEX_4}, arch_sh_dsp_up},
 913 /* 10100100xxyynnnn pwsb <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 914 {"pwsb", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_4}, arch_sh_dsp_up},
 915 /* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 916 {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up},
 917 /* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */
 918 {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up},
 919 /* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */
 920 {"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up},
 921 /* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
 922 {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up},
 923 /* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */
 924 {"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up},
 925 /* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */
 926 {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up},
 927 /* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */
 928 {"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up},
 929 /* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
 930 {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up},
 931 /* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */
 932 {"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up},
 933
 934 {"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up},
 935 {"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up},
 936
 937 /* 10000001xxyynnnn pshl <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 938 {"pshl", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_1}, arch_sh_dsp_up},
 939 /* 00000iiiiiiinnnn pshl #<imm>,<DSP_REG_N> */ {"pshl",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_0}, arch_sh_dsp_up},
 940 /* 10010001xxyynnnn psha <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 941 {"psha", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_1}, arch_sh_dsp_up},
 942 /* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up},
 943 /* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 944 {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up},
 945 /* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */
 946 {"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up},
 947 /* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 948 {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up},
 949 /* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 950 {"pand", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_5}, arch_sh_dsp_up},
 951 /* 10100101xxyynnnn pxor <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 952 {"pxor", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_5}, arch_sh_dsp_up},
 953 /* 10110101xxyynnnn por  <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */
 954 {"por",  {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_5}, arch_sh_dsp_up},
 955 /* 10001001xxyynnnn pdec <DSP_REG_X>,<DSP_REG_N> */
 956 {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up},
 957 /* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */
 958 {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up},
 959 /* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */
 960 {"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up},
 961 /* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */
 962 {"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up},
 963 /* 10001101xxyynnnn pclr <DSP_REG_N> */
 964 {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up},
 965 /* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */
 966 {"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up},
 967 /* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */
 968 {"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up},
 969 /* 11001001xxyynnnn pneg  <DSP_REG_X>,<DSP_REG_N> */
 970 {"pneg",  {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up},
 971 /* 11101001xxyynnnn pneg  <DSP_REG_Y>,<DSP_REG_N> */
 972 {"pneg",  {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_E,HEX_9}, arch_sh_dsp_up},
 973 /* 11011001xxyynnnn pcopy <DSP_REG_X>,<DSP_REG_N> */
 974 {"pcopy", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_9}, arch_sh_dsp_up},
 975 /* 11111001xxyynnnn pcopy <DSP_REG_Y>,<DSP_REG_N> */
 976 {"pcopy", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_F,HEX_9}, arch_sh_dsp_up},
 977 /* 11001101xxyynnnn psts MACH,<DSP_REG_N> */
 978 {"psts", {A_MACH,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_D}, arch_sh_dsp_up},
 979 /* 11011101xxyynnnn psts MACL,<DSP_REG_N> */
 980 {"psts", {A_MACL,DSP_REG_N},{PPI,PPIC,HEX_D,HEX_D}, arch_sh_dsp_up},
 981 /* 11101101xxyynnnn plds <DSP_REG_N>,MACH */
 982 {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up},
 983 /* 11111101xxyynnnn plds <DSP_REG_N>,MACL */
 984 {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up},
 985 /* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */
 986 {"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up},
 987 /* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */
 988 {"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up},
 989
 990 /* 1111nnnn01011101 fabs <F_REG_N>     */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up},
 991 /* 1111nnn001011101 fabs <D_REG_N>     */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up | arch_sh2a_up},
 992
 993 /* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up},
 994 /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up | arch_sh2a_up},
 995
 996 /* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up},
 997 /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up | arch_sh2a_up},
 998
 999 /* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up},
1000 /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up | arch_sh2a_up},
1001
1002 /* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up | arch_sh2a_up},
1003
1004 /* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up | arch_sh2a_up},
1005
1006 /* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up},
1007 /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up | arch_sh2a_up},
1008
1009 /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up},
1010
1011 /* 1111nnnn10001101 fldi0 <F_REG_N>    */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up},
1012
1013 /* 1111nnnn10011101 fldi1 <F_REG_N>    */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up},
1014
1015 /* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up},
1016
1017 /* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up},
1018 /* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up | arch_sh2a_up},
1019
1020 /* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up},
1021
1022 /* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up},
1023 /* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up | arch_sh2a_up},
1024
1025 /* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
1026 /* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
1027
1028 /* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
1029 /* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
1030
1031 /* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
1032 /* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
1033
1034 /* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
1035 /* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
1036
1037 /* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
1038 /* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
1039
1040 /* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
1041 /* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
1042
1043 /* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up | arch_sh2a_up},
1044
1045 /* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up | arch_sh2a_up},
1046
1047 /* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up | arch_sh2a_up},
1048
1049 /* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up | arch_sh2a_up},
1050
1051 /* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up | arch_sh2a_up},
1052
1053 /* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up | arch_sh2a_up},
1054 /* 0011nnnnmmmm0001 0011dddddddddddd fmov.d <F_REG_M>,@(<DISP12>,<REG_N>) */
1055 {"fmov.d",{DX_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY8}, arch_sh2a_up | arch_op32},
1056 /* 0011nnnnmmmm0001 0111dddddddddddd fmov.d @(<DISP12>,<REG_M>),F_REG_N */
1057 {"fmov.d",{A_DISP_REG_M,DX_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY8}, arch_sh2a_up | arch_op32},
1058
1059 /* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up},
1060
1061 /* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up},
1062
1063 /* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up},
1064
1065 /* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up},
1066
1067 /* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up},
1068
1069 /* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up},
1070 /* 0011nnnnmmmm0001 0011dddddddddddd fmov.s <F_REG_M>,@(<DISP12>,<REG_N>) */
1071 {"fmov.s",{F_REG_M,A_DISP_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_3,DISP1_12BY4}, arch_sh2a_up | arch_op32},
1072 /* 0011nnnnmmmm0001 0111dddddddddddd fmov.s @(<DISP12>,<REG_M>),F_REG_N */
1073 {"fmov.s",{A_DISP_REG_M,F_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_7,DISP0_12BY4}, arch_sh2a_up | arch_op32},
1074
1075 /* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up},
1076 /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up | arch_sh2a_up},
1077
1078 /* 1111nnnn01001101 fneg <F_REG_N>     */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up},
1079 /* 1111nnn001001101 fneg <D_REG_N>     */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up | arch_sh2a_up},
1080
1081 /* 1111011111111101 fpchg               */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up},
1082
1083 /* 1111101111111101 frchg               */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up},
1084
1085 /* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up},
1086
1087 /* 1111001111111101 fschg               */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up | arch_sh2a_up},
1088
1089 /* 1111nnnn01101101 fsqrt <F_REG_N>    */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up | arch_sh2a_up},
1090 /* 1111nnn001101101 fsqrt <D_REG_N>    */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up | arch_sh2a_up},
1091
1092 /* 1111nnnn01111101 fsrra <F_REG_N>    */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up},
1093
1094 /* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up},
1095
1096 /* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up},
1097 /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up | arch_sh2a_up},
1098
1099 /* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up},
1100 /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up | arch_sh2a_up},
1101
1102 /* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up},
1103
1104   /* 10000110nnnn0iii bclr #<imm>, <REG_N> */  {"bclr",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3c}, arch_sh2a_nofpu_up},
1105   /* 0011nnnn0iii1001 0000dddddddddddd bclr.b #<imm>,@(<DISP12>,<REG_N>) */
1106 {"bclr.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_0,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1107   /* 10000111nnnn1iii bld #<imm>, <REG_N> */   {"bld",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3s}, arch_sh2a_nofpu_up},
1108   /* 0011nnnn0iii1001 0011dddddddddddd bld.b #<imm>,@(<DISP12>,<REG_N>) */
1109 {"bld.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_3,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1110   /* 10000110nnnn1iii bset #<imm>, <REG_N> */  {"bset",{A_IMM, A_REG_N},{HEX_8,HEX_6,REG_N,IMM0_3s}, arch_sh2a_nofpu_up},
1111   /* 0011nnnn0iii1001 0001dddddddddddd bset.b #<imm>,@(<DISP12>,<REG_N>) */
1112 {"bset.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_1,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1113   /* 10000111nnnn0iii bst #<imm>, <REG_N> */   {"bst",{A_IMM, A_REG_N},{HEX_8,HEX_7,REG_N,IMM0_3c}, arch_sh2a_nofpu_up},
1114   /* 0011nnnn0iii1001 0010dddddddddddd bst.b #<imm>,@(<DISP12>,<REG_N>) */
1115 {"bst.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_2,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1116   /* 0100nnnn10010001 clips.b <REG_N> */       {"clips.b",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_1}, arch_sh2a_nofpu_up},
1117   /* 0100nnnn10010101 clips.w <REG_N> */       {"clips.w",{A_REG_N},{HEX_4,REG_N,HEX_9,HEX_5}, arch_sh2a_nofpu_up},
1118   /* 0100nnnn10000001 clipu.b <REG_N> */       {"clipu.b",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_1}, arch_sh2a_nofpu_up},
1119   /* 0100nnnn10000101 clipu.w <REG_N> */       {"clipu.w",{A_REG_N},{HEX_4,REG_N,HEX_8,HEX_5}, arch_sh2a_nofpu_up},
1120   /* 0100nnnn10010100 divs R0,<REG_N> */       {"divs",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_9,HEX_4}, arch_sh2a_nofpu_up},
1121   /* 0100nnnn10000100 divu R0,<REG_N> */       {"divu",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_4}, arch_sh2a_nofpu_up},
1122   /* 0100mmmm01001011 jsr/n @<REG_M>  */       {"jsr/n",{A_IND_M},{HEX_4,REG_M,HEX_4,HEX_B}, arch_sh2a_nofpu_up},
1123   /* 10000011dddddddd jsr/n @@(<disp>,TBR) */  {"jsr/n",{A_DISP2_TBR},{HEX_8,HEX_3,IMM0_8BY4}, arch_sh2a_nofpu_up},
1124   /* 0100mmmm11100101 ldbank @<REG_M>,R0 */    {"ldbank",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_5}, arch_sh2a_nofpu_up},
1125   /* 0100mmmm11110001 movml.l <REG_M>,@-R15 */ {"movml.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_1}, arch_sh2a_nofpu_up},
1126   /* 0100mmmm11110101 movml.l @R15+,<REG_M> */ {"movml.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_5}, arch_sh2a_nofpu_up},
1127   /* 0100mmmm11110000 movml.l <REG_M>,@-R15 */ {"movmu.l",{A_REG_M,A_DEC_R15},{HEX_4,REG_M,HEX_F,HEX_0}, arch_sh2a_nofpu_up},
1128   /* 0100mmmm11110100 movml.l @R15+,<REG_M> */ {"movmu.l",{A_INC_R15,A_REG_M},{HEX_4,REG_M,HEX_F,HEX_4}, arch_sh2a_nofpu_up},
1129   /* 0000nnnn00111001 movrt <REG_N> */         {"movrt",{A_REG_N},{HEX_0,REG_N,HEX_3,HEX_9}, arch_sh2a_nofpu_up},
1130   /* 0100nnnn10000000 mulr R0,<REG_N> */       {"mulr",{A_R0,A_REG_N},{HEX_4,REG_N,HEX_8,HEX_0}, arch_sh2a_nofpu_up},
1131   /* 0000000001101000 nott */                  {"nott",{A_END},{HEX_0,HEX_0,HEX_6,HEX_8}, arch_sh2a_nofpu_up},
1132   /* 0000000001011011 resbank */               {"resbank",{A_END},{HEX_0,HEX_0,HEX_5,HEX_B}, arch_sh2a_nofpu_up},
1133   /* 0000000001101011 rts/n */                 {"rts/n",{A_END},{HEX_0,HEX_0,HEX_6,HEX_B}, arch_sh2a_nofpu_up},
1134   /* 0000mmmm01111011 rtv/n <REG_M>*/          {"rtv/n",{A_REG_M},{HEX_0,REG_M,HEX_7,HEX_B}, arch_sh2a_nofpu_up},
1135   /* 0100nnnn11100001 stbank R0,@<REG_N>*/     {"stbank",{A_R0,A_IND_N},{HEX_4,REG_N,HEX_E,HEX_1}, arch_sh2a_nofpu_up},
1136
1137 /* 0011nnnn0iii1001 0100dddddddddddd band.b #<imm>,@(<DISP12>,<REG_N>) */
1138 {"band.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_4,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1139 /* 0011nnnn0iii1001 1100dddddddddddd bandnot.b #<imm>,@(<DISP12>,<REG_N>) */
1140 {"bandnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_C,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1141 /* 0011nnnn0iii1001 1011dddddddddddd bldnot.b #<imm>,@(<DISP12>,<REG_N>) */
1142 {"bldnot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_B,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1143 /* 0011nnnn0iii1001 0101dddddddddddd bor.b #<imm>,@(<DISP12>,<REG_N>) */
1144 {"bor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_5,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1145 /* 0011nnnn0iii1001 1101dddddddddddd bornot.b #<imm>,@(<DISP12>,<REG_N>) */
1146 {"bornot.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_D,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1147 /* 0011nnnn0iii1001 0110dddddddddddd bxor.b #<imm>,@(<DISP12>,<REG_N>) */
1148 {"bxor.b",{A_IMM,A_DISP_REG_N},{HEX_3,REG_N,IMM0_3Uc,HEX_9,HEX_6,DISP1_12}, arch_sh2a_nofpu_up | arch_op32},
1149 /* 0000nnnniiii0000 iiiiiiiiiiiiiiii movi20 #<imm>,<REG_N> */
1150 {"movi20",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_0,IMM0_20}, arch_sh2a_nofpu_up | arch_op32},
1151 /* 0000nnnniiii0001 iiiiiiiiiiiiiiii movi20s #<imm>,<REG_N> */
1152 {"movi20s",{A_IMM,A_REG_N},{HEX_0,REG_N,IMM0_20_4,HEX_1,IMM0_20BY8}, arch_sh2a_nofpu_up | arch_op32},
1153 /* 0011nnnnmmmm0001 1000dddddddddddd movu.b @(<DISP12>,<REG_M>),<REG_N> */
1154 {"movu.b",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_8,DISP0_12}, arch_sh2a_nofpu_up | arch_op32},
1155 /* 0011nnnnmmmm0001 1001dddddddddddd movu.w @(<DISP12>,<REG_M>),<REG_N> */
1156 {"movu.w",{A_DISP_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_1,HEX_9,DISP0_12BY2}, arch_sh2a_nofpu_up | arch_op32},
1157
1158 { 0, {0}, {0}, 0 }
1159 };
1160
1161 #endif
1162
1163 #ifdef ARCH_all
1164 #define INCLUDE_SHMEDIA
1165 #endif
1166
1167 static void print_movxy
1168   PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *));
1169 static void print_insn_ddt PARAMS ((int, struct disassemble_info *));
1170 static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *));
1171 static void print_insn_ppi PARAMS ((int, struct disassemble_info *));
1172
1173 static void
1174 print_movxy (op, rn, rm, fprintf_fn, stream)
1175      const sh_opcode_info *op;
1176      int rn, rm;
1177      fprintf_ftype fprintf_fn;
1178      void *stream;
1179 {
1180   int n;
1181
1182   fprintf_fn (stream, "%s\t", op->name);
1183   for (n = 0; n < 2; n++)
1184     {
1185       switch (op->arg[n])
1186         {
1187         case A_IND_N:
1188         case AX_IND_N:
1189         case AXY_IND_N:
1190         case AY_IND_N:
1191         case AYX_IND_N:
1192           fprintf_fn (stream, "@r%d", rn);
1193           break;
1194         case A_INC_N:
1195         case AX_INC_N:
1196         case AXY_INC_N:
1197         case AY_INC_N:
1198         case AYX_INC_N:
1199           fprintf_fn (stream, "@r%d+", rn);
1200           break;
1201         case AX_PMOD_N:
1202         case AXY_PMOD_N:
1203           fprintf_fn (stream, "@r%d+r8", rn);
1204           break;
1205         case AY_PMOD_N:
1206         case AYX_PMOD_N:
1207           fprintf_fn (stream, "@r%d+r9", rn);
1208           break;
1209         case DSP_REG_A_M:
1210           fprintf_fn (stream, "a%c", '0' + rm);
1211           break;
1212         case DSP_REG_X:
1213           fprintf_fn (stream, "x%c", '0' + rm);
1214           break;
1215         case DSP_REG_Y:
1216           fprintf_fn (stream, "y%c", '0' + rm);
1217           break;
1218         case DSP_REG_AX:
1219           fprintf_fn (stream, "%c%c",
1220                       (rm & 1) ? 'x' : 'a',
1221                       (rm & 2) ? '1' : '0');
1222           break;
1223         case DSP_REG_XY:
1224           fprintf_fn (stream, "%c%c",
1225                       (rm & 1) ? 'y' : 'x',
1226                       (rm & 2) ? '1' : '0');
1227           break;
1228         case DSP_REG_AY:
1229           fprintf_fn (stream, "%c%c",
1230                       (rm & 2) ? 'y' : 'a',
1231                       (rm & 1) ? '1' : '0');
1232           break;
1233         case DSP_REG_YX:
1234           fprintf_fn (stream, "%c%c",
1235                       (rm & 2) ? 'x' : 'y',
1236                       (rm & 1) ? '1' : '0');
1237           break;
1238         default:
1239           abort ();
1240         }
1241       if (n == 0)
1242         fprintf_fn (stream, ",");
1243     }
1244 }
1245
1246 /* Print a double data transfer insn.  INSN is just the lower three
1247    nibbles of the insn, i.e. field a and the bit that indicates if
1248    a parallel processing insn follows.
1249    Return nonzero if a field b of a parallel processing insns follows.  */
1250
1251 static void
1252 print_insn_ddt (insn, info)
1253      int insn;
1254      struct disassemble_info *info;
1255 {
1256   fprintf_ftype fprintf_fn = info->fprintf_func;
1257   void *stream = info->stream;
1258
1259   /* If this is just a nop, make sure to emit something.  */
1260   if (insn == 0x000)
1261     fprintf_fn (stream, "nopx\tnopy");
1262
1263   /* If a parallel processing insn was printed before,
1264      and we got a non-nop, emit a tab.  */
1265   if ((insn & 0x800) && (insn & 0x3ff))
1266     fprintf_fn (stream, "\t");
1267
1268   /* Check if either the x or y part is invalid.  */
1269   if (((insn & 0xc) == 0 && (insn & 0x2a0))
1270       || ((insn & 3) == 0 && (insn & 0x150)))
1271     if (info->mach != bfd_mach_sh_dsp
1272         && info->mach != bfd_mach_sh3_dsp)
1273       {
1274         static const sh_opcode_info *first_movx, *first_movy;
1275         const sh_opcode_info *op;
1276         int is_movy;
1277
1278         if (! first_movx)
1279           {
1280             for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;)
1281               first_movx++;
1282             for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;)
1283               first_movy++;
1284           }
1285
1286         is_movy = ((insn & 3) != 0);
1287
1288         if (is_movy)
1289           op = first_movy;
1290         else
1291           op = first_movx;
1292
1293         while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3)
1294                || op->nibbles[3] != (unsigned) (insn & 0xf))
1295           op++;
1296
1297         print_movxy (op,
1298                      (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0)
1299                       + 2 * is_movy
1300                       + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)),
1301                      (insn >> 6) & 3,
1302                      fprintf_fn, stream);
1303       }
1304     else
1305       fprintf_fn (stream, ".word 0x%x", insn);
1306   else
1307     {
1308       static const sh_opcode_info *first_movx, *first_movy;
1309       const sh_opcode_info *opx, *opy;
1310       unsigned int insn_x, insn_y;
1311
1312       if (! first_movx)
1313         {
1314           for (first_movx = sh_table; first_movx->nibbles[1] != MOVX;)
1315             first_movx++;
1316           for (first_movy = first_movx; first_movy->nibbles[1] != MOVY;)
1317             first_movy++;
1318         }
1319       insn_x = (insn >> 2) & 0xb;
1320       if (insn_x)
1321         {
1322           for (opx = first_movx; opx->nibbles[2] != insn_x;)
1323             opx++;
1324           print_movxy (opx, ((insn >> 9) & 1) + 4, (insn >> 7) & 1,
1325                        fprintf_fn, stream);
1326         }
1327       insn_y = (insn & 3) | ((insn >> 1) & 8);
1328       if (insn_y)
1329         {
1330           if (insn_x)
1331             fprintf_fn (stream, "\t");
1332           for (opy = first_movy; opy->nibbles[2] != insn_y;)
1333             opy++;
1334           print_movxy (opy, ((insn >> 8) & 1) + 6, (insn >> 6) & 1,
1335                        fprintf_fn, stream);
1336         }
1337     }
1338 }
1339
1340 static void
1341 print_dsp_reg (rm, fprintf_fn, stream)
1342      int rm;
1343      fprintf_ftype fprintf_fn;
1344      void *stream;
1345 {
1346   switch (rm)
1347     {
1348     case A_A1_NUM:
1349       fprintf_fn (stream, "a1");
1350       break;
1351     case A_A0_NUM:
1352       fprintf_fn (stream, "a0");
1353       break;
1354     case A_X0_NUM:
1355       fprintf_fn (stream, "x0");
1356       break;
1357     case A_X1_NUM:
1358       fprintf_fn (stream, "x1");
1359       break;
1360     case A_Y0_NUM:
1361       fprintf_fn (stream, "y0");
1362       break;
1363     case A_Y1_NUM:
1364       fprintf_fn (stream, "y1");
1365       break;
1366     case A_M0_NUM:
1367       fprintf_fn (stream, "m0");
1368       break;
1369     case A_A1G_NUM:
1370       fprintf_fn (stream, "a1g");
1371       break;
1372     case A_M1_NUM:
1373       fprintf_fn (stream, "m1");
1374       break;
1375     case A_A0G_NUM:
1376       fprintf_fn (stream, "a0g");
1377       break;
1378     default:
1379       fprintf_fn (stream, "0x%x", rm);
1380       break;
1381     }
1382 }
1383
1384 static void
1385 print_insn_ppi (field_b, info)
1386      int field_b;
1387      struct disassemble_info *info;
1388 {
1389   static const char *sx_tab[] = { "x0", "x1", "a0", "a1" };
1390   static const char *sy_tab[] = { "y0", "y1", "m0", "m1" };
1391   fprintf_ftype fprintf_fn = info->fprintf_func;
1392   void *stream = info->stream;
1393   unsigned int nib1, nib2, nib3;
1394   unsigned int altnib1, nib4;
1395   const char *dc = NULL;
1396   const sh_opcode_info *op;
1397
1398   if ((field_b & 0xe800) == 0)
1399     {
1400       fprintf_fn (stream, "psh%c\t#%d,",
1401                   field_b & 0x1000 ? 'a' : 'l',
1402                   (field_b >> 4) & 127);
1403       print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
1404       return;
1405     }
1406   if ((field_b & 0xc000) == 0x4000 && (field_b & 0x3000) != 0x1000)
1407     {
1408       static const char *du_tab[] = { "x0", "y0", "a0", "a1" };
1409       static const char *se_tab[] = { "x0", "x1", "y0", "a1" };
1410       static const char *sf_tab[] = { "y0", "y1", "x0", "a1" };
1411       static const char *sg_tab[] = { "m0", "m1", "a0", "a1" };
1412
1413       if (field_b & 0x2000)
1414         {
1415           fprintf_fn (stream, "p%s %s,%s,%s\t",
1416                       (field_b & 0x1000) ? "add" : "sub",
1417                       sx_tab[(field_b >> 6) & 3],
1418                       sy_tab[(field_b >> 4) & 3],
1419                       du_tab[(field_b >> 0) & 3]);
1420         }
1421       else if ((field_b & 0xf0) == 0x10
1422                && info->mach != bfd_mach_sh_dsp
1423                && info->mach != bfd_mach_sh3_dsp)
1424         {
1425           fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]);
1426         }
1427       else if ((field_b & 0xf3) != 0)
1428         {
1429           fprintf_fn (stream, ".word 0x%x\t", field_b);
1430         }
1431       fprintf_fn (stream, "pmuls%c%s,%s,%s",
1432                   field_b & 0x2000 ? ' ' : '\t',
1433                   se_tab[(field_b >> 10) & 3],
1434                   sf_tab[(field_b >>  8) & 3],
1435                   sg_tab[(field_b >>  2) & 3]);
1436       return;
1437     }
1438
1439   nib1 = PPIC;
1440   nib2 = field_b >> 12 & 0xf;
1441   nib3 = field_b >> 8 & 0xf;
1442   nib4 = field_b >> 4 & 0xf;
1443   switch (nib3 & 0x3)
1444     {
1445     case 0:
1446       dc = "";
1447       nib1 = PPI3;
1448       break;
1449     case 1:
1450       dc = "";
1451       break;
1452     case 2:
1453       dc = "dct ";
1454       nib3 -= 1;
1455       break;
1456     case 3:
1457       dc = "dcf ";
1458       nib3 -= 2;
1459       break;
1460     }
1461   if (nib1 == PPI3)
1462     altnib1 = PPI3NC;
1463   else
1464     altnib1 = nib1;
1465   for (op = sh_table; op->name; op++)
1466     {
1467       if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1)
1468           && op->nibbles[2] == nib2
1469           && op->nibbles[3] == nib3)
1470         {
1471           int n;
1472
1473           switch (op->nibbles[4])
1474             {
1475             case HEX_0:
1476               break;
1477             case HEX_XX00:
1478               if ((nib4 & 3) != 0)
1479                 continue;
1480               break;
1481             case HEX_1:
1482               if ((nib4 & 3) != 1)
1483                 continue;
1484               break;
1485             case HEX_00YY:
1486               if ((nib4 & 0xc) != 0)
1487                 continue;
1488               break;
1489             case HEX_4:
1490               if ((nib4 & 0xc) != 4)
1491                 continue;
1492               break;
1493             default:
1494               abort ();
1495             }
1496           fprintf_fn (stream, "%s%s\t", dc, op->name);
1497           for (n = 0; n < 3 && op->arg[n] != A_END; n++)
1498             {
1499               if (n && op->arg[1] != A_END)
1500                 fprintf_fn (stream, ",");
1501               switch (op->arg[n])
1502                 {
1503                 case DSP_REG_N:
1504                   print_dsp_reg (field_b & 0xf, fprintf_fn, stream);
1505                   break;
1506                 case DSP_REG_X:
1507                   fprintf_fn (stream, sx_tab[(field_b >> 6) & 3]);
1508                   break;
1509                 case DSP_REG_Y:
1510                   fprintf_fn (stream, sy_tab[(field_b >> 4) & 3]);
1511                   break;
1512                 case A_MACH:
1513                   fprintf_fn (stream, "mach");
1514                   break;
1515                 case A_MACL:
1516                   fprintf_fn (stream, "macl");
1517                   break;
1518                 default:
1519                   abort ();
1520                 }
1521             }
1522           return;
1523         }
1524     }
1525   /* Not found.  */
1526   fprintf_fn (stream, ".word 0x%x", field_b);
1527 }
1528
1529 /* FIXME mvs: movx insns print as ".word 0x%03x", insn & 0xfff
1530    (ie. the upper nibble is missing).  */
1531 int
1532 print_insn_sh (memaddr, info)
1533      bfd_vma memaddr;
1534      struct disassemble_info *info;
1535 {
1536   fprintf_ftype fprintf_fn = info->fprintf_func;
1537   void *stream = info->stream;
1538   unsigned char insn[4];
1539   unsigned char nibs[8];
1540   int status;
1541   bfd_vma relmask = ~(bfd_vma) 0;
1542   const sh_opcode_info *op;
1543   unsigned int target_arch;
1544   int allow_op32;
1545
1546   switch (info->mach)
1547     {
1548     case bfd_mach_sh:
1549       target_arch = arch_sh1;
1550       break;
1551     case bfd_mach_sh4:
1552       target_arch = arch_sh4;
1553       break;
1554     case bfd_mach_sh5:
1555 #ifdef INCLUDE_SHMEDIA
1556       status = print_insn_sh64 (memaddr, info);
1557       if (status != -2)
1558         return status;
1559 #endif
1560       /* When we get here for sh64, it's because we want to disassemble
1561          SHcompact, i.e. arch_sh4.  */
1562       target_arch = arch_sh4;
1563       break;
1564     default:
1565       fprintf (stderr, "sh architecture not supported\n");
1566       return -1;
1567     }
1568
1569   status = info->read_memory_func (memaddr, insn, 2, info);
1570
1571   if (status != 0)
1572     {
1573       info->memory_error_func (status, memaddr, info);
1574       return -1;
1575     }
1576
1577   if (info->endian == BFD_ENDIAN_LITTLE)
1578     {
1579       nibs[0] = (insn[1] >> 4) & 0xf;
1580       nibs[1] = insn[1] & 0xf;
1581
1582       nibs[2] = (insn[0] >> 4) & 0xf;
1583       nibs[3] = insn[0] & 0xf;
1584     }
1585   else
1586     {
1587       nibs[0] = (insn[0] >> 4) & 0xf;
1588       nibs[1] = insn[0] & 0xf;
1589
1590       nibs[2] = (insn[1] >> 4) & 0xf;
1591       nibs[3] = insn[1] & 0xf;
1592     }
1593   status = info->read_memory_func (memaddr + 2, insn + 2, 2, info);
1594   if (status != 0)
1595     allow_op32 = 0;
1596   else
1597     {
1598       allow_op32 = 1;
1599
1600       if (info->endian == BFD_ENDIAN_LITTLE)
1601         {
1602           nibs[4] = (insn[3] >> 4) & 0xf;
1603           nibs[5] = insn[3] & 0xf;
1604
1605           nibs[6] = (insn[2] >> 4) & 0xf;
1606           nibs[7] = insn[2] & 0xf;
1607         }
1608       else
1609         {
1610           nibs[4] = (insn[2] >> 4) & 0xf;
1611           nibs[5] = insn[2] & 0xf;
1612
1613           nibs[6] = (insn[3] >> 4) & 0xf;
1614           nibs[7] = insn[3] & 0xf;
1615         }
1616     }
1617
1618   if (nibs[0] == 0xf && (nibs[1] & 4) == 0
1619       && SH_MERGE_ARCH_SET_VALID (target_arch, arch_sh_dsp_up))
1620     {
1621       if (nibs[1] & 8)
1622         {
1623           int field_b;
1624
1625           status = info->read_memory_func (memaddr + 2, insn, 2, info);
1626
1627           if (status != 0)
1628             {
1629               info->memory_error_func (status, memaddr + 2, info);
1630               return -1;
1631             }
1632
1633           if (info->endian == BFD_ENDIAN_LITTLE)
1634             field_b = insn[1] << 8 | insn[0];
1635           else
1636             field_b = insn[0] << 8 | insn[1];
1637
1638           print_insn_ppi (field_b, info);
1639           print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
1640           return 4;
1641         }
1642       print_insn_ddt ((nibs[1] << 8) | (nibs[2] << 4) | nibs[3], info);
1643       return 2;
1644     }
1645   for (op = sh_table; op->name; op++)
1646     {
1647       int n;
1648       int imm = 0;
1649       int rn = 0;
1650       int rm = 0;
1651       int rb = 0;
1652       int disp_pc;
1653       bfd_vma disp_pc_addr = 0;
1654       int disp = 0;
1655       int has_disp = 0;
1656       int max_n = SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 8 : 4;
1657
1658       if (!allow_op32
1659           && SH_MERGE_ARCH_SET (op->arch, arch_op32))
1660         goto fail;
1661
1662       if (!SH_MERGE_ARCH_SET_VALID (op->arch, target_arch))
1663         goto fail;
1664       for (n = 0; n < max_n; n++)
1665         {
1666           int i = op->nibbles[n];
1667
1668           if (i < 16)
1669             {
1670               if (nibs[n] == i)
1671                 continue;
1672               goto fail;
1673             }
1674           switch (i)
1675             {
1676             case BRANCH_8:
1677               imm = (nibs[2] << 4) | (nibs[3]);
1678               if (imm & 0x80)
1679                 imm |= ~0xff;
1680               imm = ((char) imm) * 2 + 4;
1681               goto ok;
1682             case BRANCH_12:
1683               imm = ((nibs[1]) << 8) | (nibs[2] << 4) | (nibs[3]);
1684               if (imm & 0x800)
1685                 imm |= ~0xfff;
1686               imm = imm * 2 + 4;
1687               goto ok;
1688             case IMM0_3c:
1689               if (nibs[3] & 0x8)
1690                 goto fail;
1691               imm = nibs[3] & 0x7;
1692               break;
1693             case IMM0_3s:
1694               if (!(nibs[3] & 0x8))
1695                 goto fail;
1696               imm = nibs[3] & 0x7;
1697               break;
1698             case IMM0_3Uc:
1699               if (nibs[2] & 0x8)
1700                 goto fail;
1701               imm = nibs[2] & 0x7;
1702               break;
1703             case IMM0_3Us:
1704               if (!(nibs[2] & 0x8))
1705                 goto fail;
1706               imm = nibs[2] & 0x7;
1707               break;
1708             case DISP0_12:
1709             case DISP1_12:
1710               disp = (nibs[5] << 8) | (nibs[6] << 4) | nibs[7];
1711               has_disp = 1;
1712               goto ok;
1713             case DISP0_12BY2:
1714             case DISP1_12BY2:
1715               disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 1;
1716               relmask = ~(bfd_vma) 1;
1717               has_disp = 1;
1718               goto ok;
1719             case DISP0_12BY4:
1720             case DISP1_12BY4:
1721               disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 2;
1722               relmask = ~(bfd_vma) 3;
1723               has_disp = 1;
1724               goto ok;
1725             case DISP0_12BY8:
1726             case DISP1_12BY8:
1727               disp = ((nibs[5] << 8) | (nibs[6] << 4) | nibs[7]) << 3;
1728               relmask = ~(bfd_vma) 7;
1729               has_disp = 1;
1730               goto ok;
1731             case IMM0_20_4:
1732               break;
1733             case IMM0_20:
1734               imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
1735                      | (nibs[6] << 4) | nibs[7]);
1736               if (imm & 0x80000)
1737                 imm -= 0x100000;
1738               goto ok;
1739             case IMM0_20BY8:
1740               imm = ((nibs[2] << 16) | (nibs[4] << 12) | (nibs[5] << 8)
1741                      | (nibs[6] << 4) | nibs[7]);
1742               imm <<= 8;
1743               if (imm & 0x8000000)
1744                 imm -= 0x10000000;
1745               goto ok;
1746             case IMM0_4:
1747             case IMM1_4:
1748               imm = nibs[3];
1749               goto ok;
1750             case IMM0_4BY2:
1751             case IMM1_4BY2:
1752               imm = nibs[3] << 1;
1753               goto ok;
1754             case IMM0_4BY4:
1755             case IMM1_4BY4:
1756               imm = nibs[3] << 2;
1757               goto ok;
1758             case IMM0_8:
1759             case IMM1_8:
1760               imm = (nibs[2] << 4) | nibs[3];
1761               disp = imm;
1762               has_disp = 1;
1763               if (imm & 0x80)
1764                 imm -= 0x100;
1765               goto ok;
1766             case PCRELIMM_8BY2:
1767               imm = ((nibs[2] << 4) | nibs[3]) << 1;
1768               relmask = ~(bfd_vma) 1;
1769               goto ok;
1770             case PCRELIMM_8BY4:
1771               imm = ((nibs[2] << 4) | nibs[3]) << 2;
1772               relmask = ~(bfd_vma) 3;
1773               goto ok;
1774             case IMM0_8BY2:
1775             case IMM1_8BY2:
1776               imm = ((nibs[2] << 4) | nibs[3]) << 1;
1777               goto ok;
1778             case IMM0_8BY4:
1779             case IMM1_8BY4:
1780               imm = ((nibs[2] << 4) | nibs[3]) << 2;
1781               goto ok;
1782             case REG_N_D:
1783               if ((nibs[n] & 1) != 0)
1784                 goto fail;
1785               /* fall through */
1786             case REG_N:
1787               rn = nibs[n];
1788               break;
1789             case REG_M:
1790               rm = nibs[n];
1791               break;
1792             case REG_N_B01:
1793               if ((nibs[n] & 0x3) != 1 /* binary 01 */)
1794                 goto fail;
1795               rn = (nibs[n] & 0xc) >> 2;
1796               break;
1797             case REG_NM:
1798               rn = (nibs[n] & 0xc) >> 2;
1799               rm = (nibs[n] & 0x3);
1800               break;
1801             case REG_B:
1802               rb = nibs[n] & 0x07;
1803               break;
1804             case SDT_REG_N:
1805               /* sh-dsp: single data transfer.  */
1806               rn = nibs[n];
1807               if ((rn & 0xc) != 4)
1808                 goto fail;
1809               rn = rn & 0x3;
1810               rn |= (!(rn & 2)) << 2;
1811               break;
1812             case PPI:
1813             case REPEAT:
1814               goto fail;
1815             default:
1816               abort ();
1817             }
1818         }
1819
1820     ok:
1821       /* sh2a has D_REG but not X_REG.  We don't know the pattern
1822          doesn't match unless we check the output args to see if they
1823          make sense.  */
1824       if (target_arch == arch_sh2a
1825           && ((op->arg[0] == DX_REG_M && (rm & 1) != 0)
1826               || (op->arg[1] == DX_REG_N && (rn & 1) != 0)))
1827         goto fail;
1828
1829       fprintf_fn (stream, "%s\t", op->name);
1830       disp_pc = 0;
1831       for (n = 0; n < 3 && op->arg[n] != A_END; n++)
1832         {
1833           if (n && op->arg[1] != A_END)
1834             fprintf_fn (stream, ",");
1835           switch (op->arg[n])
1836             {
1837             case A_IMM:
1838               fprintf_fn (stream, "#%d", imm);
1839               break;
1840             case A_R0:
1841               fprintf_fn (stream, "r0");
1842               break;
1843             case A_REG_N:
1844               fprintf_fn (stream, "r%d", rn);
1845               break;
1846             case A_INC_N:
1847             case AS_INC_N:
1848               fprintf_fn (stream, "@r%d+", rn);
1849               break;
1850             case A_DEC_N:
1851             case AS_DEC_N:
1852               fprintf_fn (stream, "@-r%d", rn);
1853               break;
1854             case A_IND_N:
1855             case AS_IND_N:
1856               fprintf_fn (stream, "@r%d", rn);
1857               break;
1858             case A_DISP_REG_N:
1859               fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rn);
1860               break;
1861             case AS_PMOD_N:
1862               fprintf_fn (stream, "@r%d+r8", rn);
1863               break;
1864             case A_REG_M:
1865               fprintf_fn (stream, "r%d", rm);
1866               break;
1867             case A_INC_M:
1868               fprintf_fn (stream, "@r%d+", rm);
1869               break;
1870             case A_DEC_M:
1871               fprintf_fn (stream, "@-r%d", rm);
1872               break;
1873             case A_IND_M:
1874               fprintf_fn (stream, "@r%d", rm);
1875               break;
1876             case A_DISP_REG_M:
1877               fprintf_fn (stream, "@(%d,r%d)", has_disp?disp:imm, rm);
1878               break;
1879             case A_REG_B:
1880               fprintf_fn (stream, "r%d_bank", rb);
1881               break;
1882             case A_DISP_PC:
1883               disp_pc = 1;
1884               disp_pc_addr = imm + 4 + (memaddr & relmask);
1885               (*info->print_address_func) (disp_pc_addr, info);
1886               break;
1887             case A_IND_R0_REG_N:
1888               fprintf_fn (stream, "@(r0,r%d)", rn);
1889               break;
1890             case A_IND_R0_REG_M:
1891               fprintf_fn (stream, "@(r0,r%d)", rm);
1892               break;
1893             case A_DISP_GBR:
1894               fprintf_fn (stream, "@(%d,gbr)", has_disp?disp:imm);
1895               break;
1896             case A_TBR:
1897               fprintf_fn (stream, "tbr");
1898               break;
1899             case A_DISP2_TBR:
1900               fprintf_fn (stream, "@@(%d,tbr)", has_disp?disp:imm);
1901               break;
1902             case A_INC_R15:
1903               fprintf_fn (stream, "@r15+");
1904               break;
1905             case A_DEC_R15:
1906               fprintf_fn (stream, "@-r15");
1907               break;
1908             case A_R0_GBR:
1909               fprintf_fn (stream, "@(r0,gbr)");
1910               break;
1911             case A_BDISP12:
1912             case A_BDISP8:
1913                 {
1914                     bfd_vma addr;
1915                     addr = imm + memaddr;
1916                     (*info->print_address_func) (addr, info);
1917                 }
1918               break;
1919             case A_SR:
1920               fprintf_fn (stream, "sr");
1921               break;
1922             case A_GBR:
1923               fprintf_fn (stream, "gbr");
1924               break;
1925             case A_VBR:
1926               fprintf_fn (stream, "vbr");
1927               break;
1928             case A_DSR:
1929               fprintf_fn (stream, "dsr");
1930               break;
1931             case A_MOD:
1932               fprintf_fn (stream, "mod");
1933               break;
1934             case A_RE:
1935               fprintf_fn (stream, "re");
1936               break;
1937             case A_RS:
1938               fprintf_fn (stream, "rs");
1939               break;
1940             case A_A0:
1941               fprintf_fn (stream, "a0");
1942               break;
1943             case A_X0:
1944               fprintf_fn (stream, "x0");
1945               break;
1946             case A_X1:
1947               fprintf_fn (stream, "x1");
1948               break;
1949             case A_Y0:
1950               fprintf_fn (stream, "y0");
1951               break;
1952             case A_Y1:
1953               fprintf_fn (stream, "y1");
1954               break;
1955             case DSP_REG_M:
1956               print_dsp_reg (rm, fprintf_fn, stream);
1957               break;
1958             case A_SSR:
1959               fprintf_fn (stream, "ssr");
1960               break;
1961             case A_SPC:
1962               fprintf_fn (stream, "spc");
1963               break;
1964             case A_MACH:
1965               fprintf_fn (stream, "mach");
1966               break;
1967             case A_MACL:
1968               fprintf_fn (stream, "macl");
1969               break;
1970             case A_PR:
1971               fprintf_fn (stream, "pr");
1972               break;
1973             case A_SGR:
1974               fprintf_fn (stream, "sgr");
1975               break;
1976             case A_DBR:
1977               fprintf_fn (stream, "dbr");
1978               break;
1979             case F_REG_N:
1980               fprintf_fn (stream, "fr%d", rn);
1981               break;
1982             case F_REG_M:
1983               fprintf_fn (stream, "fr%d", rm);
1984               break;
1985             case DX_REG_N:
1986               if (rn & 1)
1987                 {
1988                   fprintf_fn (stream, "xd%d", rn & ~1);
1989                   break;
1990                 }
1991             case D_REG_N:
1992               fprintf_fn (stream, "dr%d", rn);
1993               break;
1994             case DX_REG_M:
1995               if (rm & 1)
1996                 {
1997                   fprintf_fn (stream, "xd%d", rm & ~1);
1998                   break;
1999                 }
2000             case D_REG_M:
2001               fprintf_fn (stream, "dr%d", rm);
2002               break;
2003             case FPSCR_M:
2004             case FPSCR_N:
2005               fprintf_fn (stream, "fpscr");
2006               break;
2007             case FPUL_M:
2008             case FPUL_N:
2009               fprintf_fn (stream, "fpul");
2010               break;
2011             case F_FR0:
2012               fprintf_fn (stream, "fr0");
2013               break;
2014             case V_REG_N:
2015               fprintf_fn (stream, "fv%d", rn * 4);
2016               break;
2017             case V_REG_M:
2018               fprintf_fn (stream, "fv%d", rm * 4);
2019               break;
2020             case XMTRX_M4:
2021               fprintf_fn (stream, "xmtrx");
2022               break;
2023             default:
2024               abort ();
2025             }
2026         }
2027
2028 #if 0
2029       /* This code prints instructions in delay slots on the same line
2030          as the instruction which needs the delay slots.  This can be
2031          confusing, since other disassembler don't work this way, and
2032          it means that the instructions are not all in a line.  So I
2033          disabled it.  Ian.  */
2034       if (!(info->flags & 1)
2035           && (op->name[0] == 'j'
2036               || (op->name[0] == 'b'
2037                   && (op->name[1] == 'r'
2038                       || op->name[1] == 's'))
2039               || (op->name[0] == 'r' && op->name[1] == 't')
2040               || (op->name[0] == 'b' && op->name[2] == '.')))
2041         {
2042           info->flags |= 1;
2043           fprintf_fn (stream, "\t(slot ");
2044           print_insn_sh (memaddr + 2, info);
2045           info->flags &= ~1;
2046           fprintf_fn (stream, ")");
2047           return 4;
2048         }
2049 #endif
2050
2051       if (disp_pc && strcmp (op->name, "mova") != 0)
2052         {
2053           int size;
2054           bfd_byte bytes[4];
2055
2056           if (relmask == ~(bfd_vma) 1)
2057             size = 2;
2058           else
2059             size = 4;
2060           status = info->read_memory_func (disp_pc_addr, bytes, size, info);
2061           if (status == 0)
2062             {
2063               unsigned int val;
2064
2065               if (size == 2)
2066                 {
2067                   if (info->endian == BFD_ENDIAN_LITTLE)
2068                     val = bfd_getl16 (bytes);
2069                   else
2070                     val = bfd_getb16 (bytes);
2071                 }
2072               else
2073                 {
2074                   if (info->endian == BFD_ENDIAN_LITTLE)
2075                     val = bfd_getl32 (bytes);
2076                   else
2077                     val = bfd_getb32 (bytes);
2078                 }
2079               if ((*info->symbol_at_address_func) (val, info))
2080                 {
2081                   fprintf_fn (stream, "\t! 0x");
2082                   (*info->print_address_func) (val, info);
2083                 }
2084               else
2085                 fprintf_fn (stream, "\t! 0x%x", val);
2086             }
2087         }
2088
2089       return SH_MERGE_ARCH_SET (op->arch, arch_op32) ? 4 : 2;
2090     fail:
2091       ;
2092
2093     }
2094   fprintf_fn (stream, ".word 0x%x%x%x%x", nibs[0], nibs[1], nibs[2], nibs[3]);
2095   return 2;
2096 }