qemu/hw/ipf.c

   1 /*
   2  * Itanium Platform Emulator derived from QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Copyright (c) 2007 Intel
   7  * Ported for IA64 Platform Zhang Xiantao <xiantao.zhang@intel.com>
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a copy
  10  * of this software and associated documentation files (the "Software"), to deal
  11  * in the Software without restriction, including without limitation the rights
  12  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13  * copies of the Software, and to permit persons to whom the Software is
  14  * furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice shall be included in
  17  * all copies or substantial portions of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25  * THE SOFTWARE.
  26  */
  27
  28 #include "hw.h"
  29 #include "pc.h"
  30 #include "fdc.h"
  31 #include "pci.h"
  32 #include "block.h"
  33 #include "sysemu.h"
  34 #include "audio/audio.h"
  35 #include "net.h"
  36 #include "smbus.h"
  37 #include "boards.h"
  38 #include "firmware.h"
  39 #include "ia64intrin.h"
  40 #include <unistd.h>
  41 #include "device-assignment.h"
  42 #include "virtio-blk.h"
  43
  44 #include "qemu-kvm.h"
  45
  46 #define FW_FILENAME "Flash.fd"
  47
  48 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  49 #define ACPI_DATA_SIZE       0x10000
  50
  51 #define MAX_IDE_BUS 2
  52
  53 static fdctrl_t *floppy_controller;
  54 static RTCState *rtc_state;
  55 static PCIDevice *i440fx_state;
  56
  57 uint8_t *g_fw_start;
  58 static uint32_t ipf_to_legacy_io(target_phys_addr_t addr)
  59 {
  60     return (uint32_t)(((addr&0x3ffffff) >> 12 << 2)|((addr) & 0x3));
  61 }
  62
  63 static void ipf_legacy_io_writeb(void *opaque, target_phys_addr_t addr,
  64                                  uint32_t val) {
  65     uint32_t port = ipf_to_legacy_io(addr);
  66
  67     cpu_outb(0, port, val);
  68 }
  69
  70 static void ipf_legacy_io_writew(void *opaque, target_phys_addr_t addr,
  71                                  uint32_t val) {
  72     uint32_t port = ipf_to_legacy_io(addr);
  73
  74     cpu_outw(0, port, val);
  75 }
  76
  77 static void ipf_legacy_io_writel(void *opaque, target_phys_addr_t addr,
  78                                  uint32_t val) {
  79     uint32_t port = ipf_to_legacy_io(addr);
  80
  81     cpu_outl(0, port, val);
  82 }
  83
  84 static uint32_t ipf_legacy_io_readb(void *opaque, target_phys_addr_t addr)
  85 {
  86     uint32_t port = ipf_to_legacy_io(addr);
  87
  88     return cpu_inb(0, port);
  89 }
  90
  91 static uint32_t ipf_legacy_io_readw(void *opaque, target_phys_addr_t addr)
  92 {
  93     uint32_t port = ipf_to_legacy_io(addr);
  94
  95     return cpu_inw(0, port);
  96 }
  97
  98 static uint32_t ipf_legacy_io_readl(void *opaque, target_phys_addr_t addr)
  99 {
 100     uint32_t port = ipf_to_legacy_io(addr);
 101
 102     return cpu_inl(0, port);
 103 }
 104
 105 static CPUReadMemoryFunc *ipf_legacy_io_read[3] = {
 106     ipf_legacy_io_readb,
 107     ipf_legacy_io_readw,
 108     ipf_legacy_io_readl,
 109 };
 110
 111 static CPUWriteMemoryFunc *ipf_legacy_io_write[3] = {
 112     ipf_legacy_io_writeb,
 113     ipf_legacy_io_writew,
 114     ipf_legacy_io_writel,
 115 };
 116
 117 static void pic_irq_request(void *opaque, int irq, int level)
 118 {
 119     fprintf(stderr,"pic_irq_request called!\n");
 120 }
 121
 122 /* PC cmos mappings */
 123
 124 #define REG_EQUIPMENT_BYTE          0x14
 125
 126 static int cmos_get_fd_drive_type(int fd0)
 127 {
 128     int val;
 129
 130     switch (fd0) {
 131     case 0:
 132         /* 1.44 Mb 3"5 drive */
 133         val = 4;
 134         break;
 135     case 1:
 136         /* 2.88 Mb 3"5 drive */
 137         val = 5;
 138         break;
 139     case 2:
 140         /* 1.2 Mb 5"5 drive */
 141         val = 2;
 142         break;
 143     default:
 144         val = 0;
 145         break;
 146     }
 147     return val;
 148 }
 149
 150 static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
 151 {
 152     RTCState *s = rtc_state;
 153     int cylinders, heads, sectors;
 154
 155     bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
 156     rtc_set_memory(s, type_ofs, 47);
 157     rtc_set_memory(s, info_ofs, cylinders);
 158     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 159     rtc_set_memory(s, info_ofs + 2, heads);
 160     rtc_set_memory(s, info_ofs + 3, 0xff);
 161     rtc_set_memory(s, info_ofs + 4, 0xff);
 162     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 163     rtc_set_memory(s, info_ofs + 6, cylinders);
 164     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 165     rtc_set_memory(s, info_ofs + 8, sectors);
 166 }
 167
 168 /* convert boot_device letter to something recognizable by the bios */
 169 static int boot_device2nibble(char boot_device)
 170 {
 171     switch(boot_device) {
 172     case 'a':
 173     case 'b':
 174         return 0x01; /* floppy boot */
 175     case 'c':
 176         return 0x02; /* hard drive boot */
 177     case 'd':
 178         return 0x03; /* CD-ROM boot */
 179     case 'n':
 180         return 0x04; /* Network boot */
 181     }
 182     return 0;
 183 }
 184
 185 /* hd_table must contain 4 block drivers */
 186 static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 187                       const char *boot_device, BlockDriverState **hd_table)
 188 {
 189     RTCState *s = rtc_state;
 190     int nbds, bds[3] = { 0, };
 191     int val;
 192     int fd0, fd1, nb;
 193     int i;
 194
 195     /* various important CMOS locations needed by PC/Bochs bios */
 196
 197     /* memory size */
 198     val = 640; /* base memory in K */
 199     rtc_set_memory(s, 0x15, val);
 200     rtc_set_memory(s, 0x16, val >> 8);
 201
 202     val = (ram_size / 1024) - 1024;
 203     if (val > 65535)
 204         val = 65535;
 205     rtc_set_memory(s, 0x17, val);
 206     rtc_set_memory(s, 0x18, val >> 8);
 207     rtc_set_memory(s, 0x30, val);
 208     rtc_set_memory(s, 0x31, val >> 8);
 209
 210     if (above_4g_mem_size) {
 211         rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
 212         rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
 213         rtc_set_memory(s, 0x5d, above_4g_mem_size >> 32);
 214     }
 215     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 216
 217     if (ram_size > (16 * 1024 * 1024))
 218         val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
 219     else
 220         val = 0;
 221     if (val > 65535)
 222         val = 65535;
 223     rtc_set_memory(s, 0x34, val);
 224     rtc_set_memory(s, 0x35, val >> 8);
 225
 226     /* set boot devices, and disable floppy signature check if requested */
 227 #define PC_MAX_BOOT_DEVICES 3
 228     nbds = strlen(boot_device);
 229
 230     if (nbds > PC_MAX_BOOT_DEVICES) {
 231         fprintf(stderr, "Too many boot devices for PC\n");
 232         exit(1);
 233     }
 234
 235     for (i = 0; i < nbds; i++) {
 236         bds[i] = boot_device2nibble(boot_device[i]);
 237         if (bds[i] == 0) {
 238             fprintf(stderr, "Invalid boot device for PC: '%c'\n",
 239                     boot_device[i]);
 240             exit(1);
 241         }
 242     }
 243
 244     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 245     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
 246
 247     /* floppy type */
 248
 249     fd0 = fdctrl_get_drive_type(floppy_controller, 0);
 250     fd1 = fdctrl_get_drive_type(floppy_controller, 1);
 251
 252     val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
 253     rtc_set_memory(s, 0x10, val);
 254
 255     val = 0;
 256     nb = 0;
 257     if (fd0 < 3)
 258         nb++;
 259     if (fd1 < 3)
 260         nb++;
 261
 262     switch (nb) {
 263     case 0:
 264         break;
 265     case 1:
 266         val |= 0x01; /* 1 drive, ready for boot */
 267         break;
 268     case 2:
 269         val |= 0x41; /* 2 drives, ready for boot */
 270         break;
 271     }
 272
 273     val |= 0x02; /* FPU is there */
 274     val |= 0x04; /* PS/2 mouse installed */
 275     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 276
 277     /* hard drives */
 278
 279     rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
 280     if (hd_table[0])
 281         cmos_init_hd(0x19, 0x1b, hd_table[0]);
 282     if (hd_table[1])
 283         cmos_init_hd(0x1a, 0x24, hd_table[1]);
 284
 285     val = 0;
 286     for (i = 0; i < 4; i++) {
 287         if (hd_table[i]) {
 288             int cylinders, heads, sectors, translation;
 289             /* NOTE: bdrv_get_geometry_hint() returns the physical
 290                geometry.  It is always such that: 1 <= sects <= 63, 1
 291                <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 292                geometry can be different if a translation is done. */
 293             translation = bdrv_get_translation_hint(hd_table[i]);
 294             if (translation == BIOS_ATA_TRANSLATION_AUTO) {
 295                 bdrv_get_geometry_hint(hd_table[i], &cylinders,
 296                                        &heads, &sectors);
 297                 if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
 298                     /* No translation. */
 299                     translation = 0;
 300                 } else {
 301                     /* LBA translation. */
 302                     translation = 1;
 303                 }
 304             } else {
 305                 translation--;
 306             }
 307             val |= translation << (i * 2);
 308         }
 309     }
 310     rtc_set_memory(s, 0x39, val);
 311 }
 312
 313 static void main_cpu_reset(void *opaque)
 314 {
 315     CPUState *env = opaque;
 316     cpu_reset(env);
 317 }
 318
 319 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 320 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 321 static const int ide_irq[2] = { 14, 15 };
 322
 323 #define NE2000_NB_MAX 6
 324
 325 static int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340,
 326                                         0x360, 0x280, 0x380 };
 327 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 328
 329 static int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 330 static int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 331
 332 static int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 333 static int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 334
 335 #ifdef HAS_AUDIO
 336 static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
 337 {
 338     struct soundhw *c;
 339     int audio_enabled = 0;
 340
 341     for (c = soundhw; !audio_enabled && c->name; ++c) {
 342         audio_enabled = c->enabled;
 343     }
 344
 345     if (audio_enabled) {
 346         AudioState *s;
 347
 348         s = AUD_init ();
 349         if (s) {
 350             for (c = soundhw; c->name; ++c) {
 351                 if (c->enabled) {
 352                     if (c->isa) {
 353                         c->init.init_isa (s, pic);
 354                     } else {
 355                         if (pci_bus) {
 356                             c->init.init_pci (pci_bus, s);
 357                         }
 358                     }
 359                 }
 360             }
 361         }
 362     }
 363 }
 364 #endif
 365
 366 static void pc_init_ne2k_isa(NICInfo *nd, qemu_irq *pic)
 367 {
 368     static int nb_ne2k = 0;
 369
 370     if (nb_ne2k == NE2000_NB_MAX)
 371         return;
 372     isa_ne2000_init(ne2000_io[nb_ne2k], pic[ne2000_irq[nb_ne2k]], nd);
 373     nb_ne2k++;
 374 }
 375
 376 /* Itanium hardware initialisation */
 377 static void ipf_init1(ram_addr_t ram_size, int vga_ram_size,
 378                       const char *boot_device, DisplayState *ds,
 379                       const char *kernel_filename, const char *kernel_cmdline,
 380                       const char *initrd_filename,
 381                       int pci_enabled, const char *cpu_model)
 382 {
 383     char buf[1024];
 384     int i;
 385     ram_addr_t ram_addr, vga_ram_addr;
 386     ram_addr_t above_4g_mem_size = 0;
 387     PCIBus *pci_bus;
 388     int piix3_devfn = -1;
 389     CPUState *env;
 390     qemu_irq *cpu_irq;
 391     qemu_irq *i8259;
 392     int page_size;
 393     int index;
 394     unsigned long ipf_legacy_io_base, ipf_legacy_io_mem;
 395     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 396     BlockDriverState *fd[MAX_FD];
 397
 398     page_size = getpagesize();
 399     if (page_size != TARGET_PAGE_SIZE) {
 400         fprintf(stderr,"Error! Host page size != qemu target page size,"
 401                 " you may need to change TARGET_PAGE_BITS in qemu!"
 402                 "host page size:0x%x\n", page_size);
 403         exit(-1);
 404     };
 405
 406     if (ram_size >= 0xc0000000 ) {
 407         above_4g_mem_size = ram_size - 0xc0000000;
 408         ram_size = 0xc0000000;
 409     }
 410
 411     /* init CPUs */
 412     if (cpu_model == NULL) {
 413         cpu_model = "IA64";
 414     }
 415
 416     for(i = 0; i < smp_cpus; i++) {
 417         env = cpu_init(cpu_model);
 418         if (!env) {
 419             fprintf(stderr, "Unable to find CPU definition\n");
 420             exit(1);
 421         }
 422         if (i != 0)
 423             env->hflags |= HF_HALTED_MASK;
 424         register_savevm("cpu", i, 4, cpu_save, cpu_load, env);
 425         qemu_register_reset(main_cpu_reset, env);
 426     }
 427
 428     /* allocate RAM */
 429     if (kvm_enabled()) {
 430         ram_addr = qemu_ram_alloc(0xa0000);
 431         cpu_register_physical_memory(0, 0xa0000, ram_addr);
 432
 433         ram_addr = qemu_ram_alloc(0x20000); // Workaround 0xa0000-0xc0000
 434
 435         ram_addr = qemu_ram_alloc(0x40000);
 436         cpu_register_physical_memory(0xc0000, 0x40000, ram_addr);
 437
 438         ram_addr = qemu_ram_alloc(ram_size - 0x100000);
 439         cpu_register_physical_memory(0x100000, ram_size - 0x100000, ram_addr);
 440     } else {
 441         ram_addr = qemu_ram_alloc(ram_size);
 442         cpu_register_physical_memory(0, ram_size, ram_addr);
 443     }
 444     /* allocate VGA RAM */
 445     vga_ram_addr = qemu_ram_alloc(vga_ram_size);
 446
 447     /* above 4giga memory allocation */
 448     if (above_4g_mem_size > 0) {
 449         ram_addr = qemu_ram_alloc(above_4g_mem_size);
 450         cpu_register_physical_memory(0x100000000, above_4g_mem_size, ram_addr);
 451     }
 452
 453     /*Load firware to its proper position.*/
 454     if (kvm_enabled()) {
 455         unsigned long  image_size;
 456         char *image = NULL;
 457         uint8_t *fw_image_start;
 458         unsigned long nvram_addr = 0;
 459         unsigned long nvram_fd = 0;
 460         unsigned long type = READ_FROM_NVRAM;
 461         unsigned long i = 0;
 462         ram_addr_t fw_offset = qemu_ram_alloc(GFW_SIZE);
 463         uint8_t *fw_start = phys_ram_base + fw_offset;
 464
 465         g_fw_start = fw_start;
 466         snprintf(buf, sizeof(buf), "%s/%s", bios_dir, FW_FILENAME);
 467         image = read_image(buf, &image_size );
 468         if (NULL == image || !image_size) {
 469             fprintf(stderr, "Error when reading Guest Firmware!\n");
 470             fprintf(stderr, "Please check Guest firmware at %s\n", buf);
 471             exit(1);
 472         }
 473         fw_image_start = fw_start + GFW_SIZE - image_size;
 474
 475         cpu_register_physical_memory(GFW_START, GFW_SIZE, fw_offset);
 476         memcpy(fw_image_start, image, image_size);
 477
 478         free(image);
 479         flush_icache_range((unsigned long)fw_image_start,
 480                            (unsigned long)fw_image_start + image_size);
 481
 482         nvram_addr = NVRAM_START;
 483         if (nvram) {
 484             nvram_fd = kvm_ia64_nvram_init(type);
 485             if (nvram_fd != -1) {
 486                 kvm_ia64_copy_from_nvram_to_GFW(nvram_fd, g_fw_start);
 487                 close(nvram_fd);
 488             }
 489             i = atexit((void *)kvm_ia64_copy_from_GFW_to_nvram);
 490             if (i != 0)
 491                 fprintf(stderr, "cannot set exit function\n");
 492         }
 493         kvm_ia64_build_hob(ram_size + above_4g_mem_size, smp_cpus,
 494                            fw_start, nvram_addr);
 495     }
 496
 497     /*Register legacy io address space, size:64M*/
 498     ipf_legacy_io_base = 0xE0000000;
 499     ipf_legacy_io_mem = cpu_register_io_memory(0, ipf_legacy_io_read,
 500                                                ipf_legacy_io_write, NULL);
 501     cpu_register_physical_memory(ipf_legacy_io_base, 64*1024*1024,
 502                                  ipf_legacy_io_mem);
 503
 504     cpu_irq = qemu_allocate_irqs(pic_irq_request, first_cpu, 1);
 505     i8259 = i8259_init(cpu_irq[0]);
 506
 507     if (pci_enabled) {
 508         pci_bus = i440fx_init(&i440fx_state, i8259);
 509         piix3_devfn = piix3_init(pci_bus, -1);
 510     } else {
 511         pci_bus = NULL;
 512     }
 513
 514     if (cirrus_vga_enabled) {
 515         if (pci_enabled) {
 516             pci_cirrus_vga_init(pci_bus, phys_ram_base + vga_ram_addr,
 517                                 vga_ram_addr, vga_ram_size);
 518         } else {
 519             isa_cirrus_vga_init(phys_ram_base + vga_ram_addr,
 520                                 vga_ram_addr, vga_ram_size);
 521         }
 522     } else {
 523         if (pci_enabled) {
 524             pci_vga_init(pci_bus, phys_ram_base + vga_ram_addr,
 525                          vga_ram_addr, vga_ram_size, 0, 0);
 526         } else {
 527             isa_vga_init(phys_ram_base + vga_ram_addr,
 528                          vga_ram_addr, vga_ram_size);
 529         }
 530     }
 531
 532     rtc_state = rtc_init(0x70, i8259[8], 2000);
 533
 534     if (pci_enabled) {
 535         pic_set_alt_irq_func(isa_pic, NULL, NULL);
 536     }
 537
 538     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 539         if (serial_hds[i]) {
 540             serial_init(serial_io[i], i8259[serial_irq[i]], 115200,
 541                         serial_hds[i]);
 542         }
 543     }
 544
 545     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 546         if (parallel_hds[i]) {
 547             parallel_init(parallel_io[i], i8259[parallel_irq[i]],
 548                           parallel_hds[i]);
 549         }
 550     }
 551
 552     for(i = 0; i < nb_nics; i++) {
 553         NICInfo *nd = &nd_table[i];
 554
 555         if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
 556             pc_init_ne2k_isa(nd, i8259);
 557         else
 558             pci_nic_init(pci_bus, nd, -1, "e1000");
 559     }
 560
 561 #undef USE_HYPERCALL  //Disable it now, need to implement later!
 562 #ifdef USE_HYPERCALL
 563     pci_hypercall_init(pci_bus);
 564 #endif
 565
 566     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 567         fprintf(stderr, "qemu: too many IDE bus\n");
 568         exit(1);
 569     }
 570
 571     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 572         index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 573         if (index != -1)
 574             hd[i] = drives_table[index].bdrv;
 575         else
 576             hd[i] = NULL;
 577     }
 578
 579     if (pci_enabled) {
 580         pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1, i8259);
 581     } else {
 582         for(i = 0; i < MAX_IDE_BUS; i++) {
 583             isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
 584                          hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
 585         }
 586     }
 587
 588     i8042_init(i8259[1], i8259[12], 0x60);
 589     DMA_init(0);
 590 #ifdef HAS_AUDIO
 591     audio_init(pci_enabled ? pci_bus : NULL, i8259);
 592 #endif
 593
 594     for(i = 0; i < MAX_FD; i++) {
 595         index = drive_get_index(IF_FLOPPY, 0, i);
 596         if (index != -1)
 597             fd[i] = drives_table[index].bdrv;
 598         else
 599             fd[i] = NULL;
 600     }
 601     floppy_controller = fdctrl_init(i8259[6], 2, 0, 0x3f0, fd);
 602
 603     cmos_init(ram_size, above_4g_mem_size, boot_device, hd);
 604
 605     if (pci_enabled && usb_enabled) {
 606         usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
 607     }
 608
 609     if (pci_enabled && acpi_enabled) {
 610         uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
 611         i2c_bus *smbus;
 612
 613         /* TODO: Populate SPD eeprom data.  */
 614         smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, i8259[9]);
 615         for (i = 0; i < 8; i++) {
 616             smbus_eeprom_device_init(smbus, 0x50 + i, eeprom_buf + (i * 256));
 617         }
 618     }
 619
 620     if (i440fx_state) {
 621         i440fx_init_memory_mappings(i440fx_state);
 622     }
 623
 624     if (pci_enabled) {
 625         int max_bus;
 626         int bus, unit;
 627         void *scsi;
 628
 629         max_bus = drive_get_max_bus(IF_SCSI);
 630
 631         for (bus = 0; bus <= max_bus; bus++) {
 632             scsi = lsi_scsi_init(pci_bus, -1);
 633             for (unit = 0; unit < LSI_MAX_DEVS; unit++) {
 634                 index = drive_get_index(IF_SCSI, bus, unit);
 635                 if (index == -1)
 636                     continue;
 637                 lsi_scsi_attach(scsi, drives_table[index].bdrv, unit);
 638             }
 639         }
 640     }
 641     /* Add virtio block devices */
 642     if (pci_enabled) {
 643         int index;
 644         int unit_id = 0;
 645
 646         while ((index = drive_get_index(IF_VIRTIO, 0, unit_id)) != -1) {
 647             virtio_blk_init(pci_bus, drives_table[index].bdrv);
 648             unit_id++;
 649         }
 650     }
 651
 652 #ifdef USE_KVM_DEVICE_ASSIGNMENT
 653     if (kvm_enabled())
 654         add_assigned_devices(pci_bus, assigned_devices, assigned_devices_index);
 655 #endif /* USE_KVM_DEVICE_ASSIGNMENT */
 656
 657 }
 658
 659 static void ipf_init_pci(ram_addr_t ram_size, int vga_ram_size,
 660                          const char *boot_device, DisplayState *ds,
 661                          const char *kernel_filename,
 662                          const char *kernel_cmdline,
 663                          const char *initrd_filename,
 664                          const char *cpu_model)
 665 {
 666     ipf_init1(ram_size, vga_ram_size, boot_device, ds, kernel_filename,
 667               kernel_cmdline, initrd_filename, 1, cpu_model);
 668 }
 669
 670 QEMUMachine ipf_machine = {
 671     .name = "itanium",
 672     .desc = "Itanium Platform",
 673     .init = (QEMUMachineInitFunc *)ipf_init_pci,
 674     .ram_require = (ram_addr_t)(VGA_RAM_SIZE + GFW_SIZE),
 675     .max_cpus = 255,
 676 };
 677
 678 #define IOAPIC_NUM_PINS 48
 679
 680 static int ioapic_irq_count[IOAPIC_NUM_PINS];
 681
 682 static int ioapic_map_irq(int devfn, int irq_num)
 683 {
 684     int irq, dev;
 685     dev = devfn >> 3;
 686     irq = ((((dev << 2) + (dev >> 3) + irq_num) & 31) + 16);
 687     return irq;
 688 }
 689
 690 /*
 691  * Dummy function to provide match for call from hw/apic.c
 692  */
 693 void apic_set_irq_delivered(void) {
 694 }
 695
 696 void ioapic_set_irq(void *opaque, int irq_num, int level)
 697 {
 698     int vector, pic_ret;
 699
 700     PCIDevice *pci_dev = (PCIDevice *)opaque;
 701     vector = ioapic_map_irq(pci_dev->devfn, irq_num);
 702
 703     if (level)
 704         ioapic_irq_count[vector] += 1;
 705     else
 706         ioapic_irq_count[vector] -= 1;
 707
 708     if (kvm_enabled()) {
 709         if (kvm_set_irq(vector, ioapic_irq_count[vector] == 0, &pic_ret))
 710             if (pic_ret != 0)
 711                 apic_set_irq_delivered();
 712             return;
 713     }
 714 }
 715
 716 int ipf_map_irq(PCIDevice *pci_dev, int irq_num)
 717 {
 718         return ioapic_map_irq(pci_dev->devfn, irq_num);
 719 }