qemu/hw/omap_mmc.c

   1 /*
   2  * OMAP on-chip MMC/SD host emulation.
   3  *
   4  * Copyright (C) 2006-2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 or
   9  * (at your option) version 3 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21 #include "hw.h"
  22 #include "omap.h"
  23 #include "sd.h"
  24
  25 struct omap_mmc_s {
  26     target_phys_addr_t base;
  27     qemu_irq irq;
  28     qemu_irq *dma;
  29     qemu_irq coverswitch;
  30     omap_clk clk;
  31     SDState *card;
  32     uint16_t last_cmd;
  33     uint16_t sdio;
  34     uint16_t rsp[8];
  35     uint32_t arg;
  36     int lines;
  37     int dw;
  38     int mode;
  39     int enable;
  40     int be;
  41     int rev;
  42     uint16_t status;
  43     uint16_t mask;
  44     uint8_t cto;
  45     uint16_t dto;
  46     int clkdiv;
  47     uint16_t fifo[32];
  48     int fifo_start;
  49     int fifo_len;
  50     uint16_t blen;
  51     uint16_t blen_counter;
  52     uint16_t nblk;
  53     uint16_t nblk_counter;
  54     int tx_dma;
  55     int rx_dma;
  56     int af_level;
  57     int ae_level;
  58
  59     int ddir;
  60     int transfer;
  61
  62     int cdet_wakeup;
  63     int cdet_enable;
  64     int cdet_state;
  65     qemu_irq cdet;
  66 };
  67
  68 static void omap_mmc_interrupts_update(struct omap_mmc_s *s)
  69 {
  70     qemu_set_irq(s->irq, !!(s->status & s->mask));
  71 }
  72
  73 static void omap_mmc_fifolevel_update(struct omap_mmc_s *host)
  74 {
  75     if (!host->transfer && !host->fifo_len) {
  76         host->status &= 0xf3ff;
  77         return;
  78     }
  79
  80     if (host->fifo_len > host->af_level && host->ddir) {
  81         if (host->rx_dma) {
  82             host->status &= 0xfbff;
  83             qemu_irq_raise(host->dma[1]);
  84         } else
  85             host->status |= 0x0400;
  86     } else {
  87         host->status &= 0xfbff;
  88         qemu_irq_lower(host->dma[1]);
  89     }
  90
  91     if (host->fifo_len < host->ae_level && !host->ddir) {
  92         if (host->tx_dma) {
  93             host->status &= 0xf7ff;
  94             qemu_irq_raise(host->dma[0]);
  95         } else
  96             host->status |= 0x0800;
  97     } else {
  98         qemu_irq_lower(host->dma[0]);
  99         host->status &= 0xf7ff;
 100     }
 101 }
 102
 103 typedef enum {
 104     sd_nore = 0,        /* no response */
 105     sd_r1,              /* normal response command */
 106     sd_r2,              /* CID, CSD registers */
 107     sd_r3,              /* OCR register */
 108     sd_r6 = 6,          /* Published RCA response */
 109     sd_r1b = -1,
 110 } sd_rsp_type_t;
 111
 112 static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir,
 113                 sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init)
 114 {
 115     uint32_t rspstatus, mask;
 116     int rsplen, timeout;
 117     struct sd_request_s request;
 118     uint8_t response[16];
 119
 120     if (init && cmd == 0) {
 121         host->status |= 0x0001;
 122         return;
 123     }
 124
 125     if (resptype == sd_r1 && busy)
 126         resptype = sd_r1b;
 127
 128     if (type == sd_adtc) {
 129         host->fifo_start = 0;
 130         host->fifo_len = 0;
 131         host->transfer = 1;
 132         host->ddir = dir;
 133     } else
 134         host->transfer = 0;
 135     timeout = 0;
 136     mask = 0;
 137     rspstatus = 0;
 138
 139     request.cmd = cmd;
 140     request.arg = host->arg;
 141     request.crc = 0; /* FIXME */
 142
 143     rsplen = sd_do_command(host->card, &request, response);
 144
 145     /* TODO: validate CRCs */
 146     switch (resptype) {
 147     case sd_nore:
 148         rsplen = 0;
 149         break;
 150
 151     case sd_r1:
 152     case sd_r1b:
 153         if (rsplen < 4) {
 154             timeout = 1;
 155             break;
 156         }
 157         rsplen = 4;
 158
 159         mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR |
 160                 ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION |
 161                 LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND |
 162                 CARD_ECC_FAILED | CC_ERROR | SD_ERROR |
 163                 CID_CSD_OVERWRITE;
 164         if (host->sdio & (1 << 13))
 165             mask |= AKE_SEQ_ERROR;
 166         rspstatus = (response[0] << 24) | (response[1] << 16) |
 167                 (response[2] << 8) | (response[3] << 0);
 168         break;
 169
 170     case sd_r2:
 171         if (rsplen < 16) {
 172             timeout = 1;
 173             break;
 174         }
 175         rsplen = 16;
 176         break;
 177
 178     case sd_r3:
 179         if (rsplen < 4) {
 180             timeout = 1;
 181             break;
 182         }
 183         rsplen = 4;
 184
 185         rspstatus = (response[0] << 24) | (response[1] << 16) |
 186                 (response[2] << 8) | (response[3] << 0);
 187         if (rspstatus & 0x80000000)
 188             host->status &= 0xe000;
 189         else
 190             host->status |= 0x1000;
 191         break;
 192
 193     case sd_r6:
 194         if (rsplen < 4) {
 195             timeout = 1;
 196             break;
 197         }
 198         rsplen = 4;
 199
 200         mask = 0xe000 | AKE_SEQ_ERROR;
 201         rspstatus = (response[2] << 8) | (response[3] << 0);
 202     }
 203
 204     if (rspstatus & mask)
 205         host->status |= 0x4000;
 206     else
 207         host->status &= 0xb000;
 208
 209     if (rsplen)
 210         for (rsplen = 0; rsplen < 8; rsplen ++)
 211             host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] |
 212                     (response[(rsplen << 1) | 0] << 8);
 213
 214     if (timeout)
 215         host->status |= 0x0080;
 216     else if (cmd == 12)
 217         host->status |= 0x0005; /* Makes it more real */
 218     else
 219         host->status |= 0x0001;
 220 }
 221
 222 static void omap_mmc_transfer(struct omap_mmc_s *host)
 223 {
 224     uint8_t value;
 225
 226     if (!host->transfer)
 227         return;
 228
 229     while (1) {
 230         if (host->ddir) {
 231             if (host->fifo_len > host->af_level)
 232                 break;
 233
 234             value = sd_read_data(host->card);
 235             host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
 236             if (-- host->blen_counter) {
 237                 value = sd_read_data(host->card);
 238                 host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
 239                         value << 8;
 240                 host->blen_counter --;
 241             }
 242
 243             host->fifo_len ++;
 244         } else {
 245             if (!host->fifo_len)
 246                 break;
 247
 248             value = host->fifo[host->fifo_start] & 0xff;
 249             sd_write_data(host->card, value);
 250             if (-- host->blen_counter) {
 251                 value = host->fifo[host->fifo_start] >> 8;
 252                 sd_write_data(host->card, value);
 253                 host->blen_counter --;
 254             }
 255
 256             host->fifo_start ++;
 257             host->fifo_len --;
 258             host->fifo_start &= 31;
 259         }
 260
 261         if (host->blen_counter == 0) {
 262             host->nblk_counter --;
 263             host->blen_counter = host->blen;
 264
 265             if (host->nblk_counter == 0) {
 266                 host->nblk_counter = host->nblk;
 267                 host->transfer = 0;
 268                 host->status |= 0x0008;
 269                 break;
 270             }
 271         }
 272     }
 273 }
 274
 275 static void omap_mmc_update(void *opaque)
 276 {
 277     struct omap_mmc_s *s = opaque;
 278     omap_mmc_transfer(s);
 279     omap_mmc_fifolevel_update(s);
 280     omap_mmc_interrupts_update(s);
 281 }
 282
 283 void omap_mmc_reset(struct omap_mmc_s *host)
 284 {
 285     host->last_cmd = 0;
 286     memset(host->rsp, 0, sizeof(host->rsp));
 287     host->arg = 0;
 288     host->dw = 0;
 289     host->mode = 0;
 290     host->enable = 0;
 291     host->status = 0;
 292     host->mask = 0;
 293     host->cto = 0;
 294     host->dto = 0;
 295     host->fifo_len = 0;
 296     host->blen = 0;
 297     host->blen_counter = 0;
 298     host->nblk = 0;
 299     host->nblk_counter = 0;
 300     host->tx_dma = 0;
 301     host->rx_dma = 0;
 302     host->ae_level = 0x00;
 303     host->af_level = 0x1f;
 304     host->transfer = 0;
 305     host->cdet_wakeup = 0;
 306     host->cdet_enable = 0;
 307     qemu_set_irq(host->coverswitch, host->cdet_state);
 308     host->clkdiv = 0;
 309 }
 310
 311 static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset)
 312 {
 313     uint16_t i;
 314     struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
 315     offset &= OMAP_MPUI_REG_MASK;
 316
 317     switch (offset) {
 318     case 0x00:  /* MMC_CMD */
 319         return s->last_cmd;
 320
 321     case 0x04:  /* MMC_ARGL */
 322         return s->arg & 0x0000ffff;
 323
 324     case 0x08:  /* MMC_ARGH */
 325         return s->arg >> 16;
 326
 327     case 0x0c:  /* MMC_CON */
 328         return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) |
 329                 (s->be << 10) | s->clkdiv;
 330
 331     case 0x10:  /* MMC_STAT */
 332         return s->status;
 333
 334     case 0x14:  /* MMC_IE */
 335         return s->mask;
 336
 337     case 0x18:  /* MMC_CTO */
 338         return s->cto;
 339
 340     case 0x1c:  /* MMC_DTO */
 341         return s->dto;
 342
 343     case 0x20:  /* MMC_DATA */
 344         /* TODO: support 8-bit access */
 345         i = s->fifo[s->fifo_start];
 346         if (s->fifo_len == 0) {
 347             printf("MMC: FIFO underrun\n");
 348             return i;
 349         }
 350         s->fifo_start ++;
 351         s->fifo_len --;
 352         s->fifo_start &= 31;
 353         omap_mmc_transfer(s);
 354         omap_mmc_fifolevel_update(s);
 355         omap_mmc_interrupts_update(s);
 356         return i;
 357
 358     case 0x24:  /* MMC_BLEN */
 359         return s->blen_counter;
 360
 361     case 0x28:  /* MMC_NBLK */
 362         return s->nblk_counter;
 363
 364     case 0x2c:  /* MMC_BUF */
 365         return (s->rx_dma << 15) | (s->af_level << 8) |
 366             (s->tx_dma << 7) | s->ae_level;
 367
 368     case 0x30:  /* MMC_SPI */
 369         return 0x0000;
 370     case 0x34:  /* MMC_SDIO */
 371         return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio;
 372     case 0x38:  /* MMC_SYST */
 373         return 0x0000;
 374
 375     case 0x3c:  /* MMC_REV */
 376         return s->rev;
 377
 378     case 0x40:  /* MMC_RSP0 */
 379     case 0x44:  /* MMC_RSP1 */
 380     case 0x48:  /* MMC_RSP2 */
 381     case 0x4c:  /* MMC_RSP3 */
 382     case 0x50:  /* MMC_RSP4 */
 383     case 0x54:  /* MMC_RSP5 */
 384     case 0x58:  /* MMC_RSP6 */
 385     case 0x5c:  /* MMC_RSP7 */
 386         return s->rsp[(offset - 0x40) >> 2];
 387
 388     /* OMAP2-specific */
 389     case 0x60:  /* MMC_IOSR */
 390     case 0x64:  /* MMC_SYSC */
 391         return 0;
 392     case 0x68:  /* MMC_SYSS */
 393         return 1;                                               /* RSTD */
 394     }
 395
 396     OMAP_BAD_REG(offset);
 397     return 0;
 398 }
 399
 400 static void omap_mmc_write(void *opaque, target_phys_addr_t offset,
 401                 uint32_t value)
 402 {
 403     int i;
 404     struct omap_mmc_s *s = (struct omap_mmc_s *) opaque;
 405     offset &= OMAP_MPUI_REG_MASK;
 406
 407     switch (offset) {
 408     case 0x00:  /* MMC_CMD */
 409         if (!s->enable)
 410             break;
 411
 412         s->last_cmd = value;
 413         for (i = 0; i < 8; i ++)
 414             s->rsp[i] = 0x0000;
 415         omap_mmc_command(s, value & 63, (value >> 15) & 1,
 416                 (sd_cmd_type_t) ((value >> 12) & 3),
 417                 (value >> 11) & 1,
 418                 (sd_rsp_type_t) ((value >> 8) & 7),
 419                 (value >> 7) & 1);
 420         omap_mmc_update(s);
 421         break;
 422
 423     case 0x04:  /* MMC_ARGL */
 424         s->arg &= 0xffff0000;
 425         s->arg |= 0x0000ffff & value;
 426         break;
 427
 428     case 0x08:  /* MMC_ARGH */
 429         s->arg &= 0x0000ffff;
 430         s->arg |= value << 16;
 431         break;
 432
 433     case 0x0c:  /* MMC_CON */
 434         s->dw = (value >> 15) & 1;
 435         s->mode = (value >> 12) & 3;
 436         s->enable = (value >> 11) & 1;
 437         s->be = (value >> 10) & 1;
 438         s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff);
 439         if (s->mode != 0)
 440             printf("SD mode %i unimplemented!\n", s->mode);
 441         if (s->be != 0)
 442             printf("SD FIFO byte sex unimplemented!\n");
 443         if (s->dw != 0 && s->lines < 4)
 444             printf("4-bit SD bus enabled\n");
 445         if (!s->enable)
 446             omap_mmc_reset(s);
 447         break;
 448
 449     case 0x10:  /* MMC_STAT */
 450         s->status &= ~value;
 451         omap_mmc_interrupts_update(s);
 452         break;
 453
 454     case 0x14:  /* MMC_IE */
 455         s->mask = value & 0x7fff;
 456         omap_mmc_interrupts_update(s);
 457         break;
 458
 459     case 0x18:  /* MMC_CTO */
 460         s->cto = value & 0xff;
 461         if (s->cto > 0xfd && s->rev <= 1)
 462             printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
 463         break;
 464
 465     case 0x1c:  /* MMC_DTO */
 466         s->dto = value & 0xffff;
 467         break;
 468
 469     case 0x20:  /* MMC_DATA */
 470         /* TODO: support 8-bit access */
 471         if (s->fifo_len == 32)
 472             break;
 473         s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
 474         s->fifo_len ++;
 475         omap_mmc_transfer(s);
 476         omap_mmc_fifolevel_update(s);
 477         omap_mmc_interrupts_update(s);
 478         break;
 479
 480     case 0x24:  /* MMC_BLEN */
 481         s->blen = (value & 0x07ff) + 1;
 482         s->blen_counter = s->blen;
 483         break;
 484
 485     case 0x28:  /* MMC_NBLK */
 486         s->nblk = (value & 0x07ff) + 1;
 487         s->nblk_counter = s->nblk;
 488         s->blen_counter = s->blen;
 489         break;
 490
 491     case 0x2c:  /* MMC_BUF */
 492         s->rx_dma = (value >> 15) & 1;
 493         s->af_level = (value >> 8) & 0x1f;
 494         s->tx_dma = (value >> 7) & 1;
 495         s->ae_level = value & 0x1f;
 496
 497         if (s->rx_dma)
 498             s->status &= 0xfbff;
 499         if (s->tx_dma)
 500             s->status &= 0xf7ff;
 501         omap_mmc_fifolevel_update(s);
 502         omap_mmc_interrupts_update(s);
 503         break;
 504
 505     /* SPI, SDIO and TEST modes unimplemented */
 506     case 0x30:  /* MMC_SPI (OMAP1 only) */
 507         break;
 508     case 0x34:  /* MMC_SDIO */
 509         s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020);
 510         s->cdet_wakeup = (value >> 9) & 1;
 511         s->cdet_enable = (value >> 2) & 1;
 512         break;
 513     case 0x38:  /* MMC_SYST */
 514         break;
 515
 516     case 0x3c:  /* MMC_REV */
 517     case 0x40:  /* MMC_RSP0 */
 518     case 0x44:  /* MMC_RSP1 */
 519     case 0x48:  /* MMC_RSP2 */
 520     case 0x4c:  /* MMC_RSP3 */
 521     case 0x50:  /* MMC_RSP4 */
 522     case 0x54:  /* MMC_RSP5 */
 523     case 0x58:  /* MMC_RSP6 */
 524     case 0x5c:  /* MMC_RSP7 */
 525         OMAP_RO_REG(offset);
 526         break;
 527
 528     /* OMAP2-specific */
 529     case 0x60:  /* MMC_IOSR */
 530         if (value & 0xf)
 531             printf("MMC: SDIO bits used!\n");
 532         break;
 533     case 0x64:  /* MMC_SYSC */
 534         if (value & (1 << 2))                                   /* SRTS */
 535             omap_mmc_reset(s);
 536         break;
 537     case 0x68:  /* MMC_SYSS */
 538         OMAP_RO_REG(offset);
 539         break;
 540
 541     default:
 542         OMAP_BAD_REG(offset);
 543     }
 544 }
 545
 546 static CPUReadMemoryFunc *omap_mmc_readfn[] = {
 547     omap_badwidth_read16,
 548     omap_mmc_read,
 549     omap_badwidth_read16,
 550 };
 551
 552 static CPUWriteMemoryFunc *omap_mmc_writefn[] = {
 553     omap_badwidth_write16,
 554     omap_mmc_write,
 555     omap_badwidth_write16,
 556 };
 557
 558 static void omap_mmc_cover_cb(void *opaque, int line, int level)
 559 {
 560     struct omap_mmc_s *host = (struct omap_mmc_s *) opaque;
 561
 562     if (!host->cdet_state && level) {
 563         host->status |= 0x0002;
 564         omap_mmc_interrupts_update(host);
 565         if (host->cdet_wakeup)
 566             /* TODO: Assert wake-up */;
 567     }
 568
 569     if (host->cdet_state != level) {
 570         qemu_set_irq(host->coverswitch, level);
 571         host->cdet_state = level;
 572     }
 573 }
 574
 575 struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
 576                 BlockDriverState *bd,
 577                 qemu_irq irq, qemu_irq dma[], omap_clk clk)
 578 {
 579     int iomemtype;
 580     struct omap_mmc_s *s = (struct omap_mmc_s *)
 581             qemu_mallocz(sizeof(struct omap_mmc_s));
 582
 583     s->irq = irq;
 584     s->base = base;
 585     s->dma = dma;
 586     s->clk = clk;
 587     s->lines = 1;       /* TODO: needs to be settable per-board */
 588     s->rev = 1;
 589
 590     omap_mmc_reset(s);
 591
 592     iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
 593                     omap_mmc_writefn, s);
 594     cpu_register_physical_memory(s->base, 0x800, iomemtype);
 595
 596     /* Instantiate the storage */
 597     s->card = sd_init(bd, 0);
 598
 599     return s;
 600 }
 601
 602 struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta,
 603                 BlockDriverState *bd, qemu_irq irq, qemu_irq dma[],
 604                 omap_clk fclk, omap_clk iclk)
 605 {
 606     int iomemtype;
 607     struct omap_mmc_s *s = (struct omap_mmc_s *)
 608             qemu_mallocz(sizeof(struct omap_mmc_s));
 609
 610     s->irq = irq;
 611     s->dma = dma;
 612     s->clk = fclk;
 613     s->lines = 4;
 614     s->rev = 2;
 615
 616     omap_mmc_reset(s);
 617
 618     iomemtype = l4_register_io_memory(0, omap_mmc_readfn,
 619                     omap_mmc_writefn, s);
 620     s->base = omap_l4_attach(ta, 0, iomemtype);
 621
 622     /* Instantiate the storage */
 623     s->card = sd_init(bd, 0);
 624
 625     s->cdet = qemu_allocate_irqs(omap_mmc_cover_cb, s, 1)[0];
 626     sd_set_cb(s->card, 0, s->cdet);
 627
 628     return s;
 629 }
 630
 631 void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover)
 632 {
 633     if (s->cdet) {
 634         sd_set_cb(s->card, ro, s->cdet);
 635         s->coverswitch = cover;
 636         qemu_set_irq(cover, s->cdet_state);
 637     } else
 638         sd_set_cb(s->card, ro, cover);
 639 }
 640
 641 void omap_mmc_enable(struct omap_mmc_s *s, int enable)
 642 {
 643     sd_enable(s->card, enable);
 644 }