qemu/hw/pxa2xx_pic.c

   1 /*
   2  * Intel XScale PXA Programmable Interrupt Controller.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Copyright (c) 2006 Thorsten Zitterell
   6  * Written by Andrzej Zaborowski <balrog@zabor.org>
   7  *
   8  * This code is licenced under the GPL.
   9  */
  10
  11 #include "hw.h"
  12 #include "pxa.h"
  13
  14 #define ICIP    0x00    /* Interrupt Controller IRQ Pending register */
  15 #define ICMR    0x04    /* Interrupt Controller Mask register */
  16 #define ICLR    0x08    /* Interrupt Controller Level register */
  17 #define ICFP    0x0c    /* Interrupt Controller FIQ Pending register */
  18 #define ICPR    0x10    /* Interrupt Controller Pending register */
  19 #define ICCR    0x14    /* Interrupt Controller Control register */
  20 #define ICHP    0x18    /* Interrupt Controller Highest Priority register */
  21 #define IPR0    0x1c    /* Interrupt Controller Priority register 0 */
  22 #define IPR31   0x98    /* Interrupt Controller Priority register 31 */
  23 #define ICIP2   0x9c    /* Interrupt Controller IRQ Pending register 2 */
  24 #define ICMR2   0xa0    /* Interrupt Controller Mask register 2 */
  25 #define ICLR2   0xa4    /* Interrupt Controller Level register 2 */
  26 #define ICFP2   0xa8    /* Interrupt Controller FIQ Pending register 2 */
  27 #define ICPR2   0xac    /* Interrupt Controller Pending register 2 */
  28 #define IPR32   0xb0    /* Interrupt Controller Priority register 32 */
  29 #define IPR39   0xcc    /* Interrupt Controller Priority register 39 */
  30
  31 #define PXA2XX_PIC_SRCS 40
  32
  33 struct pxa2xx_pic_state_s {
  34     target_phys_addr_t base;
  35     CPUState *cpu_env;
  36     uint32_t int_enabled[2];
  37     uint32_t int_pending[2];
  38     uint32_t is_fiq[2];
  39     uint32_t int_idle;
  40     uint32_t priority[PXA2XX_PIC_SRCS];
  41 };
  42
  43 static void pxa2xx_pic_update(void *opaque)
  44 {
  45     uint32_t mask[2];
  46     struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
  47
  48     if (s->cpu_env->halted) {
  49         mask[0] = s->int_pending[0] & (s->int_enabled[0] | s->int_idle);
  50         mask[1] = s->int_pending[1] & (s->int_enabled[1] | s->int_idle);
  51         if (mask[0] || mask[1])
  52             cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
  53     }
  54
  55     mask[0] = s->int_pending[0] & s->int_enabled[0];
  56     mask[1] = s->int_pending[1] & s->int_enabled[1];
  57
  58     if ((mask[0] & s->is_fiq[0]) || (mask[1] & s->is_fiq[1]))
  59         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ);
  60     else
  61         cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_FIQ);
  62
  63     if ((mask[0] & ~s->is_fiq[0]) || (mask[1] & ~s->is_fiq[1]))
  64         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
  65     else
  66         cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
  67 }
  68
  69 /* Note: Here level means state of the signal on a pin, not
  70  * IRQ/FIQ distinction as in PXA Developer Manual.  */
  71 static void pxa2xx_pic_set_irq(void *opaque, int irq, int level)
  72 {
  73     struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
  74     int int_set = (irq >= 32);
  75     irq &= 31;
  76
  77     if (level)
  78         s->int_pending[int_set] |= 1 << irq;
  79     else
  80         s->int_pending[int_set] &= ~(1 << irq);
  81
  82     pxa2xx_pic_update(opaque);
  83 }
  84
  85 static inline uint32_t pxa2xx_pic_highest(struct pxa2xx_pic_state_s *s) {
  86     int i, int_set, irq;
  87     uint32_t bit, mask[2];
  88     uint32_t ichp = 0x003f003f; /* Both IDs invalid */
  89
  90     mask[0] = s->int_pending[0] & s->int_enabled[0];
  91     mask[1] = s->int_pending[1] & s->int_enabled[1];
  92
  93     for (i = PXA2XX_PIC_SRCS - 1; i >= 0; i --) {
  94         irq = s->priority[i] & 0x3f;
  95         if ((s->priority[i] & (1 << 31)) && irq < PXA2XX_PIC_SRCS) {
  96             /* Source peripheral ID is valid.  */
  97             bit = 1 << (irq & 31);
  98             int_set = (irq >= 32);
  99
 100             if (mask[int_set] & bit & s->is_fiq[int_set]) {
 101                 /* FIQ asserted */
 102                 ichp &= 0xffff0000;
 103                 ichp |= (1 << 15) | irq;
 104             }
 105
 106             if (mask[int_set] & bit & ~s->is_fiq[int_set]) {
 107                 /* IRQ asserted */
 108                 ichp &= 0x0000ffff;
 109                 ichp |= (1 << 31) | (irq << 16);
 110             }
 111         }
 112     }
 113
 114     return ichp;
 115 }
 116
 117 static uint32_t pxa2xx_pic_mem_read(void *opaque, target_phys_addr_t offset)
 118 {
 119     struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
 120     offset -= s->base;
 121
 122     switch (offset) {
 123     case ICIP:  /* IRQ Pending register */
 124         return s->int_pending[0] & ~s->is_fiq[0] & s->int_enabled[0];
 125     case ICIP2: /* IRQ Pending register 2 */
 126         return s->int_pending[1] & ~s->is_fiq[1] & s->int_enabled[1];
 127     case ICMR:  /* Mask register */
 128         return s->int_enabled[0];
 129     case ICMR2: /* Mask register 2 */
 130         return s->int_enabled[1];
 131     case ICLR:  /* Level register */
 132         return s->is_fiq[0];
 133     case ICLR2: /* Level register 2 */
 134         return s->is_fiq[1];
 135     case ICCR:  /* Idle mask */
 136         return (s->int_idle == 0);
 137     case ICFP:  /* FIQ Pending register */
 138         return s->int_pending[0] & s->is_fiq[0] & s->int_enabled[0];
 139     case ICFP2: /* FIQ Pending register 2 */
 140         return s->int_pending[1] & s->is_fiq[1] & s->int_enabled[1];
 141     case ICPR:  /* Pending register */
 142         return s->int_pending[0];
 143     case ICPR2: /* Pending register 2 */
 144         return s->int_pending[1];
 145     case IPR0  ... IPR31:
 146         return s->priority[0  + ((offset - IPR0 ) >> 2)];
 147     case IPR32 ... IPR39:
 148         return s->priority[32 + ((offset - IPR32) >> 2)];
 149     case ICHP:  /* Highest Priority register */
 150         return pxa2xx_pic_highest(s);
 151     default:
 152         printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
 153         return 0;
 154     }
 155 }
 156
 157 static void pxa2xx_pic_mem_write(void *opaque, target_phys_addr_t offset,
 158                 uint32_t value)
 159 {
 160     struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
 161     offset -= s->base;
 162
 163     switch (offset) {
 164     case ICMR:  /* Mask register */
 165         s->int_enabled[0] = value;
 166         break;
 167     case ICMR2: /* Mask register 2 */
 168         s->int_enabled[1] = value;
 169         break;
 170     case ICLR:  /* Level register */
 171         s->is_fiq[0] = value;
 172         break;
 173     case ICLR2: /* Level register 2 */
 174         s->is_fiq[1] = value;
 175         break;
 176     case ICCR:  /* Idle mask */
 177         s->int_idle = (value & 1) ? 0 : ~0;
 178         break;
 179     case IPR0  ... IPR31:
 180         s->priority[0  + ((offset - IPR0 ) >> 2)] = value & 0x8000003f;
 181         break;
 182     case IPR32 ... IPR39:
 183         s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
 184         break;
 185     default:
 186         printf("%s: Bad register offset " REG_FMT "\n", __FUNCTION__, offset);
 187         return;
 188     }
 189     pxa2xx_pic_update(opaque);
 190 }
 191
 192 /* Interrupt Controller Coprocessor Space Register Mapping */
 193 static const int pxa2xx_cp_reg_map[0x10] = {
 194     [0x0 ... 0xf] = -1,
 195     [0x0] = ICIP,
 196     [0x1] = ICMR,
 197     [0x2] = ICLR,
 198     [0x3] = ICFP,
 199     [0x4] = ICPR,
 200     [0x5] = ICHP,
 201     [0x6] = ICIP2,
 202     [0x7] = ICMR2,
 203     [0x8] = ICLR2,
 204     [0x9] = ICFP2,
 205     [0xa] = ICPR2,
 206 };
 207
 208 static uint32_t pxa2xx_pic_cp_read(void *opaque, int op2, int reg, int crm)
 209 {
 210     struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
 211     target_phys_addr_t offset;
 212
 213     if (pxa2xx_cp_reg_map[reg] == -1) {
 214         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
 215         return 0;
 216     }
 217
 218     offset = s->base + pxa2xx_cp_reg_map[reg];
 219     return pxa2xx_pic_mem_read(opaque, offset);
 220 }
 221
 222 static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,
 223                 uint32_t value)
 224 {
 225     struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
 226     target_phys_addr_t offset;
 227
 228     if (pxa2xx_cp_reg_map[reg] == -1) {
 229         printf("%s: Bad register 0x%x\n", __FUNCTION__, reg);
 230         return;
 231     }
 232
 233     offset = s->base + pxa2xx_cp_reg_map[reg];
 234     pxa2xx_pic_mem_write(opaque, offset, value);
 235 }
 236
 237 static CPUReadMemoryFunc *pxa2xx_pic_readfn[] = {
 238     pxa2xx_pic_mem_read,
 239     pxa2xx_pic_mem_read,
 240     pxa2xx_pic_mem_read,
 241 };
 242
 243 static CPUWriteMemoryFunc *pxa2xx_pic_writefn[] = {
 244     pxa2xx_pic_mem_write,
 245     pxa2xx_pic_mem_write,
 246     pxa2xx_pic_mem_write,
 247 };
 248
 249 static void pxa2xx_pic_save(QEMUFile *f, void *opaque)
 250 {
 251     struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
 252     int i;
 253
 254     for (i = 0; i < 2; i ++)
 255         qemu_put_be32s(f, &s->int_enabled[i]);
 256     for (i = 0; i < 2; i ++)
 257         qemu_put_be32s(f, &s->int_pending[i]);
 258     for (i = 0; i < 2; i ++)
 259         qemu_put_be32s(f, &s->is_fiq[i]);
 260     qemu_put_be32s(f, &s->int_idle);
 261     for (i = 0; i < PXA2XX_PIC_SRCS; i ++)
 262         qemu_put_be32s(f, &s->priority[i]);
 263 }
 264
 265 static int pxa2xx_pic_load(QEMUFile *f, void *opaque, int version_id)
 266 {
 267     struct pxa2xx_pic_state_s *s = (struct pxa2xx_pic_state_s *) opaque;
 268     int i;
 269
 270     for (i = 0; i < 2; i ++)
 271         qemu_get_be32s(f, &s->int_enabled[i]);
 272     for (i = 0; i < 2; i ++)
 273         qemu_get_be32s(f, &s->int_pending[i]);
 274     for (i = 0; i < 2; i ++)
 275         qemu_get_be32s(f, &s->is_fiq[i]);
 276     qemu_get_be32s(f, &s->int_idle);
 277     for (i = 0; i < PXA2XX_PIC_SRCS; i ++)
 278         qemu_get_be32s(f, &s->priority[i]);
 279
 280     pxa2xx_pic_update(opaque);
 281     return 0;
 282 }
 283
 284 qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
 285 {
 286     struct pxa2xx_pic_state_s *s;
 287     int iomemtype;
 288     qemu_irq *qi;
 289
 290     s = (struct pxa2xx_pic_state_s *)
 291             qemu_mallocz(sizeof(struct pxa2xx_pic_state_s));
 292     if (!s)
 293         return NULL;
 294
 295     s->cpu_env = env;
 296     s->base = base;
 297
 298     s->int_pending[0] = 0;
 299     s->int_pending[1] = 0;
 300     s->int_enabled[0] = 0;
 301     s->int_enabled[1] = 0;
 302     s->is_fiq[0] = 0;
 303     s->is_fiq[1] = 0;
 304
 305     qi = qemu_allocate_irqs(pxa2xx_pic_set_irq, s, PXA2XX_PIC_SRCS);
 306
 307     /* Enable IC memory-mapped registers access.  */
 308     iomemtype = cpu_register_io_memory(0, pxa2xx_pic_readfn,
 309                     pxa2xx_pic_writefn, s);
 310     cpu_register_physical_memory(base, 0x00100000, iomemtype);
 311
 312     /* Enable IC coprocessor access.  */
 313     cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
 314
 315     register_savevm("pxa2xx_pic", 0, 0, pxa2xx_pic_save, pxa2xx_pic_load, s);
 316
 317     return qi;
 318 }