qemu/hw/slavio_intctl.c

   1 /*
   2  * QEMU Sparc SLAVIO interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "sun4m.h"
  26 #include "console.h"
  27
  28 //#define DEBUG_IRQ_COUNT
  29 //#define DEBUG_IRQ
  30
  31 #ifdef DEBUG_IRQ
  32 #define DPRINTF(fmt, args...) \
  33 do { printf("IRQ: " fmt , ##args); } while (0)
  34 #else
  35 #define DPRINTF(fmt, args...)
  36 #endif
  37
  38 /*
  39  * Registers of interrupt controller in sun4m.
  40  *
  41  * This is the interrupt controller part of chip STP2001 (Slave I/O), also
  42  * produced as NCR89C105. See
  43  * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
  44  *
  45  * There is a system master controller and one for each cpu.
  46  *
  47  */
  48
  49 #define MAX_CPUS 16
  50 #define MAX_PILS 16
  51
  52 typedef struct SLAVIO_INTCTLState {
  53     uint32_t intreg_pending[MAX_CPUS];
  54     uint32_t intregm_pending;
  55     uint32_t intregm_disabled;
  56     uint32_t target_cpu;
  57 #ifdef DEBUG_IRQ_COUNT
  58     uint64_t irq_count[32];
  59 #endif
  60     qemu_irq *cpu_irqs[MAX_CPUS];
  61     const uint32_t *intbit_to_level;
  62     uint32_t cputimer_lbit, cputimer_mbit;
  63     uint32_t pil_out[MAX_CPUS];
  64 } SLAVIO_INTCTLState;
  65
  66 #define INTCTL_MAXADDR 0xf
  67 #define INTCTL_SIZE (INTCTL_MAXADDR + 1)
  68 #define INTCTLM_MAXADDR 0x13
  69 #define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
  70 #define INTCTLM_MASK 0x1f
  71 #define MASTER_IRQ_MASK ~0x0fa2007f
  72 #define MASTER_DISABLE 0x80000000
  73 #define CPU_SOFTIRQ_MASK 0xfffe0000
  74 #define CPU_HARDIRQ_MASK 0x0000fffe
  75 #define CPU_IRQ_INT15_IN 0x0004000
  76 #define CPU_IRQ_INT15_MASK 0x80000000
  77
  78 static void slavio_check_interrupts(void *opaque);
  79
  80 // per-cpu interrupt controller
  81 static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
  82 {
  83     SLAVIO_INTCTLState *s = opaque;
  84     uint32_t saddr, ret;
  85     int cpu;
  86
  87     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
  88     saddr = (addr & INTCTL_MAXADDR) >> 2;
  89     switch (saddr) {
  90     case 0:
  91         ret = s->intreg_pending[cpu];
  92         break;
  93     default:
  94         ret = 0;
  95         break;
  96     }
  97     DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret);
  98
  99     return ret;
 100 }
 101
 102 static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr,
 103                                      uint32_t val)
 104 {
 105     SLAVIO_INTCTLState *s = opaque;
 106     uint32_t saddr;
 107     int cpu;
 108
 109     cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
 110     saddr = (addr & INTCTL_MAXADDR) >> 2;
 111     DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
 112     switch (saddr) {
 113     case 1: // clear pending softints
 114         if (val & CPU_IRQ_INT15_IN)
 115             val |= CPU_IRQ_INT15_MASK;
 116         val &= CPU_SOFTIRQ_MASK;
 117         s->intreg_pending[cpu] &= ~val;
 118         slavio_check_interrupts(s);
 119         DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val,
 120                 s->intreg_pending[cpu]);
 121         break;
 122     case 2: // set softint
 123         val &= CPU_SOFTIRQ_MASK;
 124         s->intreg_pending[cpu] |= val;
 125         slavio_check_interrupts(s);
 126         DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val,
 127                 s->intreg_pending[cpu]);
 128         break;
 129     default:
 130         break;
 131     }
 132 }
 133
 134 static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
 135     NULL,
 136     NULL,
 137     slavio_intctl_mem_readl,
 138 };
 139
 140 static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
 141     NULL,
 142     NULL,
 143     slavio_intctl_mem_writel,
 144 };
 145
 146 // master system interrupt controller
 147 static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
 148 {
 149     SLAVIO_INTCTLState *s = opaque;
 150     uint32_t saddr, ret;
 151
 152     saddr = (addr & INTCTLM_MASK) >> 2;
 153     switch (saddr) {
 154     case 0:
 155         ret = s->intregm_pending & ~MASTER_DISABLE;
 156         break;
 157     case 1:
 158         ret = s->intregm_disabled & MASTER_IRQ_MASK;
 159         break;
 160     case 4:
 161         ret = s->target_cpu;
 162         break;
 163     default:
 164         ret = 0;
 165         break;
 166     }
 167     DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
 168
 169     return ret;
 170 }
 171
 172 static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr,
 173                                       uint32_t val)
 174 {
 175     SLAVIO_INTCTLState *s = opaque;
 176     uint32_t saddr;
 177
 178     saddr = (addr & INTCTLM_MASK) >> 2;
 179     DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
 180     switch (saddr) {
 181     case 2: // clear (enable)
 182         // Force clear unused bits
 183         val &= MASTER_IRQ_MASK;
 184         s->intregm_disabled &= ~val;
 185         DPRINTF("Enabled master irq mask %x, curmask %x\n", val,
 186                 s->intregm_disabled);
 187         slavio_check_interrupts(s);
 188         break;
 189     case 3: // set (disable, clear pending)
 190         // Force clear unused bits
 191         val &= MASTER_IRQ_MASK;
 192         s->intregm_disabled |= val;
 193         s->intregm_pending &= ~val;
 194         slavio_check_interrupts(s);
 195         DPRINTF("Disabled master irq mask %x, curmask %x\n", val,
 196                 s->intregm_disabled);
 197         break;
 198     case 4:
 199         s->target_cpu = val & (MAX_CPUS - 1);
 200         slavio_check_interrupts(s);
 201         DPRINTF("Set master irq cpu %d\n", s->target_cpu);
 202         break;
 203     default:
 204         break;
 205     }
 206 }
 207
 208 static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
 209     NULL,
 210     NULL,
 211     slavio_intctlm_mem_readl,
 212 };
 213
 214 static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
 215     NULL,
 216     NULL,
 217     slavio_intctlm_mem_writel,
 218 };
 219
 220 void slavio_pic_info(void *opaque)
 221 {
 222     SLAVIO_INTCTLState *s = opaque;
 223     int i;
 224
 225     for (i = 0; i < MAX_CPUS; i++) {
 226         term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
 227     }
 228     term_printf("master: pending 0x%08x, disabled 0x%08x\n",
 229                 s->intregm_pending, s->intregm_disabled);
 230 }
 231
 232 void slavio_irq_info(void *opaque)
 233 {
 234 #ifndef DEBUG_IRQ_COUNT
 235     term_printf("irq statistic code not compiled.\n");
 236 #else
 237     SLAVIO_INTCTLState *s = opaque;
 238     int i;
 239     int64_t count;
 240
 241     term_printf("IRQ statistics:\n");
 242     for (i = 0; i < 32; i++) {
 243         count = s->irq_count[i];
 244         if (count > 0)
 245             term_printf("%2d: %" PRId64 "\n", i, count);
 246     }
 247 #endif
 248 }
 249
 250 static void slavio_check_interrupts(void *opaque)
 251 {
 252     SLAVIO_INTCTLState *s = opaque;
 253     uint32_t pending = s->intregm_pending, pil_pending;
 254     unsigned int i, j;
 255
 256     pending &= ~s->intregm_disabled;
 257
 258     DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
 259     for (i = 0; i < MAX_CPUS; i++) {
 260         pil_pending = 0;
 261         if (pending && !(s->intregm_disabled & MASTER_DISABLE) &&
 262             (i == s->target_cpu)) {
 263             for (j = 0; j < 32; j++) {
 264                 if (pending & (1 << j))
 265                     pil_pending |= 1 << s->intbit_to_level[j];
 266             }
 267         }
 268         pil_pending |= (s->intreg_pending[i] & CPU_SOFTIRQ_MASK) >> 16;
 269
 270         for (j = 0; j < MAX_PILS; j++) {
 271             if (pil_pending & (1 << j)) {
 272                 if (!(s->pil_out[i] & (1 << j)))
 273                     qemu_irq_raise(s->cpu_irqs[i][j]);
 274             } else {
 275                 if (s->pil_out[i] & (1 << j))
 276                     qemu_irq_lower(s->cpu_irqs[i][j]);
 277             }
 278         }
 279         s->pil_out[i] = pil_pending;
 280     }
 281 }
 282
 283 /*
 284  * "irq" here is the bit number in the system interrupt register to
 285  * separate serial and keyboard interrupts sharing a level.
 286  */
 287 static void slavio_set_irq(void *opaque, int irq, int level)
 288 {
 289     SLAVIO_INTCTLState *s = opaque;
 290     uint32_t mask = 1 << irq;
 291     uint32_t pil = s->intbit_to_level[irq];
 292
 293     DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
 294             level);
 295     if (pil > 0) {
 296         if (level) {
 297 #ifdef DEBUG_IRQ_COUNT
 298             s->irq_count[pil]++;
 299 #endif
 300             s->intregm_pending |= mask;
 301             s->intreg_pending[s->target_cpu] |= 1 << pil;
 302         } else {
 303             s->intregm_pending &= ~mask;
 304             s->intreg_pending[s->target_cpu] &= ~(1 << pil);
 305         }
 306         slavio_check_interrupts(s);
 307     }
 308 }
 309
 310 static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
 311 {
 312     SLAVIO_INTCTLState *s = opaque;
 313
 314     DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
 315
 316     if (level) {
 317         s->intregm_pending |= s->cputimer_mbit;
 318         s->intreg_pending[cpu] |= s->cputimer_lbit;
 319     } else {
 320         s->intregm_pending &= ~s->cputimer_mbit;
 321         s->intreg_pending[cpu] &= ~s->cputimer_lbit;
 322     }
 323
 324     slavio_check_interrupts(s);
 325 }
 326
 327 static void slavio_intctl_save(QEMUFile *f, void *opaque)
 328 {
 329     SLAVIO_INTCTLState *s = opaque;
 330     int i;
 331
 332     for (i = 0; i < MAX_CPUS; i++) {
 333         qemu_put_be32s(f, &s->intreg_pending[i]);
 334     }
 335     qemu_put_be32s(f, &s->intregm_pending);
 336     qemu_put_be32s(f, &s->intregm_disabled);
 337     qemu_put_be32s(f, &s->target_cpu);
 338 }
 339
 340 static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
 341 {
 342     SLAVIO_INTCTLState *s = opaque;
 343     int i;
 344
 345     if (version_id != 1)
 346         return -EINVAL;
 347
 348     for (i = 0; i < MAX_CPUS; i++) {
 349         qemu_get_be32s(f, &s->intreg_pending[i]);
 350     }
 351     qemu_get_be32s(f, &s->intregm_pending);
 352     qemu_get_be32s(f, &s->intregm_disabled);
 353     qemu_get_be32s(f, &s->target_cpu);
 354     slavio_check_interrupts(s);
 355     return 0;
 356 }
 357
 358 static void slavio_intctl_reset(void *opaque)
 359 {
 360     SLAVIO_INTCTLState *s = opaque;
 361     int i;
 362
 363     for (i = 0; i < MAX_CPUS; i++) {
 364         s->intreg_pending[i] = 0;
 365     }
 366     s->intregm_disabled = ~MASTER_IRQ_MASK;
 367     s->intregm_pending = 0;
 368     s->target_cpu = 0;
 369     slavio_check_interrupts(s);
 370 }
 371
 372 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
 373                          const uint32_t *intbit_to_level,
 374                          qemu_irq **irq, qemu_irq **cpu_irq,
 375                          qemu_irq **parent_irq, unsigned int cputimer)
 376 {
 377     int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
 378     SLAVIO_INTCTLState *s;
 379
 380     s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
 381     if (!s)
 382         return NULL;
 383
 384     s->intbit_to_level = intbit_to_level;
 385     for (i = 0; i < MAX_CPUS; i++) {
 386         slavio_intctl_io_memory = cpu_register_io_memory(0,
 387                                                          slavio_intctl_mem_read,
 388                                                          slavio_intctl_mem_write,
 389                                                          s);
 390         cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
 391                                      slavio_intctl_io_memory);
 392         s->cpu_irqs[i] = parent_irq[i];
 393     }
 394
 395     slavio_intctlm_io_memory = cpu_register_io_memory(0,
 396                                                       slavio_intctlm_mem_read,
 397                                                       slavio_intctlm_mem_write,
 398                                                       s);
 399     cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
 400
 401     register_savevm("slavio_intctl", addr, 1, slavio_intctl_save,
 402                     slavio_intctl_load, s);
 403     qemu_register_reset(slavio_intctl_reset, s);
 404     *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
 405
 406     *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
 407     s->cputimer_mbit = 1 << cputimer;
 408     s->cputimer_lbit = 1 << intbit_to_level[cputimer];
 409     slavio_intctl_reset(s);
 410     return s;
 411 }
 412