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kvm: qemu: fix pci_enable_capabilities to set the CAP feature in pci::status
[kvm-userspace.git] / bios / rombios32.c
blob4dea066e2b2146d3498b5780579198d949c1b1a2
1 /////////////////////////////////////////////////////////////////////////
2 // $Id: rombios32.c,v 1.11 2007/08/03 13:56:13 vruppert Exp $
3 /////////////////////////////////////////////////////////////////////////
4 //
5 // 32 bit Bochs BIOS init code
6 // Copyright (C) 2006 Fabrice Bellard
7 //
8 // This library is free software; you can redistribute it and/or
9 // modify it under the terms of the GNU Lesser General Public
10 // License as published by the Free Software Foundation; either
11 // version 2 of the License, or (at your option) any later version.
12 //
13 // This library is distributed in the hope that it will be useful,
14 // but WITHOUT ANY WARRANTY; without even the implied warranty of
15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 // Lesser General Public License for more details.
17 //
18 // You should have received a copy of the GNU Lesser General Public
19 // License along with this library; if not, write to the Free Software
20 // Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
21 #include <stdarg.h>
22 #include <stddef.h>
23
24 #include "rombios.h"
25
26 typedef signed char int8_t;
27 typedef short int16_t;
28 typedef int int32_t;
29 typedef long long int64_t;
30 typedef unsigned char uint8_t;
31 typedef unsigned short uint16_t;
32 typedef unsigned int uint32_t;
33 typedef unsigned long long uint64_t;
34
35 /* if true, put the MP float table and ACPI RSDT in EBDA and the MP
36 table in RAM. Unfortunately, Linux has bugs with that, so we prefer
37 to modify the BIOS in shadow RAM */
38 //#define BX_USE_EBDA_TABLES
39
40 /* define it if the (emulated) hardware supports SMM mode */
41 //#define BX_USE_SMM
42
43 #define cpuid(index, eax, ebx, ecx, edx) \
44 asm volatile ("cpuid" \
45 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
46 : "0" (index))
47
48 #define wbinvd() asm volatile("wbinvd")
49
50 #define CPUID_APIC (1 << 9)
51
52 #define APIC_BASE ((uint8_t *)0xfee00000)
53 #define APIC_ICR_LOW 0x300
54 #define APIC_SVR 0x0F0
55 #define APIC_ID 0x020
56 #define APIC_LVT3 0x370
57
58 /* IRQs 5,9,10,11 */
59 #define PCI_ISA_IRQ_MASK 0x0e20U
60
61 #define APIC_ENABLED 0x0100
62
63 #define AP_BOOT_ADDR 0x9f000
64
65 #define MPTABLE_MAX_SIZE 0x00002000
66 #define SMI_CMD_IO_ADDR 0xb2
67
68 #define BIOS_TMP_STORAGE 0x00030000 /* 64 KB used to copy the BIOS to shadow RAM */
69
70 #define MSR_MTRRcap 0x000000fe
71 #define MSR_MTRRfix64K_00000 0x00000250
72 #define MSR_MTRRfix16K_80000 0x00000258
73 #define MSR_MTRRfix16K_A0000 0x00000259
74 #define MSR_MTRRfix4K_C0000 0x00000268
75 #define MSR_MTRRfix4K_C8000 0x00000269
76 #define MSR_MTRRfix4K_D0000 0x0000026a
77 #define MSR_MTRRfix4K_D8000 0x0000026b
78 #define MSR_MTRRfix4K_E0000 0x0000026c
79 #define MSR_MTRRfix4K_E8000 0x0000026d
80 #define MSR_MTRRfix4K_F0000 0x0000026e
81 #define MSR_MTRRfix4K_F8000 0x0000026f
82 #define MSR_MTRRdefType 0x000002ff
83
84 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
85 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
86
87 static inline void outl(int addr, int val)
88 {
89 asm volatile ("outl %1, %w0" : : "d" (addr), "a" (val));
90 }
91
92 static inline void outw(int addr, int val)
93 {
94 asm volatile ("outw %w1, %w0" : : "d" (addr), "a" (val));
95 }
96
97 static inline void outb(int addr, int val)
98 {
99 asm volatile ("outb %b1, %w0" : : "d" (addr), "a" (val));
100 }
101
102 static inline uint32_t inl(int addr)
103 {
104 uint32_t val;
105 asm volatile ("inl %w1, %0" : "=a" (val) : "d" (addr));
106 return val;
107 }
108
109 static inline uint16_t inw(int addr)
110 {
111 uint16_t val;
112 asm volatile ("inw %w1, %w0" : "=a" (val) : "d" (addr));
113 return val;
114 }
115
116 static inline uint8_t inb(int addr)
117 {
118 uint8_t val;
119 asm volatile ("inb %w1, %b0" : "=a" (val) : "d" (addr));
120 return val;
121 }
122
123 static inline void writel(void *addr, uint32_t val)
124 {
125 *(volatile uint32_t *)addr = val;
126 }
127
128 static inline void writew(void *addr, uint16_t val)
129 {
130 *(volatile uint16_t *)addr = val;
131 }
132
133 static inline void writeb(void *addr, uint8_t val)
134 {
135 *(volatile uint8_t *)addr = val;
136 }
137
138 static inline uint32_t readl(const void *addr)
139 {
140 return *(volatile const uint32_t *)addr;
141 }
142
143 static inline uint16_t readw(const void *addr)
144 {
145 return *(volatile const uint16_t *)addr;
146 }
147
148 static inline uint8_t readb(const void *addr)
149 {
150 return *(volatile const uint8_t *)addr;
151 }
152
153 static inline void putc(int c)
154 {
155 outb(INFO_PORT, c);
156 }
157
158 static uint64_t rdmsr(unsigned index)
159 {
160 unsigned long long ret;
161
162 asm ("rdmsr" : "=A"(ret) : "c"(index));
163 return ret;
164 }
165
166 static void wrmsr(unsigned index, uint64_t val)
167 {
168 asm volatile ("wrmsr" : : "c"(index), "A"(val));
169 }
170
171 static inline int isdigit(int c)
172 {
173 return c >= '0' && c <= '9';
174 }
175
176 void *memset(void *d1, int val, size_t len)
177 {
178 uint8_t *d = d1;
179
180 while (len--) {
181 *d++ = val;
182 }
183 return d1;
184 }
185
186 void *memcpy(void *d1, const void *s1, size_t len)
187 {
188 uint8_t *d = d1;
189 const uint8_t *s = s1;
190
191 while (len--) {
192 *d++ = *s++;
193 }
194 return d1;
195 }
196
197 void *memmove(void *d1, const void *s1, size_t len)
198 {
199 uint8_t *d = d1;
200 const uint8_t *s = s1;
201
202 if (d <= s) {
203 while (len--) {
204 *d++ = *s++;
205 }
206 } else {
207 d += len;
208 s += len;
209 while (len--) {
210 *--d = *--s;
211 }
212 }
213 return d1;
214 }
215
216 int memcmp(const void *s1, const void *s2, size_t len)
217 {
218 const int8_t *p1 = s1;
219 const int8_t *p2 = s2;
220
221 while (len--) {
222 int r = *p1++ - *p2++;
223 if(r)
224 return r;
225 }
226
227 return 0;
228 }
229
230 size_t strlen(const char *s)
231 {
232 const char *s1;
233 for(s1 = s; *s1 != '\0'; s1++);
234 return s1 - s;
235 }
236
237 /* from BSD ppp sources */
238 int vsnprintf(char *buf, int buflen, const char *fmt, va_list args)
239 {
240 int c, i, n;
241 int width, prec, fillch;
242 int base, len, neg;
243 unsigned long val = 0;
244 const char *f;
245 char *str, *buf0;
246 char num[32];
247 static const char hexchars[] = "0123456789abcdef";
248
249 buf0 = buf;
250 --buflen;
251 while (buflen > 0) {
252 for (f = fmt; *f != '%' && *f != 0; ++f)
253 ;
254 if (f > fmt) {
255 len = f - fmt;
256 if (len > buflen)
257 len = buflen;
258 memcpy(buf, fmt, len);
259 buf += len;
260 buflen -= len;
261 fmt = f;
262 }
263 if (*fmt == 0)
264 break;
265 c = *++fmt;
266 width = prec = 0;
267 fillch = ' ';
268 if (c == '0') {
269 fillch = '0';
270 c = *++fmt;
271 }
272 if (c == '*') {
273 width = va_arg(args, int);
274 c = *++fmt;
275 } else {
276 while (isdigit(c)) {
277 width = width * 10 + c - '0';
278 c = *++fmt;
279 }
280 }
281 if (c == '.') {
282 c = *++fmt;
283 if (c == '*') {
284 prec = va_arg(args, int);
285 c = *++fmt;
286 } else {
287 while (isdigit(c)) {
288 prec = prec * 10 + c - '0';
289 c = *++fmt;
290 }
291 }
292 }
293 /* modifiers */
294 switch(c) {
295 case 'l':
296 c = *++fmt;
297 break;
298 default:
299 break;
300 }
301 str = 0;
302 base = 0;
303 neg = 0;
304 ++fmt;
305 switch (c) {
306 case 'd':
307 i = va_arg(args, int);
308 if (i < 0) {
309 neg = 1;
310 val = -i;
311 } else
312 val = i;
313 base = 10;
314 break;
315 case 'o':
316 val = va_arg(args, unsigned int);
317 base = 8;
318 break;
319 case 'x':
320 case 'X':
321 val = va_arg(args, unsigned int);
322 base = 16;
323 break;
324 case 'p':
325 val = (unsigned long) va_arg(args, void *);
326 base = 16;
327 neg = 2;
328 break;
329 case 's':
330 str = va_arg(args, char *);
331 break;
332 case 'c':
333 num[0] = va_arg(args, int);
334 num[1] = 0;
335 str = num;
336 break;
337 default:
338 *buf++ = '%';
339 if (c != '%')
340 --fmt; /* so %z outputs %z etc. */
341 --buflen;
342 continue;
343 }
344 if (base != 0) {
345 str = num + sizeof(num);
346 *--str = 0;
347 while (str > num + neg) {
348 *--str = hexchars[val % base];
349 val = val / base;
350 if (--prec <= 0 && val == 0)
351 break;
352 }
353 switch (neg) {
354 case 1:
355 *--str = '-';
356 break;
357 case 2:
358 *--str = 'x';
359 *--str = '0';
360 break;
361 }
362 len = num + sizeof(num) - 1 - str;
363 } else {
364 len = strlen(str);
365 if (prec > 0 && len > prec)
366 len = prec;
367 }
368 if (width > 0) {
369 if (width > buflen)
370 width = buflen;
371 if ((n = width - len) > 0) {
372 buflen -= n;
373 for (; n > 0; --n)
374 *buf++ = fillch;
375 }
376 }
377 if (len > buflen)
378 len = buflen;
379 memcpy(buf, str, len);
380 buf += len;
381 buflen -= len;
382 }
383 *buf = 0;
384 return buf - buf0;
385 }
386
387 int snprintf(char * buf, size_t size, const char *fmt, ...)
388 {
389 va_list args;
390 int i;
391
392 va_start(args, fmt);
393 i=vsnprintf(buf,size,fmt,args);
394 va_end(args);
395 return i;
396 }
397
398 void bios_printf(int flags, const char *fmt, ...)
399 {
400 va_list ap;
401 char buf[1024];
402 const char *s;
403
404 if ((flags & BIOS_PRINTF_DEBHALT) == BIOS_PRINTF_DEBHALT)
405 outb(PANIC_PORT2, 0x00);
406
407 va_start(ap, fmt);
408 vsnprintf(buf, sizeof(buf), fmt, ap);
409 s = buf;
410 while (*s)
411 putc(*s++);
412 va_end(ap);
413 }
414
415 void delay_ms(int n)
416 {
417 int i, j;
418 for(i = 0; i < n; i++) {
419 #ifdef BX_QEMU
420 /* approximative ! */
421 for(j = 0; j < 1000000; j++);
422 #else
423 {
424 int r1, r2;
425 j = 66;
426 r1 = inb(0x61) & 0x10;
427 do {
428 r2 = inb(0x61) & 0x10;
429 if (r1 != r2) {
430 j--;
431 r1 = r2;
432 }
433 } while (j > 0);
434 }
435 #endif
436 }
437 }
438
439 uint16_t smp_cpus;
440 uint32_t cpuid_signature;
441 uint32_t cpuid_features;
442 uint32_t cpuid_ext_features;
443 unsigned long ram_size;
444 uint64_t ram_end;
445 uint8_t bios_uuid[16];
446 #ifdef BX_USE_EBDA_TABLES
447 unsigned long ebda_cur_addr;
448 #endif
449 int acpi_enabled;
450 uint32_t pm_io_base, smb_io_base;
451 int pm_sci_int;
452 unsigned long bios_table_cur_addr;
453 unsigned long bios_table_end_addr;
454
455 void init_smp_msrs(void)
456 {
457 *(uint32_t *)SMP_MSR_ADDR = 0;
458 }
459
460 void wrmsr_smp(uint32_t index, uint64_t val)
461 {
462 static struct { uint32_t ecx, eax, edx; } *p = (void *)SMP_MSR_ADDR;
463
464 wrmsr(index, val);
465 p->ecx = index;
466 p->eax = val;
467 p->edx = val >> 32;
468 ++p;
469 p->ecx = 0;
470 }
471
472 #ifdef BX_QEMU
473 #define QEMU_CFG_CTL_PORT 0x510
474 #define QEMU_CFG_DATA_PORT 0x511
475 #define QEMU_CFG_SIGNATURE 0x00
476 #define QEMU_CFG_ID 0x01
477 #define QEMU_CFG_UUID 0x02
478
479 int qemu_cfg_port;
480
481 void qemu_cfg_select(int f)
482 {
483 outw(QEMU_CFG_CTL_PORT, f);
484 }
485
486 int qemu_cfg_port_probe()
487 {
488 char *sig = "QEMU";
489 int i;
490
491 qemu_cfg_select(QEMU_CFG_SIGNATURE);
492
493 for (i = 0; i < 4; i++)
494 if (inb(QEMU_CFG_DATA_PORT) != sig[i])
495 return 0;
496
497 return 1;
498 }
499
500 void qemu_cfg_read(uint8_t *buf, int len)
501 {
502 while (len--)
503 *(buf++) = inb(QEMU_CFG_DATA_PORT);
504 }
505 #endif
506
507 void uuid_probe(void)
508 {
509 #ifdef BX_QEMU
510 if(qemu_cfg_port) {
511 qemu_cfg_select(QEMU_CFG_UUID);
512 qemu_cfg_read(bios_uuid, 16);
513 return;
514 }
515 #endif
516 memset(bios_uuid, 0, 16);
517 }
518
519 void cpu_probe(void)
520 {
521 uint32_t eax, ebx, ecx, edx;
522 cpuid(1, eax, ebx, ecx, edx);
523 cpuid_signature = eax;
524 cpuid_features = edx;
525 cpuid_ext_features = ecx;
526 }
527
528 static int cmos_readb(int addr)
529 {
530 outb(0x70, addr);
531 return inb(0x71);
532 }
533
534 void setup_mtrr(void)
535 {
536 int i, vcnt, fix, wc;
537 uint32_t mtrr_cap;
538 union {
539 uint8_t valb[8];
540 uint64_t val;
541 } u;
542
543 mtrr_cap = rdmsr(MSR_MTRRcap);
544 vcnt = mtrr_cap & 0xff;
545 fix = mtrr_cap & 0x100;
546 wc = mtrr_cap & 0x400;
547 if (!vcnt || !fix)
548 return;
549 u.val = 0;
550 for (i = 0; i < 8; ++i)
551 if (ram_size >= 65536 * (i + 1))
552 u.valb[i] = 6;
553 wrmsr_smp(MSR_MTRRfix64K_00000, u.val);
554 u.val = 0;
555 for (i = 0; i < 8; ++i)
556 if (ram_size >= 65536 * 8 + 16384 * (i + 1))
557 u.valb[i] = 6;
558 wrmsr_smp(MSR_MTRRfix16K_80000, u.val);
559 wrmsr_smp(MSR_MTRRfix16K_A0000, 0);
560 wrmsr_smp(MSR_MTRRfix4K_C0000, 0);
561 wrmsr_smp(MSR_MTRRfix4K_C8000, 0);
562 wrmsr_smp(MSR_MTRRfix4K_D0000, 0);
563 wrmsr_smp(MSR_MTRRfix4K_D8000, 0);
564 wrmsr_smp(MSR_MTRRfix4K_E0000, 0);
565 wrmsr_smp(MSR_MTRRfix4K_E8000, 0);
566 wrmsr_smp(MSR_MTRRfix4K_F0000, 0);
567 wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
568 /* Mark 3.5-4GB as UC, anything not specified defaults to WB */
569 wrmsr_smp(MTRRphysBase_MSR(0), 0xe0000000ull | 0);
570 wrmsr_smp(MTRRphysMask_MSR(0), ~(0x20000000ull - 1) | 0x800);
571 wrmsr_smp(MSR_MTRRdefType, 0xc06);
572 }
573
574 void ram_probe(void)
575 {
576 if (cmos_readb(0x34) | cmos_readb(0x35))
577 ram_size = (cmos_readb(0x34) | (cmos_readb(0x35) << 8)) * 65536 +
578 16 * 1024 * 1024;
579 else
580 ram_size = (cmos_readb(0x17) | (cmos_readb(0x18) << 8)) * 1024;
581
582 if (cmos_readb(0x5b) | cmos_readb(0x5c) | cmos_readb(0x5d))
583 ram_end = (((uint64_t)cmos_readb(0x5b) << 16) |
584 ((uint64_t)cmos_readb(0x5c) << 24) |
585 ((uint64_t)cmos_readb(0x5d) << 32)) + (1ull << 32);
586 else
587 ram_end = ram_size;
588
589 BX_INFO("end of ram=%ldMB\n", ram_end >> 20);
590
591 BX_INFO("ram_size=0x%08lx\n", ram_size);
592 #ifdef BX_USE_EBDA_TABLES
593 ebda_cur_addr = ((*(uint16_t *)(0x40e)) << 4) + 0x380;
594 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
595 #endif
596 setup_mtrr();
597 }
598
599 /****************************************************/
600 /* SMP probe */
601
602 extern uint8_t smp_ap_boot_code_start;
603 extern uint8_t smp_ap_boot_code_end;
604
605 /* find the number of CPUs by launching a SIPI to them */
606 void smp_probe(void)
607 {
608 uint32_t val, sipi_vector;
609
610 writew(&smp_cpus, 1);
611 if (cpuid_features & CPUID_APIC) {
612
613 /* enable local APIC */
614 val = readl(APIC_BASE + APIC_SVR);
615 val |= APIC_ENABLED;
616 writel(APIC_BASE + APIC_SVR, val);
617
618 /* copy AP boot code */
619 memcpy((void *)AP_BOOT_ADDR, &smp_ap_boot_code_start,
620 &smp_ap_boot_code_end - &smp_ap_boot_code_start);
621
622 /* broadcast SIPI */
623 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4500);
624 sipi_vector = AP_BOOT_ADDR >> 12;
625 writel(APIC_BASE + APIC_ICR_LOW, 0x000C4600 | sipi_vector);
626
627 #ifndef BX_QEMU
628 delay_ms(10);
629 #else
630 while (cmos_readb(0x5f) + 1 != readw(&smp_cpus))
631 ;
632 #endif
633 }
634 BX_INFO("Found %d cpu(s)\n", readw(&smp_cpus));
635 }
636
637 /****************************************************/
638 /* PCI init */
639
640 #define PCI_ADDRESS_SPACE_MEM 0x00
641 #define PCI_ADDRESS_SPACE_IO 0x01
642 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
643
644 #define PCI_ROM_SLOT 6
645 #define PCI_NUM_REGIONS 7
646
647 #define PCI_DEVICES_MAX 64
648
649 #define PCI_VENDOR_ID 0x00 /* 16 bits */
650 #define PCI_DEVICE_ID 0x02 /* 16 bits */
651 #define PCI_COMMAND 0x04 /* 16 bits */
652 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
653 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
654 #define PCI_CLASS_DEVICE 0x0a /* Device class */
655 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
656 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
657 #define PCI_MIN_GNT 0x3e /* 8 bits */
658 #define PCI_MAX_LAT 0x3f /* 8 bits */
659
660 #define PCI_VENDOR_ID_INTEL 0x8086
661 #define PCI_DEVICE_ID_INTEL_82441 0x1237
662 #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000
663 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010
664 #define PCI_DEVICE_ID_INTEL_82371AB_0 0x7110
665 #define PCI_DEVICE_ID_INTEL_82371AB 0x7111
666 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113
667
668 #define PCI_VENDOR_ID_IBM 0x1014
669 #define PCI_VENDOR_ID_APPLE 0x106b
670
671 typedef struct PCIDevice {
672 int bus;
673 int devfn;
674 } PCIDevice;
675
676 static uint32_t pci_bios_io_addr;
677 static uint32_t pci_bios_mem_addr;
678 static uint32_t pci_bios_bigmem_addr;
679 /* host irqs corresponding to PCI irqs A-D */
680 static uint8_t pci_irqs[4] = { 10, 10, 11, 11 };
681 static PCIDevice i440_pcidev;
682
683 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
684 {
685 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
686 outl(0xcfc, val);
687 }
688
689 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
690 {
691 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
692 outw(0xcfc + (addr & 2), val);
693 }
694
695 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
696 {
697 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
698 outb(0xcfc + (addr & 3), val);
699 }
700
701 static uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
702 {
703 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
704 return inl(0xcfc);
705 }
706
707 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
708 {
709 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
710 return inw(0xcfc + (addr & 2));
711 }
712
713 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
714 {
715 outl(0xcf8, 0x80000000 | (d->bus << 16) | (d->devfn << 8) | (addr & 0xfc));
716 return inb(0xcfc + (addr & 3));
717 }
718
719 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
720 {
721 uint16_t cmd;
722 uint32_t ofs, old_addr;
723
724 if ( region_num == PCI_ROM_SLOT ) {
725 ofs = 0x30;
726 }else{
727 ofs = 0x10 + region_num * 4;
728 }
729
730 old_addr = pci_config_readl(d, ofs);
731
732 pci_config_writel(d, ofs, addr);
733 BX_INFO("region %d: 0x%08x\n", region_num, addr);
734
735 /* enable memory mappings */
736 cmd = pci_config_readw(d, PCI_COMMAND);
737 if ( region_num == PCI_ROM_SLOT )
738 cmd |= 2;
739 else if (old_addr & PCI_ADDRESS_SPACE_IO)
740 cmd |= 1;
741 else
742 cmd |= 2;
743 pci_config_writew(d, PCI_COMMAND, cmd);
744 }
745
746 /* return the global irq number corresponding to a given device irq
747 pin. We could also use the bus number to have a more precise
748 mapping. */
749 static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
750 {
751 int slot_addend;
752 slot_addend = (pci_dev->devfn >> 3) - 1;
753 return (irq_num + slot_addend) & 3;
754 }
755
756 static void find_bios_table_area(void)
757 {
758 unsigned long addr;
759 for(addr = 0xf0000; addr < 0x100000; addr += 16) {
760 if (*(uint32_t *)addr == 0xaafb4442) {
761 bios_table_cur_addr = addr + 8;
762 bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
763 BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
764 bios_table_cur_addr, bios_table_end_addr);
765 return;
766 }
767 }
768 return;
769 }
770
771 static void bios_shadow_init(PCIDevice *d)
772 {
773 int v;
774
775 if (bios_table_cur_addr == 0)
776 return;
777
778 /* remap the BIOS to shadow RAM an keep it read/write while we
779 are writing tables */
780 v = pci_config_readb(d, 0x59);
781 v &= 0xcf;
782 pci_config_writeb(d, 0x59, v);
783 memcpy((void *)BIOS_TMP_STORAGE, (void *)0x000f0000, 0x10000);
784 v |= 0x30;
785 pci_config_writeb(d, 0x59, v);
786 memcpy((void *)0x000f0000, (void *)BIOS_TMP_STORAGE, 0x10000);
787
788 i440_pcidev = *d;
789 }
790
791 static void bios_lock_shadow_ram(void)
792 {
793 PCIDevice *d = &i440_pcidev;
794 int v;
795
796 wbinvd();
797 v = pci_config_readb(d, 0x59);
798 v = (v & 0x0f) | (0x10);
799 pci_config_writeb(d, 0x59, v);
800 }
801
802 static void pci_bios_init_bridges(PCIDevice *d)
803 {
804 uint16_t vendor_id, device_id;
805
806 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
807 device_id = pci_config_readw(d, PCI_DEVICE_ID);
808
809 if (vendor_id == PCI_VENDOR_ID_INTEL &&
810 (device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
811 device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
812 int i, irq;
813 uint8_t elcr[2];
814
815 /* PIIX3/PIIX4 PCI to ISA bridge */
816
817 elcr[0] = 0x00;
818 elcr[1] = 0x00;
819 for(i = 0; i < 4; i++) {
820 irq = pci_irqs[i];
821 /* set to trigger level */
822 elcr[irq >> 3] |= (1 << (irq & 7));
823 /* activate irq remapping in PIIX */
824 pci_config_writeb(d, 0x60 + i, irq);
825 }
826 outb(0x4d0, elcr[0]);
827 outb(0x4d1, elcr[1]);
828 BX_INFO("PIIX3/PIIX4 init: elcr=%02x %02x\n",
829 elcr[0], elcr[1]);
830 } else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441) {
831 /* i440 PCI bridge */
832 bios_shadow_init(d);
833 }
834 }
835
836 extern uint8_t smm_relocation_start, smm_relocation_end;
837 extern uint8_t smm_code_start, smm_code_end;
838
839 #ifdef BX_USE_SMM
840 static void smm_init(PCIDevice *d)
841 {
842 uint32_t value;
843
844 /* check if SMM init is already done */
845 value = pci_config_readl(d, 0x58);
846 if ((value & (1 << 25)) == 0) {
847
848 /* enable the SMM memory window */
849 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x48);
850
851 /* save original memory content */
852 memcpy((void *)0xa8000, (void *)0x38000, 0x8000);
853
854 /* copy the SMM relocation code */
855 memcpy((void *)0x38000, &smm_relocation_start,
856 &smm_relocation_end - &smm_relocation_start);
857
858 /* enable SMI generation when writing to the APMC register */
859 pci_config_writel(d, 0x58, value | (1 << 25));
860
861 /* init APM status port */
862 outb(0xb3, 0x01);
863
864 /* raise an SMI interrupt */
865 outb(0xb2, 0x00);
866
867 /* wait until SMM code executed */
868 while (inb(0xb3) != 0x00);
869
870 /* restore original memory content */
871 memcpy((void *)0x38000, (void *)0xa8000, 0x8000);
872
873 /* copy the SMM code */
874 memcpy((void *)0xa8000, &smm_code_start,
875 &smm_code_end - &smm_code_start);
876 wbinvd();
877
878 /* close the SMM memory window and enable normal SMM */
879 pci_config_writeb(&i440_pcidev, 0x72, 0x02 | 0x08);
880 }
881 }
882 #endif
883
884 static void piix4_pm_enable(PCIDevice *d)
885 {
886 /* PIIX4 Power Management device (for ACPI) */
887 pci_config_writel(d, 0x40, PM_IO_BASE | 1);
888 pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
889 pci_config_writel(d, 0x90, SMB_IO_BASE | 1);
890 pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
891 #ifdef BX_USE_SMM
892 smm_init(d);
893 #endif
894 }
895
896 static void pci_bios_init_device(PCIDevice *d)
897 {
898 int class;
899 uint32_t *paddr;
900 int i, pin, pic_irq, vendor_id, device_id;
901
902 class = pci_config_readw(d, PCI_CLASS_DEVICE);
903 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
904 device_id = pci_config_readw(d, PCI_DEVICE_ID);
905 BX_INFO("PCI: bus=%d devfn=0x%02x: vendor_id=0x%04x device_id=0x%04x class=0x%04x\n",
906 d->bus, d->devfn, vendor_id, device_id, class);
907 switch(class) {
908 case 0x0101: /* Mass storage controller - IDE interface */
909 if (vendor_id == PCI_VENDOR_ID_INTEL &&
910 (device_id == PCI_DEVICE_ID_INTEL_82371SB_1 ||
911 device_id == PCI_DEVICE_ID_INTEL_82371AB)) {
912 /* PIIX3/PIIX4 IDE */
913 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
914 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
915 goto default_map;
916 } else {
917 /* IDE: we map it as in ISA mode */
918 pci_set_io_region_addr(d, 0, 0x1f0);
919 pci_set_io_region_addr(d, 1, 0x3f4);
920 pci_set_io_region_addr(d, 2, 0x170);
921 pci_set_io_region_addr(d, 3, 0x374);
922 }
923 break;
924 case 0x0300: /* Display controller - VGA compatible controller */
925 if (vendor_id != 0x1234)
926 goto default_map;
927 /* VGA: map frame buffer to default Bochs VBE address */
928 pci_set_io_region_addr(d, 0, 0xE0000000);
929 break;
930 case 0x0800: /* Generic system peripheral - PIC */
931 if (vendor_id == PCI_VENDOR_ID_IBM) {
932 /* IBM */
933 if (device_id == 0x0046 || device_id == 0xFFFF) {
934 /* MPIC & MPIC2 */
935 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
936 }
937 }
938 break;
939 case 0xff00:
940 if (vendor_id == PCI_VENDOR_ID_APPLE &&
941 (device_id == 0x0017 || device_id == 0x0022)) {
942 /* macio bridge */
943 pci_set_io_region_addr(d, 0, 0x80800000);
944 }
945 break;
946 default:
947 default_map:
948 /* default memory mappings */
949 for(i = 0; i < PCI_NUM_REGIONS; i++) {
950 int ofs;
951 uint32_t val, size ;
952
953 if (i == PCI_ROM_SLOT)
954 ofs = 0x30;
955 else
956 ofs = 0x10 + i * 4;
957 pci_config_writel(d, ofs, 0xffffffff);
958 val = pci_config_readl(d, ofs);
959 if (val != 0) {
960 size = (~(val & ~0xf)) + 1;
961 if (val & PCI_ADDRESS_SPACE_IO)
962 paddr = &pci_bios_io_addr;
963 else if (size >= 0x04000000)
964 paddr = &pci_bios_bigmem_addr;
965 else
966 paddr = &pci_bios_mem_addr;
967 *paddr = (*paddr + size - 1) & ~(size - 1);
968 pci_set_io_region_addr(d, i, *paddr);
969 *paddr += size;
970 /* make memory address page aligned */
971 if (!(val & PCI_ADDRESS_SPACE_IO))
972 *paddr = (*paddr + 0xfff) & 0xfffff000;
973 }
974 }
975 break;
976 }
977
978 /* map the interrupt */
979 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
980 if (pin != 0) {
981 pin = pci_slot_get_pirq(d, pin - 1);
982 pic_irq = pci_irqs[pin];
983 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
984 }
985
986 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
987 /* PIIX4 Power Management device (for ACPI) */
988
989 // acpi sci is hardwired to 9
990 pci_config_writeb(d, PCI_INTERRUPT_LINE, 9);
991
992 pm_io_base = PM_IO_BASE;
993 smb_io_base = SMB_IO_BASE;
994 pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
995 piix4_pm_enable(d);
996 acpi_enabled = 1;
997 }
998 }
999
1000 void pci_for_each_device(void (*init_func)(PCIDevice *d))
1001 {
1002 PCIDevice d1, *d = &d1;
1003 int bus, devfn;
1004 uint16_t vendor_id, device_id;
1005
1006 for(bus = 0; bus < 1; bus++) {
1007 for(devfn = 0; devfn < 256; devfn++) {
1008 d->bus = bus;
1009 d->devfn = devfn;
1010 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1011 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1012 if (vendor_id != 0xffff || device_id != 0xffff) {
1013 init_func(d);
1014 }
1015 }
1016 }
1017 }
1018
1019 void pci_bios_init(void)
1020 {
1021 pci_bios_io_addr = 0xc000;
1022 pci_bios_mem_addr = 0xf0000000;
1023 pci_bios_bigmem_addr = ram_size;
1024 if (pci_bios_bigmem_addr < 0x90000000)
1025 pci_bios_bigmem_addr = 0x90000000;
1026
1027 pci_for_each_device(pci_bios_init_bridges);
1028
1029 pci_for_each_device(pci_bios_init_device);
1030 }
1031
1032 /****************************************************/
1033 /* Multi Processor table init */
1034
1035 static void putb(uint8_t **pp, int val)
1036 {
1037 uint8_t *q;
1038 q = *pp;
1039 *q++ = val;
1040 *pp = q;
1041 }
1042
1043 static void putstr(uint8_t **pp, const char *str)
1044 {
1045 uint8_t *q;
1046 q = *pp;
1047 while (*str)
1048 *q++ = *str++;
1049 *pp = q;
1050 }
1051
1052 static void putle16(uint8_t **pp, int val)
1053 {
1054 uint8_t *q;
1055 q = *pp;
1056 *q++ = val;
1057 *q++ = val >> 8;
1058 *pp = q;
1059 }
1060
1061 static void putle32(uint8_t **pp, int val)
1062 {
1063 uint8_t *q;
1064 q = *pp;
1065 *q++ = val;
1066 *q++ = val >> 8;
1067 *q++ = val >> 16;
1068 *q++ = val >> 24;
1069 *pp = q;
1070 }
1071
1072 static int mpf_checksum(const uint8_t *data, int len)
1073 {
1074 int sum, i;
1075 sum = 0;
1076 for(i = 0; i < len; i++)
1077 sum += data[i];
1078 return sum & 0xff;
1079 }
1080
1081 static unsigned long align(unsigned long addr, unsigned long v)
1082 {
1083 return (addr + v - 1) & ~(v - 1);
1084 }
1085
1086 static void mptable_init(void)
1087 {
1088 uint8_t *mp_config_table, *q, *float_pointer_struct;
1089 int ioapic_id, i, len;
1090 int mp_config_table_size;
1091
1092 #ifdef BX_USE_EBDA_TABLES
1093 mp_config_table = (uint8_t *)(ram_size - ACPI_DATA_SIZE - MPTABLE_MAX_SIZE);
1094 #else
1095 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1096 mp_config_table = (uint8_t *)bios_table_cur_addr;
1097 #endif
1098 q = mp_config_table;
1099 putstr(&q, "PCMP"); /* "PCMP signature */
1100 putle16(&q, 0); /* table length (patched later) */
1101 putb(&q, 4); /* spec rev */
1102 putb(&q, 0); /* checksum (patched later) */
1103 #ifdef BX_QEMU
1104 putstr(&q, "QEMUCPU "); /* OEM id */
1105 #else
1106 putstr(&q, "BOCHSCPU");
1107 #endif
1108 putstr(&q, "0.1 "); /* vendor id */
1109 putle32(&q, 0); /* OEM table ptr */
1110 putle16(&q, 0); /* OEM table size */
1111 putle16(&q, MAX_CPUS + 18); /* entry count */
1112 putle32(&q, 0xfee00000); /* local APIC addr */
1113 putle16(&q, 0); /* ext table length */
1114 putb(&q, 0); /* ext table checksum */
1115 putb(&q, 0); /* reserved */
1116
1117 for(i = 0; i < MAX_CPUS ; i++) {
1118 putb(&q, 0); /* entry type = processor */
1119 putb(&q, i); /* APIC id */
1120 putb(&q, 0x11); /* local APIC version number */
1121 if (i == 0)
1122 putb(&q, 3); /* cpu flags: enabled, bootstrap cpu */
1123 else if ( i < smp_cpus)
1124 putb(&q, 1); /* cpu flags: enabled */
1125 else
1126 putb(&q, 0); /* cpu flags: disabled */
1127 putb(&q, 0); /* cpu signature */
1128 putb(&q, 6);
1129 putb(&q, 0);
1130 putb(&q, 0);
1131 putle16(&q, 0x201); /* feature flags */
1132 putle16(&q, 0);
1133
1134 putle16(&q, 0); /* reserved */
1135 putle16(&q, 0);
1136 putle16(&q, 0);
1137 putle16(&q, 0);
1138 }
1139
1140 /* isa bus */
1141 putb(&q, 1); /* entry type = bus */
1142 putb(&q, 0); /* bus ID */
1143 putstr(&q, "ISA ");
1144
1145 /* ioapic */
1146 ioapic_id = smp_cpus;
1147 putb(&q, 2); /* entry type = I/O APIC */
1148 putb(&q, ioapic_id); /* apic ID */
1149 putb(&q, 0x11); /* I/O APIC version number */
1150 putb(&q, 1); /* enable */
1151 putle32(&q, 0xfec00000); /* I/O APIC addr */
1152
1153 /* irqs */
1154 for(i = 0; i < 16; i++) {
1155 putb(&q, 3); /* entry type = I/O interrupt */
1156 putb(&q, 0); /* interrupt type = vectored interrupt */
1157 putb(&q, 0); /* flags: po=0, el=0 */
1158 putb(&q, 0);
1159 putb(&q, 0); /* source bus ID = ISA */
1160 putb(&q, i); /* source bus IRQ */
1161 putb(&q, ioapic_id); /* dest I/O APIC ID */
1162 putb(&q, i); /* dest I/O APIC interrupt in */
1163 }
1164 /* patch length */
1165 len = q - mp_config_table;
1166 mp_config_table[4] = len;
1167 mp_config_table[5] = len >> 8;
1168
1169 mp_config_table[7] = -mpf_checksum(mp_config_table, q - mp_config_table);
1170
1171 mp_config_table_size = q - mp_config_table;
1172
1173 #ifndef BX_USE_EBDA_TABLES
1174 bios_table_cur_addr += mp_config_table_size;
1175 #endif
1176
1177 /* floating pointer structure */
1178 #ifdef BX_USE_EBDA_TABLES
1179 ebda_cur_addr = align(ebda_cur_addr, 16);
1180 float_pointer_struct = (uint8_t *)ebda_cur_addr;
1181 #else
1182 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1183 float_pointer_struct = (uint8_t *)bios_table_cur_addr;
1184 #endif
1185 q = float_pointer_struct;
1186 putstr(&q, "_MP_");
1187 /* pointer to MP config table */
1188 putle32(&q, (unsigned long)mp_config_table);
1189
1190 putb(&q, 1); /* length in 16 byte units */
1191 putb(&q, 4); /* MP spec revision */
1192 putb(&q, 0); /* checksum (patched later) */
1193 putb(&q, 0); /* MP feature byte 1 */
1194
1195 putb(&q, 0);
1196 putb(&q, 0);
1197 putb(&q, 0);
1198 putb(&q, 0);
1199 float_pointer_struct[10] =
1200 -mpf_checksum(float_pointer_struct, q - float_pointer_struct);
1201 #ifdef BX_USE_EBDA_TABLES
1202 ebda_cur_addr += (q - float_pointer_struct);
1203 #else
1204 bios_table_cur_addr += (q - float_pointer_struct);
1205 #endif
1206 BX_INFO("MP table addr=0x%08lx MPC table addr=0x%08lx size=0x%x\n",
1207 (unsigned long)float_pointer_struct,
1208 (unsigned long)mp_config_table,
1209 mp_config_table_size);
1210 }
1211
1212 /****************************************************/
1213 /* ACPI tables init */
1214
1215 /* Table structure from Linux kernel (the ACPI tables are under the
1216 BSD license) */
1217
1218 /*
1219 * All tables must be byte-packed to match the ACPI specification, since
1220 * the tables are provided by the system BIOS.
1221 */
1222
1223 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \
1224 uint8_t signature [4]; /* ACPI signature (4 ASCII characters) */\
1225 uint32_t length; /* Length of table, in bytes, including header */\
1226 uint8_t revision; /* ACPI Specification minor version # */\
1227 uint8_t checksum; /* To make sum of entire table == 0 */\
1228 uint8_t oem_id [6]; /* OEM identification */\
1229 uint8_t oem_table_id [8]; /* OEM table identification */\
1230 uint32_t oem_revision; /* OEM revision number */\
1231 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */\
1232 uint32_t asl_compiler_revision; /* ASL compiler revision number */
1233
1234
1235 struct acpi_table_header /* ACPI common table header */
1236 {
1237 ACPI_TABLE_HEADER_DEF
1238 } __attribute__((__packed__));
1239
1240 struct rsdp_descriptor /* Root System Descriptor Pointer */
1241 {
1242 uint8_t signature [8]; /* ACPI signature, contains "RSD PTR " */
1243 uint8_t checksum; /* To make sum of struct == 0 */
1244 uint8_t oem_id [6]; /* OEM identification */
1245 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */
1246 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */
1247 uint32_t length; /* XSDT Length in bytes including hdr */
1248 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */
1249 uint8_t extended_checksum; /* Checksum of entire table */
1250 uint8_t reserved [3]; /* Reserved field must be 0 */
1251 } __attribute__((__packed__));
1252
1253 /*
1254 * ACPI 1.0 Root System Description Table (RSDT)
1255 */
1256 struct rsdt_descriptor_rev1
1257 {
1258 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1259 uint32_t table_offset_entry [2]; /* Array of pointers to other */
1260 /* ACPI tables */
1261 } __attribute__((__packed__));
1262
1263 /*
1264 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
1265 */
1266 struct facs_descriptor_rev1
1267 {
1268 uint8_t signature[4]; /* ACPI Signature */
1269 uint32_t length; /* Length of structure, in bytes */
1270 uint32_t hardware_signature; /* Hardware configuration signature */
1271 uint32_t firmware_waking_vector; /* ACPI OS waking vector */
1272 uint32_t global_lock; /* Global Lock */
1273 uint32_t S4bios_f : 1; /* Indicates if S4BIOS support is present */
1274 uint32_t reserved1 : 31; /* Must be 0 */
1275 uint8_t resverved3 [40]; /* Reserved - must be zero */
1276 } __attribute__((__packed__));
1277
1278
1279 /*
1280 * ACPI 1.0 Fixed ACPI Description Table (FADT)
1281 */
1282 struct fadt_descriptor_rev1
1283 {
1284 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1285 uint32_t firmware_ctrl; /* Physical address of FACS */
1286 uint32_t dsdt; /* Physical address of DSDT */
1287 uint8_t model; /* System Interrupt Model */
1288 uint8_t reserved1; /* Reserved */
1289 uint16_t sci_int; /* System vector of SCI interrupt */
1290 uint32_t smi_cmd; /* Port address of SMI command port */
1291 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */
1292 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */
1293 uint8_t S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
1294 uint8_t reserved2; /* Reserved - must be zero */
1295 uint32_t pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
1296 uint32_t pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
1297 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
1298 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
1299 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
1300 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
1301 uint32_t gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
1302 uint32_t gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
1303 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
1304 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
1305 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
1306 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */
1307 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
1308 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
1309 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */
1310 uint8_t reserved3; /* Reserved */
1311 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
1312 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
1313 uint16_t flush_size; /* Size of area read to flush caches */
1314 uint16_t flush_stride; /* Stride used in flushing caches */
1315 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */
1316 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */
1317 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
1318 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
1319 uint8_t century; /* Index to century in RTC CMOS RAM */
1320 uint8_t reserved4; /* Reserved */
1321 uint8_t reserved4a; /* Reserved */
1322 uint8_t reserved4b; /* Reserved */
1323 #if 0
1324 uint32_t wb_invd : 1; /* The wbinvd instruction works properly */
1325 uint32_t wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
1326 uint32_t proc_c1 : 1; /* All processors support C1 state */
1327 uint32_t plvl2_up : 1; /* C2 state works on MP system */
1328 uint32_t pwr_button : 1; /* Power button is handled as a generic feature */
1329 uint32_t sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
1330 uint32_t fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
1331 uint32_t rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
1332 uint32_t tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
1333 uint32_t reserved5 : 23; /* Reserved - must be zero */
1334 #else
1335 uint32_t flags;
1336 #endif
1337 } __attribute__((__packed__));
1338
1339 /*
1340 * MADT values and structures
1341 */
1342
1343 /* Values for MADT PCATCompat */
1344
1345 #define DUAL_PIC 0
1346 #define MULTIPLE_APIC 1
1347
1348
1349 /* Master MADT */
1350
1351 struct multiple_apic_table
1352 {
1353 ACPI_TABLE_HEADER_DEF /* ACPI common table header */
1354 uint32_t local_apic_address; /* Physical address of local APIC */
1355 #if 0
1356 uint32_t PCATcompat : 1; /* A one indicates system also has dual 8259s */
1357 uint32_t reserved1 : 31;
1358 #else
1359 uint32_t flags;
1360 #endif
1361 } __attribute__((__packed__));
1362
1363
1364 /* Values for Type in APIC_HEADER_DEF */
1365
1366 #define APIC_PROCESSOR 0
1367 #define APIC_IO 1
1368 #define APIC_XRUPT_OVERRIDE 2
1369 #define APIC_NMI 3
1370 #define APIC_LOCAL_NMI 4
1371 #define APIC_ADDRESS_OVERRIDE 5
1372 #define APIC_IO_SAPIC 6
1373 #define APIC_LOCAL_SAPIC 7
1374 #define APIC_XRUPT_SOURCE 8
1375 #define APIC_RESERVED 9 /* 9 and greater are reserved */
1376
1377 /*
1378 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE)
1379 */
1380 #define APIC_HEADER_DEF /* Common APIC sub-structure header */\
1381 uint8_t type; \
1382 uint8_t length;
1383
1384 /* Sub-structures for MADT */
1385
1386 struct madt_processor_apic
1387 {
1388 APIC_HEADER_DEF
1389 uint8_t processor_id; /* ACPI processor id */
1390 uint8_t local_apic_id; /* Processor's local APIC id */
1391 #if 0
1392 uint32_t processor_enabled: 1; /* Processor is usable if set */
1393 uint32_t reserved2 : 31; /* Reserved, must be zero */
1394 #else
1395 uint32_t flags;
1396 #endif
1397 } __attribute__((__packed__));
1398
1399 struct madt_io_apic
1400 {
1401 APIC_HEADER_DEF
1402 uint8_t io_apic_id; /* I/O APIC ID */
1403 uint8_t reserved; /* Reserved - must be zero */
1404 uint32_t address; /* APIC physical address */
1405 uint32_t interrupt; /* Global system interrupt where INTI
1406 * lines start */
1407 } __attribute__((__packed__));
1408
1409 struct madt_intsrcovr {
1410 APIC_HEADER_DEF
1411 uint8_t bus;
1412 uint8_t source;
1413 uint32_t gsi;
1414 uint16_t flags;
1415 } __attribute__((packed));
1416
1417 #include "acpi-dsdt.hex"
1418
1419 static inline uint16_t cpu_to_le16(uint16_t x)
1420 {
1421 return x;
1422 }
1423
1424 static inline uint32_t cpu_to_le32(uint32_t x)
1425 {
1426 return x;
1427 }
1428
1429 static int acpi_checksum(const uint8_t *data, int len)
1430 {
1431 int sum, i;
1432 sum = 0;
1433 for(i = 0; i < len; i++)
1434 sum += data[i];
1435 return (-sum) & 0xff;
1436 }
1437
1438 static void acpi_build_table_header(struct acpi_table_header *h,
1439 char *sig, int len, uint8_t rev)
1440 {
1441 memcpy(h->signature, sig, 4);
1442 h->length = cpu_to_le32(len);
1443 h->revision = rev;
1444 #ifdef BX_QEMU
1445 memcpy(h->oem_id, "QEMU ", 6);
1446 memcpy(h->oem_table_id, "QEMU", 4);
1447 #else
1448 memcpy(h->oem_id, "BOCHS ", 6);
1449 memcpy(h->oem_table_id, "BXPC", 4);
1450 #endif
1451 memcpy(h->oem_table_id + 4, sig, 4);
1452 h->oem_revision = cpu_to_le32(1);
1453 #ifdef BX_QEMU
1454 memcpy(h->asl_compiler_id, "QEMU", 4);
1455 #else
1456 memcpy(h->asl_compiler_id, "BXPC", 4);
1457 #endif
1458 h->asl_compiler_revision = cpu_to_le32(1);
1459 h->checksum = acpi_checksum((void *)h, len);
1460 }
1461
1462 /* base_addr must be a multiple of 4KB */
1463 void acpi_bios_init(void)
1464 {
1465 struct rsdp_descriptor *rsdp;
1466 struct rsdt_descriptor_rev1 *rsdt;
1467 struct fadt_descriptor_rev1 *fadt;
1468 struct facs_descriptor_rev1 *facs;
1469 struct multiple_apic_table *madt;
1470 uint8_t *dsdt;
1471 uint32_t base_addr, rsdt_addr, fadt_addr, addr, facs_addr, dsdt_addr;
1472 uint32_t acpi_tables_size, madt_addr, madt_size;
1473 int i;
1474
1475 /* reserve memory space for tables */
1476 #ifdef BX_USE_EBDA_TABLES
1477 ebda_cur_addr = align(ebda_cur_addr, 16);
1478 rsdp = (void *)(ebda_cur_addr);
1479 ebda_cur_addr += sizeof(*rsdp);
1480 #else
1481 bios_table_cur_addr = align(bios_table_cur_addr, 16);
1482 rsdp = (void *)(bios_table_cur_addr);
1483 bios_table_cur_addr += sizeof(*rsdp);
1484 #endif
1485
1486 addr = base_addr = ram_size - ACPI_DATA_SIZE;
1487 rsdt_addr = addr;
1488 rsdt = (void *)(addr);
1489 addr += sizeof(*rsdt);
1490
1491 fadt_addr = addr;
1492 fadt = (void *)(addr);
1493 addr += sizeof(*fadt);
1494
1495 /* XXX: FACS should be in RAM */
1496 addr = (addr + 63) & ~63; /* 64 byte alignment for FACS */
1497 facs_addr = addr;
1498 facs = (void *)(addr);
1499 addr += sizeof(*facs);
1500
1501 dsdt_addr = addr;
1502 dsdt = (void *)(addr);
1503 addr += sizeof(AmlCode);
1504
1505 addr = (addr + 7) & ~7;
1506 madt_addr = addr;
1507 madt_size = sizeof(*madt) +
1508 sizeof(struct madt_processor_apic) * MAX_CPUS +
1509 sizeof(struct madt_io_apic);
1510 madt = (void *)(addr);
1511 addr += madt_size;
1512
1513 acpi_tables_size = addr - base_addr;
1514
1515 BX_INFO("ACPI tables: RSDP addr=0x%08lx ACPI DATA addr=0x%08lx size=0x%x\n",
1516 (unsigned long)rsdp,
1517 (unsigned long)rsdt, acpi_tables_size);
1518
1519 /* RSDP */
1520 memset(rsdp, 0, sizeof(*rsdp));
1521 memcpy(rsdp->signature, "RSD PTR ", 8);
1522 #ifdef BX_QEMU
1523 memcpy(rsdp->oem_id, "QEMU ", 6);
1524 #else
1525 memcpy(rsdp->oem_id, "BOCHS ", 6);
1526 #endif
1527 rsdp->rsdt_physical_address = cpu_to_le32(rsdt_addr);
1528 rsdp->checksum = acpi_checksum((void *)rsdp, 20);
1529
1530 /* RSDT */
1531 memset(rsdt, 0, sizeof(*rsdt));
1532 rsdt->table_offset_entry[0] = cpu_to_le32(fadt_addr);
1533 rsdt->table_offset_entry[1] = cpu_to_le32(madt_addr);
1534 acpi_build_table_header((struct acpi_table_header *)rsdt,
1535 "RSDT", sizeof(*rsdt), 1);
1536
1537 /* FADT */
1538 memset(fadt, 0, sizeof(*fadt));
1539 fadt->firmware_ctrl = cpu_to_le32(facs_addr);
1540 fadt->dsdt = cpu_to_le32(dsdt_addr);
1541 fadt->model = 1;
1542 fadt->reserved1 = 0;
1543 fadt->sci_int = cpu_to_le16(pm_sci_int);
1544 fadt->smi_cmd = cpu_to_le32(SMI_CMD_IO_ADDR);
1545 fadt->acpi_enable = 0xf1;
1546 fadt->acpi_disable = 0xf0;
1547 fadt->pm1a_evt_blk = cpu_to_le32(pm_io_base);
1548 fadt->pm1a_cnt_blk = cpu_to_le32(pm_io_base + 0x04);
1549 fadt->pm_tmr_blk = cpu_to_le32(pm_io_base + 0x08);
1550 fadt->pm1_evt_len = 4;
1551 fadt->pm1_cnt_len = 2;
1552 fadt->pm_tmr_len = 4;
1553 fadt->plvl2_lat = cpu_to_le16(0xfff); // C2 state not supported
1554 fadt->plvl3_lat = cpu_to_le16(0xfff); // C3 state not supported
1555 fadt->gpe0_blk = cpu_to_le32(0xafe0);
1556 fadt->gpe0_blk_len = 4;
1557 /* WBINVD + PROC_C1 + SLP_BUTTON + FIX_RTC */
1558 fadt->flags = cpu_to_le32((1 << 0) | (1 << 2) | (1 << 5) | (1 << 6));
1559 acpi_build_table_header((struct acpi_table_header *)fadt, "FACP",
1560 sizeof(*fadt), 1);
1561
1562 /* FACS */
1563 memset(facs, 0, sizeof(*facs));
1564 memcpy(facs->signature, "FACS", 4);
1565 facs->length = cpu_to_le32(sizeof(*facs));
1566 BX_INFO("Firmware waking vector %p\n", &facs->firmware_waking_vector);
1567
1568 /* DSDT */
1569 memcpy(dsdt, AmlCode, sizeof(AmlCode));
1570
1571 /* MADT */
1572 {
1573 struct madt_processor_apic *apic;
1574 struct madt_io_apic *io_apic;
1575 struct madt_intsrcovr *intsrcovr;
1576
1577 memset(madt, 0, madt_size);
1578 madt->local_apic_address = cpu_to_le32(0xfee00000);
1579 madt->flags = cpu_to_le32(1);
1580 apic = (void *)(madt + 1);
1581 for(i=0;i<MAX_CPUS;i++) {
1582 apic->type = APIC_PROCESSOR;
1583 apic->length = sizeof(*apic);
1584 apic->processor_id = i;
1585 apic->local_apic_id = i;
1586 if (i < smp_cpus)
1587 apic->flags = cpu_to_le32(1);
1588 else
1589 apic->flags = 0;
1590 apic++;
1591 }
1592 io_apic = (void *)apic;
1593 io_apic->type = APIC_IO;
1594 io_apic->length = sizeof(*io_apic);
1595 io_apic->io_apic_id = smp_cpus;
1596 io_apic->address = cpu_to_le32(0xfec00000);
1597 io_apic->interrupt = cpu_to_le32(0);
1598
1599 intsrcovr = (struct madt_intsrcovr*)(io_apic + 1);
1600 for ( i = 0; i < 16; i++ ) {
1601 if ( PCI_ISA_IRQ_MASK & (1U << i) ) {
1602 memset(intsrcovr, 0, sizeof(*intsrcovr));
1603 intsrcovr->type = APIC_XRUPT_OVERRIDE;
1604 intsrcovr->length = sizeof(*intsrcovr);
1605 intsrcovr->source = i;
1606 intsrcovr->gsi = i;
1607 intsrcovr->flags = 0xd; /* active high, level triggered */
1608 } else {
1609 /* No need for a INT source override structure. */
1610 continue;
1611 }
1612 intsrcovr++;
1613 madt_size += sizeof(struct madt_intsrcovr);
1614 }
1615 acpi_build_table_header((struct acpi_table_header *)madt,
1616 "APIC", madt_size, 1);
1617 }
1618 }
1619
1620 /* SMBIOS entry point -- must be written to a 16-bit aligned address
1621 between 0xf0000 and 0xfffff.
1622 */
1623 struct smbios_entry_point {
1624 char anchor_string[4];
1625 uint8_t checksum;
1626 uint8_t length;
1627 uint8_t smbios_major_version;
1628 uint8_t smbios_minor_version;
1629 uint16_t max_structure_size;
1630 uint8_t entry_point_revision;
1631 uint8_t formatted_area[5];
1632 char intermediate_anchor_string[5];
1633 uint8_t intermediate_checksum;
1634 uint16_t structure_table_length;
1635 uint32_t structure_table_address;
1636 uint16_t number_of_structures;
1637 uint8_t smbios_bcd_revision;
1638 } __attribute__((__packed__));
1639
1640 /* This goes at the beginning of every SMBIOS structure. */
1641 struct smbios_structure_header {
1642 uint8_t type;
1643 uint8_t length;
1644 uint16_t handle;
1645 } __attribute__((__packed__));
1646
1647 /* SMBIOS type 0 - BIOS Information */
1648 struct smbios_type_0 {
1649 struct smbios_structure_header header;
1650 uint8_t vendor_str;
1651 uint8_t bios_version_str;
1652 uint16_t bios_starting_address_segment;
1653 uint8_t bios_release_date_str;
1654 uint8_t bios_rom_size;
1655 uint8_t bios_characteristics[8];
1656 uint8_t bios_characteristics_extension_bytes[2];
1657 uint8_t system_bios_major_release;
1658 uint8_t system_bios_minor_release;
1659 uint8_t embedded_controller_major_release;
1660 uint8_t embedded_controller_minor_release;
1661 } __attribute__((__packed__));
1662
1663 /* SMBIOS type 1 - System Information */
1664 struct smbios_type_1 {
1665 struct smbios_structure_header header;
1666 uint8_t manufacturer_str;
1667 uint8_t product_name_str;
1668 uint8_t version_str;
1669 uint8_t serial_number_str;
1670 uint8_t uuid[16];
1671 uint8_t wake_up_type;
1672 uint8_t sku_number_str;
1673 uint8_t family_str;
1674 } __attribute__((__packed__));
1675
1676 /* SMBIOS type 3 - System Enclosure (v2.3) */
1677 struct smbios_type_3 {
1678 struct smbios_structure_header header;
1679 uint8_t manufacturer_str;
1680 uint8_t type;
1681 uint8_t version_str;
1682 uint8_t serial_number_str;
1683 uint8_t asset_tag_number_str;
1684 uint8_t boot_up_state;
1685 uint8_t power_supply_state;
1686 uint8_t thermal_state;
1687 uint8_t security_status;
1688 uint32_t oem_defined;
1689 uint8_t height;
1690 uint8_t number_of_power_cords;
1691 uint8_t contained_element_count;
1692 // contained elements follow
1693 } __attribute__((__packed__));
1694
1695 /* SMBIOS type 4 - Processor Information (v2.0) */
1696 struct smbios_type_4 {
1697 struct smbios_structure_header header;
1698 uint8_t socket_designation_str;
1699 uint8_t processor_type;
1700 uint8_t processor_family;
1701 uint8_t processor_manufacturer_str;
1702 uint32_t processor_id[2];
1703 uint8_t processor_version_str;
1704 uint8_t voltage;
1705 uint16_t external_clock;
1706 uint16_t max_speed;
1707 uint16_t current_speed;
1708 uint8_t status;
1709 uint8_t processor_upgrade;
1710 uint16_t l1_cache_handle;
1711 uint16_t l2_cache_handle;
1712 uint16_t l3_cache_handle;
1713 } __attribute__((__packed__));
1714
1715 /* SMBIOS type 16 - Physical Memory Array
1716 * Associated with one type 17 (Memory Device).
1717 */
1718 struct smbios_type_16 {
1719 struct smbios_structure_header header;
1720 uint8_t location;
1721 uint8_t use;
1722 uint8_t error_correction;
1723 uint32_t maximum_capacity;
1724 uint16_t memory_error_information_handle;
1725 uint16_t number_of_memory_devices;
1726 } __attribute__((__packed__));
1727
1728 /* SMBIOS type 17 - Memory Device
1729 * Associated with one type 19
1730 */
1731 struct smbios_type_17 {
1732 struct smbios_structure_header header;
1733 uint16_t physical_memory_array_handle;
1734 uint16_t memory_error_information_handle;
1735 uint16_t total_width;
1736 uint16_t data_width;
1737 uint16_t size;
1738 uint8_t form_factor;
1739 uint8_t device_set;
1740 uint8_t device_locator_str;
1741 uint8_t bank_locator_str;
1742 uint8_t memory_type;
1743 uint16_t type_detail;
1744 } __attribute__((__packed__));
1745
1746 /* SMBIOS type 19 - Memory Array Mapped Address */
1747 struct smbios_type_19 {
1748 struct smbios_structure_header header;
1749 uint32_t starting_address;
1750 uint32_t ending_address;
1751 uint16_t memory_array_handle;
1752 uint8_t partition_width;
1753 } __attribute__((__packed__));
1754
1755 /* SMBIOS type 20 - Memory Device Mapped Address */
1756 struct smbios_type_20 {
1757 struct smbios_structure_header header;
1758 uint32_t starting_address;
1759 uint32_t ending_address;
1760 uint16_t memory_device_handle;
1761 uint16_t memory_array_mapped_address_handle;
1762 uint8_t partition_row_position;
1763 uint8_t interleave_position;
1764 uint8_t interleaved_data_depth;
1765 } __attribute__((__packed__));
1766
1767 /* SMBIOS type 32 - System Boot Information */
1768 struct smbios_type_32 {
1769 struct smbios_structure_header header;
1770 uint8_t reserved[6];
1771 uint8_t boot_status;
1772 } __attribute__((__packed__));
1773
1774 /* SMBIOS type 127 -- End-of-table */
1775 struct smbios_type_127 {
1776 struct smbios_structure_header header;
1777 } __attribute__((__packed__));
1778
1779 static void
1780 smbios_entry_point_init(void *start,
1781 uint16_t max_structure_size,
1782 uint16_t structure_table_length,
1783 uint32_t structure_table_address,
1784 uint16_t number_of_structures)
1785 {
1786 uint8_t sum;
1787 int i;
1788 struct smbios_entry_point *ep = (struct smbios_entry_point *)start;
1789
1790 memcpy(ep->anchor_string, "_SM_", 4);
1791 ep->length = 0x1f;
1792 ep->smbios_major_version = 2;
1793 ep->smbios_minor_version = 4;
1794 ep->max_structure_size = max_structure_size;
1795 ep->entry_point_revision = 0;
1796 memset(ep->formatted_area, 0, 5);
1797 memcpy(ep->intermediate_anchor_string, "_DMI_", 5);
1798
1799 ep->structure_table_length = structure_table_length;
1800 ep->structure_table_address = structure_table_address;
1801 ep->number_of_structures = number_of_structures;
1802 ep->smbios_bcd_revision = 0x24;
1803
1804 ep->checksum = 0;
1805 ep->intermediate_checksum = 0;
1806
1807 sum = 0;
1808 for (i = 0; i < 0x10; i++)
1809 sum += ((int8_t *)start)[i];
1810 ep->checksum = -sum;
1811
1812 sum = 0;
1813 for (i = 0x10; i < ep->length; i++)
1814 sum += ((int8_t *)start)[i];
1815 ep->intermediate_checksum = -sum;
1816 }
1817
1818 /* Type 0 -- BIOS Information */
1819 #define RELEASE_DATE_STR "01/01/2007"
1820 static void *
1821 smbios_type_0_init(void *start)
1822 {
1823 struct smbios_type_0 *p = (struct smbios_type_0 *)start;
1824
1825 p->header.type = 0;
1826 p->header.length = sizeof(struct smbios_type_0);
1827 p->header.handle = 0;
1828
1829 p->vendor_str = 1;
1830 p->bios_version_str = 1;
1831 p->bios_starting_address_segment = 0xe800;
1832 p->bios_release_date_str = 2;
1833 p->bios_rom_size = 0; /* FIXME */
1834
1835 memset(p->bios_characteristics, 0, 8);
1836 p->bios_characteristics[0] = 0x08; /* BIOS characteristics not supported */
1837 p->bios_characteristics_extension_bytes[0] = 0;
1838 p->bios_characteristics_extension_bytes[1] = 0;
1839
1840 p->system_bios_major_release = 1;
1841 p->system_bios_minor_release = 0;
1842 p->embedded_controller_major_release = 0xff;
1843 p->embedded_controller_minor_release = 0xff;
1844
1845 start += sizeof(struct smbios_type_0);
1846 memcpy((char *)start, BX_APPNAME, sizeof(BX_APPNAME));
1847 start += sizeof(BX_APPNAME);
1848 memcpy((char *)start, RELEASE_DATE_STR, sizeof(RELEASE_DATE_STR));
1849 start += sizeof(RELEASE_DATE_STR);
1850 *((uint8_t *)start) = 0;
1851
1852 return start+1;
1853 }
1854
1855 /* Type 1 -- System Information */
1856 static void *
1857 smbios_type_1_init(void *start)
1858 {
1859 struct smbios_type_1 *p = (struct smbios_type_1 *)start;
1860 p->header.type = 1;
1861 p->header.length = sizeof(struct smbios_type_1);
1862 p->header.handle = 0x100;
1863
1864 p->manufacturer_str = 0;
1865 p->product_name_str = 0;
1866 p->version_str = 0;
1867 p->serial_number_str = 0;
1868
1869 memcpy(p->uuid, bios_uuid, 16);
1870
1871 p->wake_up_type = 0x06; /* power switch */
1872 p->sku_number_str = 0;
1873 p->family_str = 0;
1874
1875 start += sizeof(struct smbios_type_1);
1876 *((uint16_t *)start) = 0;
1877
1878 return start+2;
1879 }
1880
1881 /* Type 3 -- System Enclosure */
1882 static void *
1883 smbios_type_3_init(void *start)
1884 {
1885 struct smbios_type_3 *p = (struct smbios_type_3 *)start;
1886
1887 p->header.type = 3;
1888 p->header.length = sizeof(struct smbios_type_3);
1889 p->header.handle = 0x300;
1890
1891 p->manufacturer_str = 0;
1892 p->type = 0x01; /* other */
1893 p->version_str = 0;
1894 p->serial_number_str = 0;
1895 p->asset_tag_number_str = 0;
1896 p->boot_up_state = 0x03; /* safe */
1897 p->power_supply_state = 0x03; /* safe */
1898 p->thermal_state = 0x03; /* safe */
1899 p->security_status = 0x02; /* unknown */
1900 p->oem_defined = 0;
1901 p->height = 0;
1902 p->number_of_power_cords = 0;
1903 p->contained_element_count = 0;
1904
1905 start += sizeof(struct smbios_type_3);
1906 *((uint16_t *)start) = 0;
1907
1908 return start+2;
1909 }
1910
1911 /* Type 4 -- Processor Information */
1912 static void *
1913 smbios_type_4_init(void *start, unsigned int cpu_number)
1914 {
1915 struct smbios_type_4 *p = (struct smbios_type_4 *)start;
1916
1917 p->header.type = 4;
1918 p->header.length = sizeof(struct smbios_type_4);
1919 p->header.handle = 0x400 + cpu_number;
1920
1921 p->socket_designation_str = 1;
1922 p->processor_type = 0x03; /* CPU */
1923 p->processor_family = 0x01; /* other */
1924 p->processor_manufacturer_str = 0;
1925
1926 p->processor_id[0] = cpuid_signature;
1927 p->processor_id[1] = cpuid_features;
1928
1929 p->processor_version_str = 0;
1930 p->voltage = 0;
1931 p->external_clock = 0;
1932
1933 p->max_speed = 0; /* unknown */
1934 p->current_speed = 0; /* unknown */
1935
1936 p->status = 0x41; /* socket populated, CPU enabled */
1937 p->processor_upgrade = 0x01; /* other */
1938
1939 p->l1_cache_handle = 0xffff; /* cache information structure not provided */
1940 p->l2_cache_handle = 0xffff;
1941 p->l3_cache_handle = 0xffff;
1942
1943 start += sizeof(struct smbios_type_4);
1944
1945 memcpy((char *)start, "CPU " "\0" "" "\0" "", 7);
1946 ((char *)start)[4] = cpu_number + '0';
1947
1948 return start+7;
1949 }
1950
1951 /* Type 16 -- Physical Memory Array */
1952 static void *
1953 smbios_type_16_init(void *start, uint32_t memsize, int nr_mem_devs)
1954 {
1955 struct smbios_type_16 *p = (struct smbios_type_16*)start;
1956
1957 p->header.type = 16;
1958 p->header.length = sizeof(struct smbios_type_16);
1959 p->header.handle = 0x1000;
1960
1961 p->location = 0x01; /* other */
1962 p->use = 0x03; /* system memory */
1963 p->error_correction = 0x01; /* other */
1964 p->maximum_capacity = memsize * 1024;
1965 p->memory_error_information_handle = 0xfffe; /* none provided */
1966 p->number_of_memory_devices = nr_mem_devs;
1967
1968 start += sizeof(struct smbios_type_16);
1969 *((uint16_t *)start) = 0;
1970
1971 return start + 2;
1972 }
1973
1974 /* Type 17 -- Memory Device */
1975 static void *
1976 smbios_type_17_init(void *start, uint32_t memory_size_mb, int instance)
1977 {
1978 struct smbios_type_17 *p = (struct smbios_type_17 *)start;
1979
1980 p->header.type = 17;
1981 p->header.length = sizeof(struct smbios_type_17);
1982 p->header.handle = 0x1100 + instance;
1983
1984 p->physical_memory_array_handle = 0x1000;
1985 p->total_width = 64;
1986 p->data_width = 64;
1987 /* TODO: should assert in case something is wrong ASSERT((memory_size_mb & ~0x7fff) == 0); */
1988 p->size = memory_size_mb;
1989 p->form_factor = 0x09; /* DIMM */
1990 p->device_set = 0;
1991 p->device_locator_str = 1;
1992 p->bank_locator_str = 0;
1993 p->memory_type = 0x07; /* RAM */
1994 p->type_detail = 0;
1995
1996 start += sizeof(struct smbios_type_17);
1997 snprintf(start, 8, "DIMM %d", instance);
1998 start += strlen(start) + 1;
1999 *((uint8_t *)start) = 0;
2000
2001 return start+1;
2002 }
2003
2004 /* Type 19 -- Memory Array Mapped Address */
2005 static void *
2006 smbios_type_19_init(void *start, uint32_t memory_size_mb, int instance)
2007 {
2008 struct smbios_type_19 *p = (struct smbios_type_19 *)start;
2009
2010 p->header.type = 19;
2011 p->header.length = sizeof(struct smbios_type_19);
2012 p->header.handle = 0x1300 + instance;
2013
2014 p->starting_address = instance << 24;
2015 p->ending_address = p->starting_address + (memory_size_mb << 10) - 1;
2016 p->memory_array_handle = 0x1000;
2017 p->partition_width = 1;
2018
2019 start += sizeof(struct smbios_type_19);
2020 *((uint16_t *)start) = 0;
2021
2022 return start + 2;
2023 }
2024
2025 /* Type 20 -- Memory Device Mapped Address */
2026 static void *
2027 smbios_type_20_init(void *start, uint32_t memory_size_mb, int instance)
2028 {
2029 struct smbios_type_20 *p = (struct smbios_type_20 *)start;
2030
2031 p->header.type = 20;
2032 p->header.length = sizeof(struct smbios_type_20);
2033 p->header.handle = 0x1400 + instance;
2034
2035 p->starting_address = instance << 24;
2036 p->ending_address = p->starting_address + (memory_size_mb << 10) - 1;
2037 p->memory_device_handle = 0x1100 + instance;
2038 p->memory_array_mapped_address_handle = 0x1300 + instance;
2039 p->partition_row_position = 1;
2040 p->interleave_position = 0;
2041 p->interleaved_data_depth = 0;
2042
2043 start += sizeof(struct smbios_type_20);
2044
2045 *((uint16_t *)start) = 0;
2046 return start+2;
2047 }
2048
2049 /* Type 32 -- System Boot Information */
2050 static void *
2051 smbios_type_32_init(void *start)
2052 {
2053 struct smbios_type_32 *p = (struct smbios_type_32 *)start;
2054
2055 p->header.type = 32;
2056 p->header.length = sizeof(struct smbios_type_32);
2057 p->header.handle = 0x2000;
2058 memset(p->reserved, 0, 6);
2059 p->boot_status = 0; /* no errors detected */
2060
2061 start += sizeof(struct smbios_type_32);
2062 *((uint16_t *)start) = 0;
2063
2064 return start+2;
2065 }
2066
2067 /* Type 127 -- End of Table */
2068 static void *
2069 smbios_type_127_init(void *start)
2070 {
2071 struct smbios_type_127 *p = (struct smbios_type_127 *)start;
2072
2073 p->header.type = 127;
2074 p->header.length = sizeof(struct smbios_type_127);
2075 p->header.handle = 0x7f00;
2076
2077 start += sizeof(struct smbios_type_127);
2078 *((uint16_t *)start) = 0;
2079
2080 return start + 2;
2081 }
2082
2083 void smbios_init(void)
2084 {
2085 unsigned cpu_num, nr_structs = 0, max_struct_size = 0;
2086 char *start, *p, *q;
2087 int memsize = (ram_end == ram_size) ? ram_size / (1024 * 1024) :
2088 (ram_end - (1ull << 32) + ram_size) / (1024 * 1024);
2089 int i, nr_mem_devs;
2090
2091 #ifdef BX_USE_EBDA_TABLES
2092 ebda_cur_addr = align(ebda_cur_addr, 16);
2093 start = (void *)(ebda_cur_addr);
2094 #else
2095 bios_table_cur_addr = align(bios_table_cur_addr, 16);
2096 start = (void *)(bios_table_cur_addr);
2097 #endif
2098
2099 p = (char *)start + sizeof(struct smbios_entry_point);
2100
2101 #define add_struct(fn) do{ \
2102 q = (fn); \
2103 nr_structs++; \
2104 if ((q - p) > max_struct_size) \
2105 max_struct_size = q - p; \
2106 p = q; \
2107 }while (0)
2108
2109 add_struct(smbios_type_0_init(p));
2110 add_struct(smbios_type_1_init(p));
2111 add_struct(smbios_type_3_init(p));
2112 for (cpu_num = 1; cpu_num <= smp_cpus; cpu_num++)
2113 add_struct(smbios_type_4_init(p, cpu_num));
2114
2115 /* Each 'memory device' covers up to 16GB of address space. */
2116 nr_mem_devs = (memsize + 0x3fff) >> 14;
2117 add_struct(smbios_type_16_init(p, memsize, nr_mem_devs));
2118 for ( i = 0; i < nr_mem_devs; i++ )
2119 {
2120 uint32_t dev_memsize = ((i == (nr_mem_devs - 1))
2121 ? (((memsize-1) & 0x3fff)+1) : 0x4000);
2122 add_struct(smbios_type_17_init(p, dev_memsize, i));
2123 add_struct(smbios_type_19_init(p, dev_memsize, i));
2124 add_struct(smbios_type_20_init(p, dev_memsize, i));
2125 }
2126
2127 add_struct(smbios_type_32_init(p));
2128 add_struct(smbios_type_127_init(p));
2129
2130 #undef add_struct
2131
2132 smbios_entry_point_init(
2133 start, max_struct_size,
2134 (p - (char *)start) - sizeof(struct smbios_entry_point),
2135 (uint32_t)(start + sizeof(struct smbios_entry_point)),
2136 nr_structs);
2137
2138 #ifdef BX_USE_EBDA_TABLES
2139 ebda_cur_addr += (p - (char *)start);
2140 #else
2141 bios_table_cur_addr += (p - (char *)start);
2142 #endif
2143
2144 BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
2145 }
2146
2147 static uint32_t find_resume_vector(void)
2148 {
2149 unsigned long addr, start, end;
2150
2151 #ifdef BX_USE_EBDA_TABLES
2152 start = align(ebda_cur_addr, 16);
2153 end = 0xa000 << 4;
2154 #else
2155 if (bios_table_cur_addr == 0)
2156 return 0;
2157 start = align(bios_table_cur_addr, 16);
2158 end = bios_table_end_addr;
2159 #endif
2160
2161 for (addr = start; addr < end; addr += 16) {
2162 if (!memcmp((void*)addr, "RSD PTR ", 8)) {
2163 struct rsdp_descriptor *rsdp = (void*)addr;
2164 struct rsdt_descriptor_rev1 *rsdt = (void*)rsdp->rsdt_physical_address;
2165 struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[0];
2166 struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
2167 return facs->firmware_waking_vector;
2168 }
2169 }
2170
2171 return 0;
2172 }
2173
2174 static void find_440fx(PCIDevice *d)
2175 {
2176 uint16_t vendor_id, device_id;
2177
2178 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2179 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2180
2181 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441)
2182 i440_pcidev = *d;
2183 }
2184
2185 static void reinit_piix4_pm(PCIDevice *d)
2186 {
2187 uint16_t vendor_id, device_id;
2188
2189 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
2190 device_id = pci_config_readw(d, PCI_DEVICE_ID);
2191
2192 if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3)
2193 piix4_pm_enable(d);
2194 }
2195
2196 void rombios32_init(uint32_t *s3_resume_vector, uint8_t *shutdown_flag)
2197 {
2198 BX_INFO("Starting rombios32\n");
2199 BX_INFO("Shutdown flag %x\n", *shutdown_flag);
2200
2201 #ifdef BX_QEMU
2202 qemu_cfg_port = qemu_cfg_port_probe();
2203 #endif
2204
2205 init_smp_msrs();
2206
2207 ram_probe();
2208
2209 cpu_probe();
2210
2211 smp_probe();
2212
2213 find_bios_table_area();
2214
2215 if (*shutdown_flag == 0xfe) {
2216 /* redirect bios read access to RAM */
2217 pci_for_each_device(find_440fx);
2218 bios_lock_shadow_ram(); /* bios is already copied */
2219 *s3_resume_vector = find_resume_vector();
2220 if (!*s3_resume_vector) {
2221 BX_INFO("This is S3 resume but wakeup vector is NULL\n");
2222 } else {
2223 BX_INFO("S3 resume vector %p\n", *s3_resume_vector);
2224 pci_for_each_device(reinit_piix4_pm);
2225 }
2226 return;
2227 }
2228
2229 pci_bios_init();
2230
2231 if (bios_table_cur_addr != 0) {
2232
2233 mptable_init();
2234
2235 uuid_probe();
2236
2237 smbios_init();
2238
2239 if (acpi_enabled)
2240 acpi_bios_init();
2241
2242 bios_lock_shadow_ram();
2243
2244 BX_INFO("bios_table_cur_addr: 0x%08lx\n", bios_table_cur_addr);
2245 if (bios_table_cur_addr > bios_table_end_addr)
2246 BX_PANIC("bios_table_end_addr overflow!\n");
2247 #ifdef BX_USE_EBDA_TABLES
2248 BX_INFO("ebda_cur_addr: 0x%08lx\n", ebda_cur_addr);
2249 if (ebda_cur_addr > 0xA0000)
2250 BX_PANIC("ebda_cur_addr overflow!\n");
2251 #endif
2252 }
2253 }
kvm userspace components