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kvm: qemu: fix pci_enable_capabilities to set the CAP feature in pci::status
[kvm-userspace.git] / qemu / hw / vga.c
blobf0b690a7e90ccde376af100d8c827a179e73c960
1 /*
2 * QEMU VGA Emulator.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "console.h"
26 #include "pc.h"
27 #include "pci.h"
28 #include "vga_int.h"
29 #include "pixel_ops.h"
30 #include "qemu-timer.h"
31 #include "kvm.h"
32 #include "qemu-kvm.h"
33
34 //#define DEBUG_VGA
35 //#define DEBUG_VGA_MEM
36 //#define DEBUG_VGA_REG
37
38 //#define DEBUG_BOCHS_VBE
39
40 /* force some bits to zero */
41 const uint8_t sr_mask[8] = {
42 0x03,
43 0x3d,
44 0x0f,
45 0x3f,
46 0x0e,
47 0x00,
48 0x00,
49 0xff,
50 };
51
52 const uint8_t gr_mask[16] = {
53 0x0f, /* 0x00 */
54 0x0f, /* 0x01 */
55 0x0f, /* 0x02 */
56 0x1f, /* 0x03 */
57 0x03, /* 0x04 */
58 0x7b, /* 0x05 */
59 0x0f, /* 0x06 */
60 0x0f, /* 0x07 */
61 0xff, /* 0x08 */
62 0x00, /* 0x09 */
63 0x00, /* 0x0a */
64 0x00, /* 0x0b */
65 0x00, /* 0x0c */
66 0x00, /* 0x0d */
67 0x00, /* 0x0e */
68 0x00, /* 0x0f */
69 };
70
71 #define cbswap_32(__x) \
72 ((uint32_t)( \
73 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
74 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
75 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
76 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
77
78 #ifdef WORDS_BIGENDIAN
79 #define PAT(x) cbswap_32(x)
80 #else
81 #define PAT(x) (x)
82 #endif
83
84 #ifdef WORDS_BIGENDIAN
85 #define BIG 1
86 #else
87 #define BIG 0
88 #endif
89
90 #ifdef WORDS_BIGENDIAN
91 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
92 #else
93 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
94 #endif
95
96 static const uint32_t mask16[16] = {
97 PAT(0x00000000),
98 PAT(0x000000ff),
99 PAT(0x0000ff00),
100 PAT(0x0000ffff),
101 PAT(0x00ff0000),
102 PAT(0x00ff00ff),
103 PAT(0x00ffff00),
104 PAT(0x00ffffff),
105 PAT(0xff000000),
106 PAT(0xff0000ff),
107 PAT(0xff00ff00),
108 PAT(0xff00ffff),
109 PAT(0xffff0000),
110 PAT(0xffff00ff),
111 PAT(0xffffff00),
112 PAT(0xffffffff),
113 };
114
115 #undef PAT
116
117 #ifdef WORDS_BIGENDIAN
118 #define PAT(x) (x)
119 #else
120 #define PAT(x) cbswap_32(x)
121 #endif
122
123 static const uint32_t dmask16[16] = {
124 PAT(0x00000000),
125 PAT(0x000000ff),
126 PAT(0x0000ff00),
127 PAT(0x0000ffff),
128 PAT(0x00ff0000),
129 PAT(0x00ff00ff),
130 PAT(0x00ffff00),
131 PAT(0x00ffffff),
132 PAT(0xff000000),
133 PAT(0xff0000ff),
134 PAT(0xff00ff00),
135 PAT(0xff00ffff),
136 PAT(0xffff0000),
137 PAT(0xffff00ff),
138 PAT(0xffffff00),
139 PAT(0xffffffff),
140 };
141
142 static const uint32_t dmask4[4] = {
143 PAT(0x00000000),
144 PAT(0x0000ffff),
145 PAT(0xffff0000),
146 PAT(0xffffffff),
147 };
148
149 static uint32_t expand4[256];
150 static uint16_t expand2[256];
151 static uint8_t expand4to8[16];
152
153 static void vga_screen_dump(void *opaque, const char *filename);
154
155 static void vga_dumb_update_retrace_info(VGAState *s)
156 {
157 (void) s;
158 }
159
160 static void vga_precise_update_retrace_info(VGAState *s)
161 {
162 int htotal_chars;
163 int hretr_start_char;
164 int hretr_skew_chars;
165 int hretr_end_char;
166
167 int vtotal_lines;
168 int vretr_start_line;
169 int vretr_end_line;
170
171 int div2, sldiv2, dots;
172 int clocking_mode;
173 int clock_sel;
174 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
175 int64_t chars_per_sec;
176 struct vga_precise_retrace *r = &s->retrace_info.precise;
177
178 htotal_chars = s->cr[0x00] + 5;
179 hretr_start_char = s->cr[0x04];
180 hretr_skew_chars = (s->cr[0x05] >> 5) & 3;
181 hretr_end_char = s->cr[0x05] & 0x1f;
182
183 vtotal_lines = (s->cr[0x06]
184 | (((s->cr[0x07] & 1) | ((s->cr[0x07] >> 4) & 2)) << 8)) + 2
185 ;
186 vretr_start_line = s->cr[0x10]
187 | ((((s->cr[0x07] >> 2) & 1) | ((s->cr[0x07] >> 6) & 2)) << 8)
188 ;
189 vretr_end_line = s->cr[0x11] & 0xf;
190
191
192 div2 = (s->cr[0x17] >> 2) & 1;
193 sldiv2 = (s->cr[0x17] >> 3) & 1;
194
195 clocking_mode = (s->sr[0x01] >> 3) & 1;
196 clock_sel = (s->msr >> 2) & 3;
197 dots = (s->msr & 1) ? 8 : 9;
198
199 chars_per_sec = clk_hz[clock_sel] / dots;
200
201 htotal_chars <<= clocking_mode;
202
203 r->total_chars = vtotal_lines * htotal_chars;
204 if (r->freq) {
205 r->ticks_per_char = ticks_per_sec / (r->total_chars * r->freq);
206 } else {
207 r->ticks_per_char = ticks_per_sec / chars_per_sec;
208 }
209
210 r->vstart = vretr_start_line;
211 r->vend = r->vstart + vretr_end_line + 1;
212
213 r->hstart = hretr_start_char + hretr_skew_chars;
214 r->hend = r->hstart + hretr_end_char + 1;
215 r->htotal = htotal_chars;
216
217 #if 0
218 printf (
219 "hz=%f\n"
220 "htotal = %d\n"
221 "hretr_start = %d\n"
222 "hretr_skew = %d\n"
223 "hretr_end = %d\n"
224 "vtotal = %d\n"
225 "vretr_start = %d\n"
226 "vretr_end = %d\n"
227 "div2 = %d sldiv2 = %d\n"
228 "clocking_mode = %d\n"
229 "clock_sel = %d %d\n"
230 "dots = %d\n"
231 "ticks/char = %lld\n"
232 "\n",
233 (double) ticks_per_sec / (r->ticks_per_char * r->total_chars),
234 htotal_chars,
235 hretr_start_char,
236 hretr_skew_chars,
237 hretr_end_char,
238 vtotal_lines,
239 vretr_start_line,
240 vretr_end_line,
241 div2, sldiv2,
242 clocking_mode,
243 clock_sel,
244 clk_hz[clock_sel],
245 dots,
246 r->ticks_per_char
247 );
248 #endif
249 }
250
251 static uint8_t vga_precise_retrace(VGAState *s)
252 {
253 struct vga_precise_retrace *r = &s->retrace_info.precise;
254 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
255
256 if (r->total_chars) {
257 int cur_line, cur_line_char, cur_char;
258 int64_t cur_tick;
259
260 cur_tick = qemu_get_clock(vm_clock);
261
262 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
263 cur_line = cur_char / r->htotal;
264
265 if (cur_line >= r->vstart && cur_line <= r->vend) {
266 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
267 } else {
268 cur_line_char = cur_char % r->htotal;
269 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
270 val |= ST01_DISP_ENABLE;
271 }
272 }
273
274 return val;
275 } else {
276 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
277 }
278 }
279
280 static uint8_t vga_dumb_retrace(VGAState *s)
281 {
282 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
283 }
284
285 static uint32_t vga_ioport_read(void *opaque, uint32_t addr)
286 {
287 VGAState *s = opaque;
288 int val, index;
289
290 /* check port range access depending on color/monochrome mode */
291 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
292 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION))) {
293 val = 0xff;
294 } else {
295 switch(addr) {
296 case 0x3c0:
297 if (s->ar_flip_flop == 0) {
298 val = s->ar_index;
299 } else {
300 val = 0;
301 }
302 break;
303 case 0x3c1:
304 index = s->ar_index & 0x1f;
305 if (index < 21)
306 val = s->ar[index];
307 else
308 val = 0;
309 break;
310 case 0x3c2:
311 val = s->st00;
312 break;
313 case 0x3c4:
314 val = s->sr_index;
315 break;
316 case 0x3c5:
317 val = s->sr[s->sr_index];
318 #ifdef DEBUG_VGA_REG
319 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
320 #endif
321 break;
322 case 0x3c7:
323 val = s->dac_state;
324 break;
325 case 0x3c8:
326 val = s->dac_write_index;
327 break;
328 case 0x3c9:
329 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
330 if (++s->dac_sub_index == 3) {
331 s->dac_sub_index = 0;
332 s->dac_read_index++;
333 }
334 break;
335 case 0x3ca:
336 val = s->fcr;
337 break;
338 case 0x3cc:
339 val = s->msr;
340 break;
341 case 0x3ce:
342 val = s->gr_index;
343 break;
344 case 0x3cf:
345 val = s->gr[s->gr_index];
346 #ifdef DEBUG_VGA_REG
347 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
348 #endif
349 break;
350 case 0x3b4:
351 case 0x3d4:
352 val = s->cr_index;
353 break;
354 case 0x3b5:
355 case 0x3d5:
356 val = s->cr[s->cr_index];
357 #ifdef DEBUG_VGA_REG
358 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
359 #endif
360 break;
361 case 0x3ba:
362 case 0x3da:
363 /* just toggle to fool polling */
364 val = s->st01 = s->retrace(s);
365 s->ar_flip_flop = 0;
366 break;
367 default:
368 val = 0x00;
369 break;
370 }
371 }
372 #if defined(DEBUG_VGA)
373 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
374 #endif
375 return val;
376 }
377
378 static void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
379 {
380 VGAState *s = opaque;
381 int index;
382
383 /* check port range access depending on color/monochrome mode */
384 if ((addr >= 0x3b0 && addr <= 0x3bf && (s->msr & MSR_COLOR_EMULATION)) ||
385 (addr >= 0x3d0 && addr <= 0x3df && !(s->msr & MSR_COLOR_EMULATION)))
386 return;
387
388 #ifdef DEBUG_VGA
389 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
390 #endif
391
392 switch(addr) {
393 case 0x3c0:
394 if (s->ar_flip_flop == 0) {
395 val &= 0x3f;
396 s->ar_index = val;
397 } else {
398 index = s->ar_index & 0x1f;
399 switch(index) {
400 case 0x00 ... 0x0f:
401 s->ar[index] = val & 0x3f;
402 break;
403 case 0x10:
404 s->ar[index] = val & ~0x10;
405 break;
406 case 0x11:
407 s->ar[index] = val;
408 break;
409 case 0x12:
410 s->ar[index] = val & ~0xc0;
411 break;
412 case 0x13:
413 s->ar[index] = val & ~0xf0;
414 break;
415 case 0x14:
416 s->ar[index] = val & ~0xf0;
417 break;
418 default:
419 break;
420 }
421 }
422 s->ar_flip_flop ^= 1;
423 break;
424 case 0x3c2:
425 s->msr = val & ~0x10;
426 s->update_retrace_info(s);
427 break;
428 case 0x3c4:
429 s->sr_index = val & 7;
430 break;
431 case 0x3c5:
432 #ifdef DEBUG_VGA_REG
433 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
434 #endif
435 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
436 if (s->sr_index == 1) s->update_retrace_info(s);
437 break;
438 case 0x3c7:
439 s->dac_read_index = val;
440 s->dac_sub_index = 0;
441 s->dac_state = 3;
442 break;
443 case 0x3c8:
444 s->dac_write_index = val;
445 s->dac_sub_index = 0;
446 s->dac_state = 0;
447 break;
448 case 0x3c9:
449 s->dac_cache[s->dac_sub_index] = val;
450 if (++s->dac_sub_index == 3) {
451 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
452 s->dac_sub_index = 0;
453 s->dac_write_index++;
454 }
455 break;
456 case 0x3ce:
457 s->gr_index = val & 0x0f;
458 break;
459 case 0x3cf:
460 #ifdef DEBUG_VGA_REG
461 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
462 #endif
463 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
464 break;
465 case 0x3b4:
466 case 0x3d4:
467 s->cr_index = val;
468 break;
469 case 0x3b5:
470 case 0x3d5:
471 #ifdef DEBUG_VGA_REG
472 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
473 #endif
474 /* handle CR0-7 protection */
475 if ((s->cr[0x11] & 0x80) && s->cr_index <= 7) {
476 /* can always write bit 4 of CR7 */
477 if (s->cr_index == 7)
478 s->cr[7] = (s->cr[7] & ~0x10) | (val & 0x10);
479 return;
480 }
481 switch(s->cr_index) {
482 case 0x01: /* horizontal display end */
483 case 0x07:
484 case 0x09:
485 case 0x0c:
486 case 0x0d:
487 case 0x12: /* vertical display end */
488 s->cr[s->cr_index] = val;
489 break;
490 default:
491 s->cr[s->cr_index] = val;
492 break;
493 }
494
495 switch(s->cr_index) {
496 case 0x00:
497 case 0x04:
498 case 0x05:
499 case 0x06:
500 case 0x07:
501 case 0x11:
502 case 0x17:
503 s->update_retrace_info(s);
504 break;
505 }
506 break;
507 case 0x3ba:
508 case 0x3da:
509 s->fcr = val & 0x10;
510 break;
511 }
512 }
513
514 #ifdef CONFIG_BOCHS_VBE
515 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
516 {
517 VGAState *s = opaque;
518 uint32_t val;
519 val = s->vbe_index;
520 return val;
521 }
522
523 static uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
524 {
525 VGAState *s = opaque;
526 uint32_t val;
527
528 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
529 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
530 switch(s->vbe_index) {
531 /* XXX: do not hardcode ? */
532 case VBE_DISPI_INDEX_XRES:
533 val = VBE_DISPI_MAX_XRES;
534 break;
535 case VBE_DISPI_INDEX_YRES:
536 val = VBE_DISPI_MAX_YRES;
537 break;
538 case VBE_DISPI_INDEX_BPP:
539 val = VBE_DISPI_MAX_BPP;
540 break;
541 default:
542 val = s->vbe_regs[s->vbe_index];
543 break;
544 }
545 } else {
546 val = s->vbe_regs[s->vbe_index];
547 }
548 } else {
549 val = 0;
550 }
551 #ifdef DEBUG_BOCHS_VBE
552 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
553 #endif
554 return val;
555 }
556
557 static void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
558 {
559 VGAState *s = opaque;
560 s->vbe_index = val;
561 }
562
563 static void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
564 {
565 VGAState *s = opaque;
566
567 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
568 #ifdef DEBUG_BOCHS_VBE
569 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
570 #endif
571 switch(s->vbe_index) {
572 case VBE_DISPI_INDEX_ID:
573 if (val == VBE_DISPI_ID0 ||
574 val == VBE_DISPI_ID1 ||
575 val == VBE_DISPI_ID2 ||
576 val == VBE_DISPI_ID3 ||
577 val == VBE_DISPI_ID4) {
578 s->vbe_regs[s->vbe_index] = val;
579 }
580 break;
581 case VBE_DISPI_INDEX_XRES:
582 if ((val <= VBE_DISPI_MAX_XRES) && ((val & 7) == 0)) {
583 s->vbe_regs[s->vbe_index] = val;
584 }
585 break;
586 case VBE_DISPI_INDEX_YRES:
587 if (val <= VBE_DISPI_MAX_YRES) {
588 s->vbe_regs[s->vbe_index] = val;
589 }
590 break;
591 case VBE_DISPI_INDEX_BPP:
592 if (val == 0)
593 val = 8;
594 if (val == 4 || val == 8 || val == 15 ||
595 val == 16 || val == 24 || val == 32) {
596 s->vbe_regs[s->vbe_index] = val;
597 }
598 break;
599 case VBE_DISPI_INDEX_BANK:
600 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
601 val &= (s->vbe_bank_mask >> 2);
602 } else {
603 val &= s->vbe_bank_mask;
604 }
605 s->vbe_regs[s->vbe_index] = val;
606 s->bank_offset = (val << 16);
607 break;
608 case VBE_DISPI_INDEX_ENABLE:
609 if ((val & VBE_DISPI_ENABLED) &&
610 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
611 int h, shift_control;
612
613 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] =
614 s->vbe_regs[VBE_DISPI_INDEX_XRES];
615 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] =
616 s->vbe_regs[VBE_DISPI_INDEX_YRES];
617 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
618 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
619
620 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
621 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 1;
622 else
623 s->vbe_line_offset = s->vbe_regs[VBE_DISPI_INDEX_XRES] *
624 ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
625 s->vbe_start_addr = 0;
626
627 /* clear the screen (should be done in BIOS) */
628 if (!(val & VBE_DISPI_NOCLEARMEM)) {
629 memset(s->vram_ptr, 0,
630 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
631 }
632
633 /* we initialize the VGA graphic mode (should be done
634 in BIOS) */
635 s->gr[0x06] = (s->gr[0x06] & ~0x0c) | 0x05; /* graphic mode + memory map 1 */
636 s->cr[0x17] |= 3; /* no CGA modes */
637 s->cr[0x13] = s->vbe_line_offset >> 3;
638 /* width */
639 s->cr[0x01] = (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
640 /* height (only meaningful if < 1024) */
641 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
642 s->cr[0x12] = h;
643 s->cr[0x07] = (s->cr[0x07] & ~0x42) |
644 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
645 /* line compare to 1023 */
646 s->cr[0x18] = 0xff;
647 s->cr[0x07] |= 0x10;
648 s->cr[0x09] |= 0x40;
649
650 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
651 shift_control = 0;
652 s->sr[0x01] &= ~8; /* no double line */
653 } else {
654 shift_control = 2;
655 s->sr[4] |= 0x08; /* set chain 4 mode */
656 s->sr[2] |= 0x0f; /* activate all planes */
657 }
658 s->gr[0x05] = (s->gr[0x05] & ~0x60) | (shift_control << 5);
659 s->cr[0x09] &= ~0x9f; /* no double scan */
660 } else {
661 /* XXX: the bios should do that */
662 s->bank_offset = 0;
663 }
664 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
665 s->vbe_regs[s->vbe_index] = val;
666 break;
667 case VBE_DISPI_INDEX_VIRT_WIDTH:
668 {
669 int w, h, line_offset;
670
671 if (val < s->vbe_regs[VBE_DISPI_INDEX_XRES])
672 return;
673 w = val;
674 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
675 line_offset = w >> 1;
676 else
677 line_offset = w * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
678 h = s->vram_size / line_offset;
679 /* XXX: support weird bochs semantics ? */
680 if (h < s->vbe_regs[VBE_DISPI_INDEX_YRES])
681 return;
682 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = w;
683 s->vbe_regs[VBE_DISPI_INDEX_VIRT_HEIGHT] = h;
684 s->vbe_line_offset = line_offset;
685 }
686 break;
687 case VBE_DISPI_INDEX_X_OFFSET:
688 case VBE_DISPI_INDEX_Y_OFFSET:
689 {
690 int x;
691 s->vbe_regs[s->vbe_index] = val;
692 s->vbe_start_addr = s->vbe_line_offset * s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET];
693 x = s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET];
694 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4)
695 s->vbe_start_addr += x >> 1;
696 else
697 s->vbe_start_addr += x * ((s->vbe_regs[VBE_DISPI_INDEX_BPP] + 7) >> 3);
698 s->vbe_start_addr >>= 2;
699 }
700 break;
701 default:
702 break;
703 }
704 }
705 }
706 #endif
707
708 /* called for accesses between 0xa0000 and 0xc0000 */
709 uint32_t vga_mem_readb(void *opaque, target_phys_addr_t addr)
710 {
711 VGAState *s = opaque;
712 int memory_map_mode, plane;
713 uint32_t ret;
714
715 /* convert to VGA memory offset */
716 memory_map_mode = (s->gr[6] >> 2) & 3;
717 addr &= 0x1ffff;
718 switch(memory_map_mode) {
719 case 0:
720 break;
721 case 1:
722 if (addr >= 0x10000)
723 return 0xff;
724 addr += s->bank_offset;
725 break;
726 case 2:
727 addr -= 0x10000;
728 if (addr >= 0x8000)
729 return 0xff;
730 break;
731 default:
732 case 3:
733 addr -= 0x18000;
734 if (addr >= 0x8000)
735 return 0xff;
736 break;
737 }
738
739 if (s->sr[4] & 0x08) {
740 /* chain 4 mode : simplest access */
741 ret = s->vram_ptr[addr];
742 } else if (s->gr[5] & 0x10) {
743 /* odd/even mode (aka text mode mapping) */
744 plane = (s->gr[4] & 2) | (addr & 1);
745 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
746 } else {
747 /* standard VGA latched access */
748 s->latch = ((uint32_t *)s->vram_ptr)[addr];
749
750 if (!(s->gr[5] & 0x08)) {
751 /* read mode 0 */
752 plane = s->gr[4];
753 ret = GET_PLANE(s->latch, plane);
754 } else {
755 /* read mode 1 */
756 ret = (s->latch ^ mask16[s->gr[2]]) & mask16[s->gr[7]];
757 ret |= ret >> 16;
758 ret |= ret >> 8;
759 ret = (~ret) & 0xff;
760 }
761 }
762 return ret;
763 }
764
765 static uint32_t vga_mem_readw(void *opaque, target_phys_addr_t addr)
766 {
767 uint32_t v;
768 #ifdef TARGET_WORDS_BIGENDIAN
769 v = vga_mem_readb(opaque, addr) << 8;
770 v |= vga_mem_readb(opaque, addr + 1);
771 #else
772 v = vga_mem_readb(opaque, addr);
773 v |= vga_mem_readb(opaque, addr + 1) << 8;
774 #endif
775 return v;
776 }
777
778 static uint32_t vga_mem_readl(void *opaque, target_phys_addr_t addr)
779 {
780 uint32_t v;
781 #ifdef TARGET_WORDS_BIGENDIAN
782 v = vga_mem_readb(opaque, addr) << 24;
783 v |= vga_mem_readb(opaque, addr + 1) << 16;
784 v |= vga_mem_readb(opaque, addr + 2) << 8;
785 v |= vga_mem_readb(opaque, addr + 3);
786 #else
787 v = vga_mem_readb(opaque, addr);
788 v |= vga_mem_readb(opaque, addr + 1) << 8;
789 v |= vga_mem_readb(opaque, addr + 2) << 16;
790 v |= vga_mem_readb(opaque, addr + 3) << 24;
791 #endif
792 return v;
793 }
794
795 /* called for accesses between 0xa0000 and 0xc0000 */
796 void vga_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
797 {
798 VGAState *s = opaque;
799 int memory_map_mode, plane, write_mode, b, func_select, mask;
800 uint32_t write_mask, bit_mask, set_mask;
801
802 #ifdef DEBUG_VGA_MEM
803 printf("vga: [0x%x] = 0x%02x\n", addr, val);
804 #endif
805 /* convert to VGA memory offset */
806 memory_map_mode = (s->gr[6] >> 2) & 3;
807 addr &= 0x1ffff;
808 switch(memory_map_mode) {
809 case 0:
810 break;
811 case 1:
812 if (addr >= 0x10000)
813 return;
814 addr += s->bank_offset;
815 break;
816 case 2:
817 addr -= 0x10000;
818 if (addr >= 0x8000)
819 return;
820 break;
821 default:
822 case 3:
823 addr -= 0x18000;
824 if (addr >= 0x8000)
825 return;
826 break;
827 }
828
829 if (s->sr[4] & 0x08) {
830 /* chain 4 mode : simplest access */
831 plane = addr & 3;
832 mask = (1 << plane);
833 if (s->sr[2] & mask) {
834 s->vram_ptr[addr] = val;
835 #ifdef DEBUG_VGA_MEM
836 printf("vga: chain4: [0x%x]\n", addr);
837 #endif
838 s->plane_updated |= mask; /* only used to detect font change */
839 cpu_physical_memory_set_dirty(s->vram_offset + addr);
840 }
841 } else if (s->gr[5] & 0x10) {
842 /* odd/even mode (aka text mode mapping) */
843 plane = (s->gr[4] & 2) | (addr & 1);
844 mask = (1 << plane);
845 if (s->sr[2] & mask) {
846 addr = ((addr & ~1) << 1) | plane;
847 s->vram_ptr[addr] = val;
848 #ifdef DEBUG_VGA_MEM
849 printf("vga: odd/even: [0x%x]\n", addr);
850 #endif
851 s->plane_updated |= mask; /* only used to detect font change */
852 cpu_physical_memory_set_dirty(s->vram_offset + addr);
853 }
854 } else {
855 /* standard VGA latched access */
856 write_mode = s->gr[5] & 3;
857 switch(write_mode) {
858 default:
859 case 0:
860 /* rotate */
861 b = s->gr[3] & 7;
862 val = ((val >> b) | (val << (8 - b))) & 0xff;
863 val |= val << 8;
864 val |= val << 16;
865
866 /* apply set/reset mask */
867 set_mask = mask16[s->gr[1]];
868 val = (val & ~set_mask) | (mask16[s->gr[0]] & set_mask);
869 bit_mask = s->gr[8];
870 break;
871 case 1:
872 val = s->latch;
873 goto do_write;
874 case 2:
875 val = mask16[val & 0x0f];
876 bit_mask = s->gr[8];
877 break;
878 case 3:
879 /* rotate */
880 b = s->gr[3] & 7;
881 val = (val >> b) | (val << (8 - b));
882
883 bit_mask = s->gr[8] & val;
884 val = mask16[s->gr[0]];
885 break;
886 }
887
888 /* apply logical operation */
889 func_select = s->gr[3] >> 3;
890 switch(func_select) {
891 case 0:
892 default:
893 /* nothing to do */
894 break;
895 case 1:
896 /* and */
897 val &= s->latch;
898 break;
899 case 2:
900 /* or */
901 val |= s->latch;
902 break;
903 case 3:
904 /* xor */
905 val ^= s->latch;
906 break;
907 }
908
909 /* apply bit mask */
910 bit_mask |= bit_mask << 8;
911 bit_mask |= bit_mask << 16;
912 val = (val & bit_mask) | (s->latch & ~bit_mask);
913
914 do_write:
915 /* mask data according to sr[2] */
916 mask = s->sr[2];
917 s->plane_updated |= mask; /* only used to detect font change */
918 write_mask = mask16[mask];
919 ((uint32_t *)s->vram_ptr)[addr] =
920 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
921 (val & write_mask);
922 #ifdef DEBUG_VGA_MEM
923 printf("vga: latch: [0x%x] mask=0x%08x val=0x%08x\n",
924 addr * 4, write_mask, val);
925 #endif
926 cpu_physical_memory_set_dirty(s->vram_offset + (addr << 2));
927 }
928 }
929
930 static void vga_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
931 {
932 #ifdef TARGET_WORDS_BIGENDIAN
933 vga_mem_writeb(opaque, addr, (val >> 8) & 0xff);
934 vga_mem_writeb(opaque, addr + 1, val & 0xff);
935 #else
936 vga_mem_writeb(opaque, addr, val & 0xff);
937 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
938 #endif
939 }
940
941 static void vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
942 {
943 #ifdef TARGET_WORDS_BIGENDIAN
944 vga_mem_writeb(opaque, addr, (val >> 24) & 0xff);
945 vga_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
946 vga_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
947 vga_mem_writeb(opaque, addr + 3, val & 0xff);
948 #else
949 vga_mem_writeb(opaque, addr, val & 0xff);
950 vga_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
951 vga_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
952 vga_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
953 #endif
954 }
955
956 typedef void vga_draw_glyph8_func(uint8_t *d, int linesize,
957 const uint8_t *font_ptr, int h,
958 uint32_t fgcol, uint32_t bgcol);
959 typedef void vga_draw_glyph9_func(uint8_t *d, int linesize,
960 const uint8_t *font_ptr, int h,
961 uint32_t fgcol, uint32_t bgcol, int dup9);
962 typedef void vga_draw_line_func(VGAState *s1, uint8_t *d,
963 const uint8_t *s, int width);
964
965 #define DEPTH 8
966 #include "vga_template.h"
967
968 #define DEPTH 15
969 #include "vga_template.h"
970
971 #define BGR_FORMAT
972 #define DEPTH 15
973 #include "vga_template.h"
974
975 #define DEPTH 16
976 #include "vga_template.h"
977
978 #define BGR_FORMAT
979 #define DEPTH 16
980 #include "vga_template.h"
981
982 #define DEPTH 32
983 #include "vga_template.h"
984
985 #define BGR_FORMAT
986 #define DEPTH 32
987 #include "vga_template.h"
988
989 static unsigned int rgb_to_pixel8_dup(unsigned int r, unsigned int g, unsigned b)
990 {
991 unsigned int col;
992 col = rgb_to_pixel8(r, g, b);
993 col |= col << 8;
994 col |= col << 16;
995 return col;
996 }
997
998 static unsigned int rgb_to_pixel15_dup(unsigned int r, unsigned int g, unsigned b)
999 {
1000 unsigned int col;
1001 col = rgb_to_pixel15(r, g, b);
1002 col |= col << 16;
1003 return col;
1004 }
1005
1006 static unsigned int rgb_to_pixel15bgr_dup(unsigned int r, unsigned int g,
1007 unsigned int b)
1008 {
1009 unsigned int col;
1010 col = rgb_to_pixel15bgr(r, g, b);
1011 col |= col << 16;
1012 return col;
1013 }
1014
1015 static unsigned int rgb_to_pixel16_dup(unsigned int r, unsigned int g, unsigned b)
1016 {
1017 unsigned int col;
1018 col = rgb_to_pixel16(r, g, b);
1019 col |= col << 16;
1020 return col;
1021 }
1022
1023 static unsigned int rgb_to_pixel16bgr_dup(unsigned int r, unsigned int g,
1024 unsigned int b)
1025 {
1026 unsigned int col;
1027 col = rgb_to_pixel16bgr(r, g, b);
1028 col |= col << 16;
1029 return col;
1030 }
1031
1032 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1033 {
1034 unsigned int col;
1035 col = rgb_to_pixel32(r, g, b);
1036 return col;
1037 }
1038
1039 static unsigned int rgb_to_pixel32bgr_dup(unsigned int r, unsigned int g, unsigned b)
1040 {
1041 unsigned int col;
1042 col = rgb_to_pixel32bgr(r, g, b);
1043 return col;
1044 }
1045
1046 /* return true if the palette was modified */
1047 static int update_palette16(VGAState *s)
1048 {
1049 int full_update, i;
1050 uint32_t v, col, *palette;
1051
1052 full_update = 0;
1053 palette = s->last_palette;
1054 for(i = 0; i < 16; i++) {
1055 v = s->ar[i];
1056 if (s->ar[0x10] & 0x80)
1057 v = ((s->ar[0x14] & 0xf) << 4) | (v & 0xf);
1058 else
1059 v = ((s->ar[0x14] & 0xc) << 4) | (v & 0x3f);
1060 v = v * 3;
1061 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1062 c6_to_8(s->palette[v + 1]),
1063 c6_to_8(s->palette[v + 2]));
1064 if (col != palette[i]) {
1065 full_update = 1;
1066 palette[i] = col;
1067 }
1068 }
1069 return full_update;
1070 }
1071
1072 /* return true if the palette was modified */
1073 static int update_palette256(VGAState *s)
1074 {
1075 int full_update, i;
1076 uint32_t v, col, *palette;
1077
1078 full_update = 0;
1079 palette = s->last_palette;
1080 v = 0;
1081 for(i = 0; i < 256; i++) {
1082 if (s->dac_8bit) {
1083 col = s->rgb_to_pixel(s->palette[v],
1084 s->palette[v + 1],
1085 s->palette[v + 2]);
1086 } else {
1087 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1088 c6_to_8(s->palette[v + 1]),
1089 c6_to_8(s->palette[v + 2]));
1090 }
1091 if (col != palette[i]) {
1092 full_update = 1;
1093 palette[i] = col;
1094 }
1095 v += 3;
1096 }
1097 return full_update;
1098 }
1099
1100 static void vga_get_offsets(VGAState *s,
1101 uint32_t *pline_offset,
1102 uint32_t *pstart_addr,
1103 uint32_t *pline_compare)
1104 {
1105 uint32_t start_addr, line_offset, line_compare;
1106 #ifdef CONFIG_BOCHS_VBE
1107 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1108 line_offset = s->vbe_line_offset;
1109 start_addr = s->vbe_start_addr;
1110 line_compare = 65535;
1111 } else
1112 #endif
1113 {
1114 /* compute line_offset in bytes */
1115 line_offset = s->cr[0x13];
1116 line_offset <<= 3;
1117
1118 /* starting address */
1119 start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
1120
1121 /* line compare */
1122 line_compare = s->cr[0x18] |
1123 ((s->cr[0x07] & 0x10) << 4) |
1124 ((s->cr[0x09] & 0x40) << 3);
1125 }
1126 *pline_offset = line_offset;
1127 *pstart_addr = start_addr;
1128 *pline_compare = line_compare;
1129 }
1130
1131 /* update start_addr and line_offset. Return TRUE if modified */
1132 static int update_basic_params(VGAState *s)
1133 {
1134 int full_update;
1135 uint32_t start_addr, line_offset, line_compare;
1136
1137 full_update = 0;
1138
1139 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1140
1141 if (line_offset != s->line_offset ||
1142 start_addr != s->start_addr ||
1143 line_compare != s->line_compare) {
1144 s->line_offset = line_offset;
1145 s->start_addr = start_addr;
1146 s->line_compare = line_compare;
1147 full_update = 1;
1148 }
1149 return full_update;
1150 }
1151
1152 #define NB_DEPTHS 7
1153
1154 static inline int get_depth_index(DisplayState *s)
1155 {
1156 switch(ds_get_bits_per_pixel(s)) {
1157 default:
1158 case 8:
1159 return 0;
1160 case 15:
1161 return 1;
1162 case 16:
1163 return 2;
1164 case 32:
1165 if (is_surface_bgr(s->surface))
1166 return 4;
1167 else
1168 return 3;
1169 }
1170 }
1171
1172 static vga_draw_glyph8_func *vga_draw_glyph8_table[NB_DEPTHS] = {
1173 vga_draw_glyph8_8,
1174 vga_draw_glyph8_16,
1175 vga_draw_glyph8_16,
1176 vga_draw_glyph8_32,
1177 vga_draw_glyph8_32,
1178 vga_draw_glyph8_16,
1179 vga_draw_glyph8_16,
1180 };
1181
1182 static vga_draw_glyph8_func *vga_draw_glyph16_table[NB_DEPTHS] = {
1183 vga_draw_glyph16_8,
1184 vga_draw_glyph16_16,
1185 vga_draw_glyph16_16,
1186 vga_draw_glyph16_32,
1187 vga_draw_glyph16_32,
1188 vga_draw_glyph16_16,
1189 vga_draw_glyph16_16,
1190 };
1191
1192 static vga_draw_glyph9_func *vga_draw_glyph9_table[NB_DEPTHS] = {
1193 vga_draw_glyph9_8,
1194 vga_draw_glyph9_16,
1195 vga_draw_glyph9_16,
1196 vga_draw_glyph9_32,
1197 vga_draw_glyph9_32,
1198 vga_draw_glyph9_16,
1199 vga_draw_glyph9_16,
1200 };
1201
1202 static const uint8_t cursor_glyph[32 * 4] = {
1203 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1204 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1205 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1206 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1207 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1208 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1209 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1210 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1211 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1212 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1213 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1214 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1215 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1216 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1217 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1218 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1219 };
1220
1221 static void vga_get_text_resolution(VGAState *s, int *pwidth, int *pheight,
1222 int *pcwidth, int *pcheight)
1223 {
1224 int width, cwidth, height, cheight;
1225
1226 /* total width & height */
1227 cheight = (s->cr[9] & 0x1f) + 1;
1228 cwidth = 8;
1229 if (!(s->sr[1] & 0x01))
1230 cwidth = 9;
1231 if (s->sr[1] & 0x08)
1232 cwidth = 16; /* NOTE: no 18 pixel wide */
1233 width = (s->cr[0x01] + 1);
1234 if (s->cr[0x06] == 100) {
1235 /* ugly hack for CGA 160x100x16 - explain me the logic */
1236 height = 100;
1237 } else {
1238 height = s->cr[0x12] |
1239 ((s->cr[0x07] & 0x02) << 7) |
1240 ((s->cr[0x07] & 0x40) << 3);
1241 height = (height + 1) / cheight;
1242 }
1243
1244 *pwidth = width;
1245 *pheight = height;
1246 *pcwidth = cwidth;
1247 *pcheight = cheight;
1248 }
1249
1250 typedef unsigned int rgb_to_pixel_dup_func(unsigned int r, unsigned int g, unsigned b);
1251
1252 static rgb_to_pixel_dup_func *rgb_to_pixel_dup_table[NB_DEPTHS] = {
1253 rgb_to_pixel8_dup,
1254 rgb_to_pixel15_dup,
1255 rgb_to_pixel16_dup,
1256 rgb_to_pixel32_dup,
1257 rgb_to_pixel32bgr_dup,
1258 rgb_to_pixel15bgr_dup,
1259 rgb_to_pixel16bgr_dup,
1260 };
1261
1262 /*
1263 * Text mode update
1264 * Missing:
1265 * - double scan
1266 * - double width
1267 * - underline
1268 * - flashing
1269 */
1270 static void vga_draw_text(VGAState *s, int full_update)
1271 {
1272 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1273 int cx_min, cx_max, linesize, x_incr;
1274 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1275 uint8_t *d1, *d, *src, *s1, *dest, *cursor_ptr;
1276 const uint8_t *font_ptr, *font_base[2];
1277 int dup9, line_offset, depth_index;
1278 uint32_t *palette;
1279 uint32_t *ch_attr_ptr;
1280 vga_draw_glyph8_func *vga_draw_glyph8;
1281 vga_draw_glyph9_func *vga_draw_glyph9;
1282
1283 vga_dirty_log_stop(s);
1284
1285 /* compute font data address (in plane 2) */
1286 v = s->sr[3];
1287 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1288 if (offset != s->font_offsets[0]) {
1289 s->font_offsets[0] = offset;
1290 full_update = 1;
1291 }
1292 font_base[0] = s->vram_ptr + offset;
1293
1294 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1295 font_base[1] = s->vram_ptr + offset;
1296 if (offset != s->font_offsets[1]) {
1297 s->font_offsets[1] = offset;
1298 full_update = 1;
1299 }
1300 if (s->plane_updated & (1 << 2)) {
1301 /* if the plane 2 was modified since the last display, it
1302 indicates the font may have been modified */
1303 s->plane_updated = 0;
1304 full_update = 1;
1305 }
1306 full_update |= update_basic_params(s);
1307
1308 line_offset = s->line_offset;
1309 s1 = s->vram_ptr + (s->start_addr * 4);
1310
1311 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1312 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1313 if ((height * width) > CH_ATTR_SIZE) {
1314 /* better than nothing: exit if transient size is too big */
1315 return;
1316 }
1317
1318 if (width != s->last_width || height != s->last_height ||
1319 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1320 s->last_scr_width = width * cw;
1321 s->last_scr_height = height * cheight;
1322 qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height);
1323 s->last_depth = 0;
1324 s->last_width = width;
1325 s->last_height = height;
1326 s->last_ch = cheight;
1327 s->last_cw = cw;
1328 full_update = 1;
1329 }
1330 s->rgb_to_pixel =
1331 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1332 full_update |= update_palette16(s);
1333 palette = s->last_palette;
1334 x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1335
1336 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
1337 if (cursor_offset != s->cursor_offset ||
1338 s->cr[0xa] != s->cursor_start ||
1339 s->cr[0xb] != s->cursor_end) {
1340 /* if the cursor position changed, we update the old and new
1341 chars */
1342 if (s->cursor_offset < CH_ATTR_SIZE)
1343 s->last_ch_attr[s->cursor_offset] = -1;
1344 if (cursor_offset < CH_ATTR_SIZE)
1345 s->last_ch_attr[cursor_offset] = -1;
1346 s->cursor_offset = cursor_offset;
1347 s->cursor_start = s->cr[0xa];
1348 s->cursor_end = s->cr[0xb];
1349 }
1350 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1351
1352 depth_index = get_depth_index(s->ds);
1353 if (cw == 16)
1354 vga_draw_glyph8 = vga_draw_glyph16_table[depth_index];
1355 else
1356 vga_draw_glyph8 = vga_draw_glyph8_table[depth_index];
1357 vga_draw_glyph9 = vga_draw_glyph9_table[depth_index];
1358
1359 dest = ds_get_data(s->ds);
1360 linesize = ds_get_linesize(s->ds);
1361 ch_attr_ptr = s->last_ch_attr;
1362 for(cy = 0; cy < height; cy++) {
1363 d1 = dest;
1364 src = s1;
1365 cx_min = width;
1366 cx_max = -1;
1367 for(cx = 0; cx < width; cx++) {
1368 ch_attr = *(uint16_t *)src;
1369 if (full_update || ch_attr != *ch_attr_ptr) {
1370 if (cx < cx_min)
1371 cx_min = cx;
1372 if (cx > cx_max)
1373 cx_max = cx;
1374 *ch_attr_ptr = ch_attr;
1375 #ifdef WORDS_BIGENDIAN
1376 ch = ch_attr >> 8;
1377 cattr = ch_attr & 0xff;
1378 #else
1379 ch = ch_attr & 0xff;
1380 cattr = ch_attr >> 8;
1381 #endif
1382 font_ptr = font_base[(cattr >> 3) & 1];
1383 font_ptr += 32 * 4 * ch;
1384 bgcol = palette[cattr >> 4];
1385 fgcol = palette[cattr & 0x0f];
1386 if (cw != 9) {
1387 vga_draw_glyph8(d1, linesize,
1388 font_ptr, cheight, fgcol, bgcol);
1389 } else {
1390 dup9 = 0;
1391 if (ch >= 0xb0 && ch <= 0xdf && (s->ar[0x10] & 0x04))
1392 dup9 = 1;
1393 vga_draw_glyph9(d1, linesize,
1394 font_ptr, cheight, fgcol, bgcol, dup9);
1395 }
1396 if (src == cursor_ptr &&
1397 !(s->cr[0x0a] & 0x20)) {
1398 int line_start, line_last, h;
1399 /* draw the cursor */
1400 line_start = s->cr[0x0a] & 0x1f;
1401 line_last = s->cr[0x0b] & 0x1f;
1402 /* XXX: check that */
1403 if (line_last > cheight - 1)
1404 line_last = cheight - 1;
1405 if (line_last >= line_start && line_start < cheight) {
1406 h = line_last - line_start + 1;
1407 d = d1 + linesize * line_start;
1408 if (cw != 9) {
1409 vga_draw_glyph8(d, linesize,
1410 cursor_glyph, h, fgcol, bgcol);
1411 } else {
1412 vga_draw_glyph9(d, linesize,
1413 cursor_glyph, h, fgcol, bgcol, 1);
1414 }
1415 }
1416 }
1417 }
1418 d1 += x_incr;
1419 src += 4;
1420 ch_attr_ptr++;
1421 }
1422 if (cx_max != -1) {
1423 dpy_update(s->ds, cx_min * cw, cy * cheight,
1424 (cx_max - cx_min + 1) * cw, cheight);
1425 }
1426 dest += linesize * cheight;
1427 s1 += line_offset;
1428 }
1429 }
1430
1431 enum {
1432 VGA_DRAW_LINE2,
1433 VGA_DRAW_LINE2D2,
1434 VGA_DRAW_LINE4,
1435 VGA_DRAW_LINE4D2,
1436 VGA_DRAW_LINE8D2,
1437 VGA_DRAW_LINE8,
1438 VGA_DRAW_LINE15,
1439 VGA_DRAW_LINE16,
1440 VGA_DRAW_LINE24,
1441 VGA_DRAW_LINE32,
1442 VGA_DRAW_LINE_NB,
1443 };
1444
1445 static vga_draw_line_func *vga_draw_line_table[NB_DEPTHS * VGA_DRAW_LINE_NB] = {
1446 vga_draw_line2_8,
1447 vga_draw_line2_16,
1448 vga_draw_line2_16,
1449 vga_draw_line2_32,
1450 vga_draw_line2_32,
1451 vga_draw_line2_16,
1452 vga_draw_line2_16,
1453
1454 vga_draw_line2d2_8,
1455 vga_draw_line2d2_16,
1456 vga_draw_line2d2_16,
1457 vga_draw_line2d2_32,
1458 vga_draw_line2d2_32,
1459 vga_draw_line2d2_16,
1460 vga_draw_line2d2_16,
1461
1462 vga_draw_line4_8,
1463 vga_draw_line4_16,
1464 vga_draw_line4_16,
1465 vga_draw_line4_32,
1466 vga_draw_line4_32,
1467 vga_draw_line4_16,
1468 vga_draw_line4_16,
1469
1470 vga_draw_line4d2_8,
1471 vga_draw_line4d2_16,
1472 vga_draw_line4d2_16,
1473 vga_draw_line4d2_32,
1474 vga_draw_line4d2_32,
1475 vga_draw_line4d2_16,
1476 vga_draw_line4d2_16,
1477
1478 vga_draw_line8d2_8,
1479 vga_draw_line8d2_16,
1480 vga_draw_line8d2_16,
1481 vga_draw_line8d2_32,
1482 vga_draw_line8d2_32,
1483 vga_draw_line8d2_16,
1484 vga_draw_line8d2_16,
1485
1486 vga_draw_line8_8,
1487 vga_draw_line8_16,
1488 vga_draw_line8_16,
1489 vga_draw_line8_32,
1490 vga_draw_line8_32,
1491 vga_draw_line8_16,
1492 vga_draw_line8_16,
1493
1494 vga_draw_line15_8,
1495 vga_draw_line15_15,
1496 vga_draw_line15_16,
1497 vga_draw_line15_32,
1498 vga_draw_line15_32bgr,
1499 vga_draw_line15_15bgr,
1500 vga_draw_line15_16bgr,
1501
1502 vga_draw_line16_8,
1503 vga_draw_line16_15,
1504 vga_draw_line16_16,
1505 vga_draw_line16_32,
1506 vga_draw_line16_32bgr,
1507 vga_draw_line16_15bgr,
1508 vga_draw_line16_16bgr,
1509
1510 vga_draw_line24_8,
1511 vga_draw_line24_15,
1512 vga_draw_line24_16,
1513 vga_draw_line24_32,
1514 vga_draw_line24_32bgr,
1515 vga_draw_line24_15bgr,
1516 vga_draw_line24_16bgr,
1517
1518 vga_draw_line32_8,
1519 vga_draw_line32_15,
1520 vga_draw_line32_16,
1521 vga_draw_line32_32,
1522 vga_draw_line32_32bgr,
1523 vga_draw_line32_15bgr,
1524 vga_draw_line32_16bgr,
1525 };
1526
1527 static int vga_get_bpp(VGAState *s)
1528 {
1529 int ret;
1530 #ifdef CONFIG_BOCHS_VBE
1531 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1532 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1533 } else
1534 #endif
1535 {
1536 ret = 0;
1537 }
1538 return ret;
1539 }
1540
1541 static void vga_get_resolution(VGAState *s, int *pwidth, int *pheight)
1542 {
1543 int width, height;
1544
1545 #ifdef CONFIG_BOCHS_VBE
1546 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1547 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1548 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1549 } else
1550 #endif
1551 {
1552 width = (s->cr[0x01] + 1) * 8;
1553 height = s->cr[0x12] |
1554 ((s->cr[0x07] & 0x02) << 7) |
1555 ((s->cr[0x07] & 0x40) << 3);
1556 height = (height + 1);
1557 }
1558 *pwidth = width;
1559 *pheight = height;
1560 }
1561
1562 void vga_invalidate_scanlines(VGAState *s, int y1, int y2)
1563 {
1564 int y;
1565 if (y1 >= VGA_MAX_HEIGHT)
1566 return;
1567 if (y2 >= VGA_MAX_HEIGHT)
1568 y2 = VGA_MAX_HEIGHT;
1569 for(y = y1; y < y2; y++) {
1570 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1571 }
1572 }
1573
1574 static void vga_sync_dirty_bitmap(VGAState *s)
1575 {
1576 if (s->map_addr)
1577 cpu_physical_sync_dirty_bitmap(s->map_addr, s->map_end);
1578
1579 if (s->lfb_vram_mapped) {
1580 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa0000, 0xa8000);
1581 cpu_physical_sync_dirty_bitmap(isa_mem_base + 0xa8000, 0xb0000);
1582 }
1583 vga_dirty_log_start(s);
1584 }
1585
1586 /*
1587 * graphic modes
1588 */
1589 static void vga_draw_graphic(VGAState *s, int full_update)
1590 {
1591 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1592 int width, height, shift_control, line_offset, bwidth, bits;
1593 int disp_width, multi_scan, multi_run;
1594 uint8_t *d;
1595 uint32_t v, addr1, addr;
1596 long page0, page1, page_min, page_max;
1597 vga_draw_line_func *vga_draw_line;
1598
1599 full_update |= update_basic_params(s);
1600
1601 if (!full_update)
1602 vga_sync_dirty_bitmap(s);
1603
1604 s->get_resolution(s, &width, &height);
1605 disp_width = width;
1606
1607 shift_control = (s->gr[0x05] >> 5) & 3;
1608 double_scan = (s->cr[0x09] >> 7);
1609 if (shift_control != 1) {
1610 multi_scan = (((s->cr[0x09] & 0x1f) + 1) << double_scan) - 1;
1611 } else {
1612 /* in CGA modes, multi_scan is ignored */
1613 /* XXX: is it correct ? */
1614 multi_scan = double_scan;
1615 }
1616 multi_run = multi_scan;
1617 if (shift_control != s->shift_control ||
1618 double_scan != s->double_scan) {
1619 full_update = 1;
1620 s->shift_control = shift_control;
1621 s->double_scan = double_scan;
1622 }
1623
1624 if (shift_control == 0) {
1625 if (s->sr[0x01] & 8) {
1626 disp_width <<= 1;
1627 }
1628 } else if (shift_control == 1) {
1629 if (s->sr[0x01] & 8) {
1630 disp_width <<= 1;
1631 }
1632 }
1633
1634 depth = s->get_bpp(s);
1635 if (s->line_offset != s->last_line_offset ||
1636 disp_width != s->last_width ||
1637 height != s->last_height ||
1638 s->last_depth != depth) {
1639 #if defined(WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1640 if (depth == 16 || depth == 32) {
1641 #else
1642 if (depth == 32) {
1643 #endif
1644 qemu_free_displaysurface(s->ds);
1645 s->ds->surface = qemu_create_displaysurface_from(disp_width, height, depth,
1646 s->line_offset,
1647 s->vram_ptr + (s->start_addr * 4));
1648 #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
1649 s->ds->surface->pf = qemu_different_endianness_pixelformat(depth);
1650 #endif
1651 dpy_resize(s->ds);
1652 } else {
1653 qemu_console_resize(s->ds, disp_width, height);
1654 }
1655 s->last_scr_width = disp_width;
1656 s->last_scr_height = height;
1657 s->last_width = disp_width;
1658 s->last_height = height;
1659 s->last_line_offset = s->line_offset;
1660 s->last_depth = depth;
1661 full_update = 1;
1662 } else if (is_buffer_shared(s->ds->surface) &&
1663 (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) {
1664 s->ds->surface->data = s->vram_ptr + (s->start_addr * 4);
1665 dpy_setdata(s->ds);
1666 }
1667
1668 s->rgb_to_pixel =
1669 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1670
1671 if (shift_control == 0) {
1672 full_update |= update_palette16(s);
1673 if (s->sr[0x01] & 8) {
1674 v = VGA_DRAW_LINE4D2;
1675 } else {
1676 v = VGA_DRAW_LINE4;
1677 }
1678 bits = 4;
1679 } else if (shift_control == 1) {
1680 full_update |= update_palette16(s);
1681 if (s->sr[0x01] & 8) {
1682 v = VGA_DRAW_LINE2D2;
1683 } else {
1684 v = VGA_DRAW_LINE2;
1685 }
1686 bits = 4;
1687 } else {
1688 switch(s->get_bpp(s)) {
1689 default:
1690 case 0:
1691 full_update |= update_palette256(s);
1692 v = VGA_DRAW_LINE8D2;
1693 bits = 4;
1694 break;
1695 case 8:
1696 full_update |= update_palette256(s);
1697 v = VGA_DRAW_LINE8;
1698 bits = 8;
1699 break;
1700 case 15:
1701 v = VGA_DRAW_LINE15;
1702 bits = 16;
1703 break;
1704 case 16:
1705 v = VGA_DRAW_LINE16;
1706 bits = 16;
1707 break;
1708 case 24:
1709 v = VGA_DRAW_LINE24;
1710 bits = 24;
1711 break;
1712 case 32:
1713 v = VGA_DRAW_LINE32;
1714 bits = 32;
1715 break;
1716 }
1717 }
1718 vga_draw_line = vga_draw_line_table[v * NB_DEPTHS + get_depth_index(s->ds)];
1719
1720 if (!is_buffer_shared(s->ds->surface) && s->cursor_invalidate)
1721 s->cursor_invalidate(s);
1722
1723 line_offset = s->line_offset;
1724 #if 0
1725 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1726 width, height, v, line_offset, s->cr[9], s->cr[0x17], s->line_compare, s->sr[0x01]);
1727 #endif
1728 addr1 = (s->start_addr * 4);
1729 bwidth = (width * bits + 7) / 8;
1730 y_start = -1;
1731 page_min = 0x7fffffff;
1732 page_max = -1;
1733 d = ds_get_data(s->ds);
1734 linesize = ds_get_linesize(s->ds);
1735 y1 = 0;
1736 for(y = 0; y < height; y++) {
1737 addr = addr1;
1738 if (!(s->cr[0x17] & 1)) {
1739 int shift;
1740 /* CGA compatibility handling */
1741 shift = 14 + ((s->cr[0x17] >> 6) & 1);
1742 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1743 }
1744 if (!(s->cr[0x17] & 2)) {
1745 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1746 }
1747 page0 = s->vram_offset + (addr & TARGET_PAGE_MASK);
1748 page1 = s->vram_offset + ((addr + bwidth - 1) & TARGET_PAGE_MASK);
1749 update = full_update |
1750 cpu_physical_memory_get_dirty(page0, VGA_DIRTY_FLAG) |
1751 cpu_physical_memory_get_dirty(page1, VGA_DIRTY_FLAG);
1752 if ((page1 - page0) > TARGET_PAGE_SIZE) {
1753 /* if wide line, can use another page */
1754 update |= cpu_physical_memory_get_dirty(page0 + TARGET_PAGE_SIZE,
1755 VGA_DIRTY_FLAG);
1756 }
1757 /* explicit invalidation for the hardware cursor */
1758 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1759 if (update) {
1760 if (y_start < 0)
1761 y_start = y;
1762 if (page0 < page_min)
1763 page_min = page0;
1764 if (page1 > page_max)
1765 page_max = page1;
1766 if (!(is_buffer_shared(s->ds->surface))) {
1767 vga_draw_line(s, d, s->vram_ptr + addr, width);
1768 if (s->cursor_draw_line)
1769 s->cursor_draw_line(s, d, y);
1770 }
1771 } else {
1772 if (y_start >= 0) {
1773 /* flush to display */
1774 dpy_update(s->ds, 0, y_start,
1775 disp_width, y - y_start);
1776 y_start = -1;
1777 }
1778 }
1779 if (!multi_run) {
1780 mask = (s->cr[0x17] & 3) ^ 3;
1781 if ((y1 & mask) == mask)
1782 addr1 += line_offset;
1783 y1++;
1784 multi_run = multi_scan;
1785 } else {
1786 multi_run--;
1787 }
1788 /* line compare acts on the displayed lines */
1789 if (y == s->line_compare)
1790 addr1 = 0;
1791 d += linesize;
1792 }
1793 if (y_start >= 0) {
1794 /* flush to display */
1795 dpy_update(s->ds, 0, y_start,
1796 disp_width, y - y_start);
1797 }
1798 /* reset modified pages */
1799 if (page_max != -1) {
1800 cpu_physical_memory_reset_dirty(page_min, page_max + TARGET_PAGE_SIZE,
1801 VGA_DIRTY_FLAG);
1802 }
1803 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1804 }
1805
1806 static void vga_draw_blank(VGAState *s, int full_update)
1807 {
1808 int i, w, val;
1809 uint8_t *d;
1810
1811 if (!full_update)
1812 return;
1813 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1814 return;
1815 vga_dirty_log_stop(s);
1816
1817 s->rgb_to_pixel =
1818 rgb_to_pixel_dup_table[get_depth_index(s->ds)];
1819 if (ds_get_bits_per_pixel(s->ds) == 8)
1820 val = s->rgb_to_pixel(0, 0, 0);
1821 else
1822 val = 0;
1823 w = s->last_scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
1824 d = ds_get_data(s->ds);
1825 for(i = 0; i < s->last_scr_height; i++) {
1826 memset(d, val, w);
1827 d += ds_get_linesize(s->ds);
1828 }
1829 dpy_update(s->ds, 0, 0,
1830 s->last_scr_width, s->last_scr_height);
1831 }
1832
1833 #define GMODE_TEXT 0
1834 #define GMODE_GRAPH 1
1835 #define GMODE_BLANK 2
1836
1837 static void vga_update_display(void *opaque)
1838 {
1839 VGAState *s = (VGAState *)opaque;
1840 int full_update, graphic_mode;
1841
1842 if (ds_get_bits_per_pixel(s->ds) == 0) {
1843 /* nothing to do */
1844 } else {
1845 full_update = 0;
1846 if (!(s->ar_index & 0x20)) {
1847 graphic_mode = GMODE_BLANK;
1848 } else {
1849 graphic_mode = s->gr[6] & 1;
1850 }
1851 if (graphic_mode != s->graphic_mode) {
1852 s->graphic_mode = graphic_mode;
1853 full_update = 1;
1854 }
1855 switch(graphic_mode) {
1856 case GMODE_TEXT:
1857 vga_draw_text(s, full_update);
1858 break;
1859 case GMODE_GRAPH:
1860 #ifdef TARGET_IA64
1861 full_update = 1;
1862 #endif
1863 vga_draw_graphic(s, full_update);
1864 break;
1865 case GMODE_BLANK:
1866 default:
1867 vga_draw_blank(s, full_update);
1868 break;
1869 }
1870 }
1871 }
1872
1873 /* force a full display refresh */
1874 static void vga_invalidate_display(void *opaque)
1875 {
1876 VGAState *s = (VGAState *)opaque;
1877
1878 s->last_width = -1;
1879 s->last_height = -1;
1880 }
1881
1882 void vga_reset(void *opaque)
1883 {
1884 VGAState *s = (VGAState *) opaque;
1885
1886 s->lfb_addr = 0;
1887 s->lfb_end = 0;
1888 s->map_addr = 0;
1889 s->map_end = 0;
1890 s->lfb_vram_mapped = 0;
1891 s->bios_offset = 0;
1892 s->bios_size = 0;
1893 s->sr_index = 0;
1894 memset(s->sr, '\0', sizeof(s->sr));
1895 s->gr_index = 0;
1896 memset(s->gr, '\0', sizeof(s->gr));
1897 s->ar_index = 0;
1898 memset(s->ar, '\0', sizeof(s->ar));
1899 s->ar_flip_flop = 0;
1900 s->cr_index = 0;
1901 memset(s->cr, '\0', sizeof(s->cr));
1902 s->msr = 0;
1903 s->fcr = 0;
1904 s->st00 = 0;
1905 s->st01 = 0;
1906 s->dac_state = 0;
1907 s->dac_sub_index = 0;
1908 s->dac_read_index = 0;
1909 s->dac_write_index = 0;
1910 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1911 s->dac_8bit = 0;
1912 memset(s->palette, '\0', sizeof(s->palette));
1913 s->bank_offset = 0;
1914 #ifdef CONFIG_BOCHS_VBE
1915 s->vbe_index = 0;
1916 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1917 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID0;
1918 s->vbe_start_addr = 0;
1919 s->vbe_line_offset = 0;
1920 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1921 #endif
1922 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1923 s->graphic_mode = -1; /* force full update */
1924 s->shift_control = 0;
1925 s->double_scan = 0;
1926 s->line_offset = 0;
1927 s->line_compare = 0;
1928 s->start_addr = 0;
1929 s->plane_updated = 0;
1930 s->last_cw = 0;
1931 s->last_ch = 0;
1932 s->last_width = 0;
1933 s->last_height = 0;
1934 s->last_scr_width = 0;
1935 s->last_scr_height = 0;
1936 s->cursor_start = 0;
1937 s->cursor_end = 0;
1938 s->cursor_offset = 0;
1939 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1940 memset(s->last_palette, '\0', sizeof(s->last_palette));
1941 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1942 switch (vga_retrace_method) {
1943 case VGA_RETRACE_DUMB:
1944 break;
1945 case VGA_RETRACE_PRECISE:
1946 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1947 break;
1948 }
1949 }
1950
1951 #define TEXTMODE_X(x) ((x) % width)
1952 #define TEXTMODE_Y(x) ((x) / width)
1953 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1954 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1955 /* relay text rendering to the display driver
1956 * instead of doing a full vga_update_display() */
1957 static void vga_update_text(void *opaque, console_ch_t *chardata)
1958 {
1959 VGAState *s = (VGAState *) opaque;
1960 int graphic_mode, i, cursor_offset, cursor_visible;
1961 int cw, cheight, width, height, size, c_min, c_max;
1962 uint32_t *src;
1963 console_ch_t *dst, val;
1964 char msg_buffer[80];
1965 int full_update = 0;
1966
1967 if (!(s->ar_index & 0x20)) {
1968 graphic_mode = GMODE_BLANK;
1969 } else {
1970 graphic_mode = s->gr[6] & 1;
1971 }
1972 if (graphic_mode != s->graphic_mode) {
1973 s->graphic_mode = graphic_mode;
1974 full_update = 1;
1975 }
1976 if (s->last_width == -1) {
1977 s->last_width = 0;
1978 full_update = 1;
1979 }
1980
1981 switch (graphic_mode) {
1982 case GMODE_TEXT:
1983 /* TODO: update palette */
1984 full_update |= update_basic_params(s);
1985
1986 /* total width & height */
1987 cheight = (s->cr[9] & 0x1f) + 1;
1988 cw = 8;
1989 if (!(s->sr[1] & 0x01))
1990 cw = 9;
1991 if (s->sr[1] & 0x08)
1992 cw = 16; /* NOTE: no 18 pixel wide */
1993 width = (s->cr[0x01] + 1);
1994 if (s->cr[0x06] == 100) {
1995 /* ugly hack for CGA 160x100x16 - explain me the logic */
1996 height = 100;
1997 } else {
1998 height = s->cr[0x12] |
1999 ((s->cr[0x07] & 0x02) << 7) |
2000 ((s->cr[0x07] & 0x40) << 3);
2001 height = (height + 1) / cheight;
2002 }
2003
2004 size = (height * width);
2005 if (size > CH_ATTR_SIZE) {
2006 if (!full_update)
2007 return;
2008
2009 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
2010 width, height);
2011 break;
2012 }
2013
2014 if (width != s->last_width || height != s->last_height ||
2015 cw != s->last_cw || cheight != s->last_ch) {
2016 s->last_scr_width = width * cw;
2017 s->last_scr_height = height * cheight;
2018 s->ds->surface->width = width;
2019 s->ds->surface->height = height;
2020 dpy_resize(s->ds);
2021 s->last_width = width;
2022 s->last_height = height;
2023 s->last_ch = cheight;
2024 s->last_cw = cw;
2025 full_update = 1;
2026 }
2027
2028 /* Update "hardware" cursor */
2029 cursor_offset = ((s->cr[0x0e] << 8) | s->cr[0x0f]) - s->start_addr;
2030 if (cursor_offset != s->cursor_offset ||
2031 s->cr[0xa] != s->cursor_start ||
2032 s->cr[0xb] != s->cursor_end || full_update) {
2033 cursor_visible = !(s->cr[0xa] & 0x20);
2034 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
2035 dpy_cursor(s->ds,
2036 TEXTMODE_X(cursor_offset),
2037 TEXTMODE_Y(cursor_offset));
2038 else
2039 dpy_cursor(s->ds, -1, -1);
2040 s->cursor_offset = cursor_offset;
2041 s->cursor_start = s->cr[0xa];
2042 s->cursor_end = s->cr[0xb];
2043 }
2044
2045 src = (uint32_t *) s->vram_ptr + s->start_addr;
2046 dst = chardata;
2047
2048 if (full_update) {
2049 for (i = 0; i < size; src ++, dst ++, i ++)
2050 console_write_ch(dst, VMEM2CHTYPE(*src));
2051
2052 dpy_update(s->ds, 0, 0, width, height);
2053 } else {
2054 c_max = 0;
2055
2056 for (i = 0; i < size; src ++, dst ++, i ++) {
2057 console_write_ch(&val, VMEM2CHTYPE(*src));
2058 if (*dst != val) {
2059 *dst = val;
2060 c_max = i;
2061 break;
2062 }
2063 }
2064 c_min = i;
2065 for (; i < size; src ++, dst ++, i ++) {
2066 console_write_ch(&val, VMEM2CHTYPE(*src));
2067 if (*dst != val) {
2068 *dst = val;
2069 c_max = i;
2070 }
2071 }
2072
2073 if (c_min <= c_max) {
2074 i = TEXTMODE_Y(c_min);
2075 dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
2076 }
2077 }
2078
2079 return;
2080 case GMODE_GRAPH:
2081 if (!full_update)
2082 return;
2083
2084 s->get_resolution(s, &width, &height);
2085 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
2086 width, height);
2087 break;
2088 case GMODE_BLANK:
2089 default:
2090 if (!full_update)
2091 return;
2092
2093 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
2094 break;
2095 }
2096
2097 /* Display a message */
2098 s->last_width = 60;
2099 s->last_height = height = 3;
2100 dpy_cursor(s->ds, -1, -1);
2101 s->ds->surface->width = s->last_width;
2102 s->ds->surface->height = height;
2103 dpy_resize(s->ds);
2104
2105 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
2106 console_write_ch(dst ++, ' ');
2107
2108 size = strlen(msg_buffer);
2109 width = (s->last_width - size) / 2;
2110 dst = chardata + s->last_width + width;
2111 for (i = 0; i < size; i ++)
2112 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
2113
2114 dpy_update(s->ds, 0, 0, s->last_width, height);
2115 }
2116
2117 static CPUReadMemoryFunc *vga_mem_read[3] = {
2118 vga_mem_readb,
2119 vga_mem_readw,
2120 vga_mem_readl,
2121 };
2122
2123 static CPUWriteMemoryFunc *vga_mem_write[3] = {
2124 vga_mem_writeb,
2125 vga_mem_writew,
2126 vga_mem_writel,
2127 };
2128
2129 static void vga_save(QEMUFile *f, void *opaque)
2130 {
2131 VGAState *s = opaque;
2132 int i;
2133
2134 if (s->pci_dev)
2135 pci_device_save(s->pci_dev, f);
2136
2137 qemu_put_be32s(f, &s->latch);
2138 qemu_put_8s(f, &s->sr_index);
2139 qemu_put_buffer(f, s->sr, 8);
2140 qemu_put_8s(f, &s->gr_index);
2141 qemu_put_buffer(f, s->gr, 16);
2142 qemu_put_8s(f, &s->ar_index);
2143 qemu_put_buffer(f, s->ar, 21);
2144 qemu_put_be32(f, s->ar_flip_flop);
2145 qemu_put_8s(f, &s->cr_index);
2146 qemu_put_buffer(f, s->cr, 256);
2147 qemu_put_8s(f, &s->msr);
2148 qemu_put_8s(f, &s->fcr);
2149 qemu_put_byte(f, s->st00);
2150 qemu_put_8s(f, &s->st01);
2151
2152 qemu_put_8s(f, &s->dac_state);
2153 qemu_put_8s(f, &s->dac_sub_index);
2154 qemu_put_8s(f, &s->dac_read_index);
2155 qemu_put_8s(f, &s->dac_write_index);
2156 qemu_put_buffer(f, s->dac_cache, 3);
2157 qemu_put_buffer(f, s->palette, 768);
2158
2159 qemu_put_be32(f, s->bank_offset);
2160 #ifdef CONFIG_BOCHS_VBE
2161 qemu_put_byte(f, 1);
2162 qemu_put_be16s(f, &s->vbe_index);
2163 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2164 qemu_put_be16s(f, &s->vbe_regs[i]);
2165 qemu_put_be32s(f, &s->vbe_start_addr);
2166 qemu_put_be32s(f, &s->vbe_line_offset);
2167 qemu_put_be32s(f, &s->vbe_bank_mask);
2168 #else
2169 qemu_put_byte(f, 0);
2170 #endif
2171 }
2172
2173 static int vga_load(QEMUFile *f, void *opaque, int version_id)
2174 {
2175 VGAState *s = opaque;
2176 int is_vbe, i, ret;
2177
2178 if (version_id > 2)
2179 return -EINVAL;
2180
2181 if (s->pci_dev && version_id >= 2) {
2182 ret = pci_device_load(s->pci_dev, f);
2183 if (ret < 0)
2184 return ret;
2185 }
2186
2187 qemu_get_be32s(f, &s->latch);
2188 qemu_get_8s(f, &s->sr_index);
2189 qemu_get_buffer(f, s->sr, 8);
2190 qemu_get_8s(f, &s->gr_index);
2191 qemu_get_buffer(f, s->gr, 16);
2192 qemu_get_8s(f, &s->ar_index);
2193 qemu_get_buffer(f, s->ar, 21);
2194 s->ar_flip_flop=qemu_get_be32(f);
2195 qemu_get_8s(f, &s->cr_index);
2196 qemu_get_buffer(f, s->cr, 256);
2197 qemu_get_8s(f, &s->msr);
2198 qemu_get_8s(f, &s->fcr);
2199 qemu_get_8s(f, &s->st00);
2200 qemu_get_8s(f, &s->st01);
2201
2202 qemu_get_8s(f, &s->dac_state);
2203 qemu_get_8s(f, &s->dac_sub_index);
2204 qemu_get_8s(f, &s->dac_read_index);
2205 qemu_get_8s(f, &s->dac_write_index);
2206 qemu_get_buffer(f, s->dac_cache, 3);
2207 qemu_get_buffer(f, s->palette, 768);
2208
2209 s->bank_offset=qemu_get_be32(f);
2210 is_vbe = qemu_get_byte(f);
2211 #ifdef CONFIG_BOCHS_VBE
2212 if (!is_vbe)
2213 return -EINVAL;
2214 qemu_get_be16s(f, &s->vbe_index);
2215 for(i = 0; i < VBE_DISPI_INDEX_NB; i++)
2216 qemu_get_be16s(f, &s->vbe_regs[i]);
2217 qemu_get_be32s(f, &s->vbe_start_addr);
2218 qemu_get_be32s(f, &s->vbe_line_offset);
2219 qemu_get_be32s(f, &s->vbe_bank_mask);
2220 #else
2221 if (is_vbe)
2222 return -EINVAL;
2223 #endif
2224
2225 /* force refresh */
2226 s->graphic_mode = -1;
2227 return 0;
2228 }
2229
2230 typedef struct PCIVGAState {
2231 PCIDevice dev;
2232 VGAState vga_state;
2233 } PCIVGAState;
2234
2235 static int s1, s2;
2236
2237 static void mark_dirty(target_phys_addr_t start, target_phys_addr_t len)
2238 {
2239 target_phys_addr_t end = start + len;
2240
2241 while (start < end) {
2242 cpu_physical_memory_set_dirty(cpu_get_physical_page_desc(start));
2243 start += TARGET_PAGE_SIZE;
2244 }
2245 }
2246
2247 void vga_dirty_log_start(VGAState *s)
2248 {
2249 if (kvm_enabled() && s->map_addr)
2250 if (!s1) {
2251 kvm_log_start(s->map_addr, s->map_end - s->map_addr);
2252 mark_dirty(s->map_addr, s->map_end - s->map_addr);
2253 s1 = 1;
2254 }
2255 if (kvm_enabled() && s->lfb_vram_mapped) {
2256 if (!s2) {
2257 kvm_log_start(isa_mem_base + 0xa0000, 0x8000);
2258 kvm_log_start(isa_mem_base + 0xa8000, 0x8000);
2259 mark_dirty(isa_mem_base + 0xa0000, 0x10000);
2260 }
2261 s2 = 1;
2262 }
2263 }
2264
2265 void vga_dirty_log_stop(VGAState *s)
2266 {
2267 if (kvm_enabled() && s->map_addr && s1)
2268 kvm_log_stop(s->map_addr, s->map_end - s->map_addr);
2269
2270 if (kvm_enabled() && s->lfb_vram_mapped && s2) {
2271 kvm_log_stop(isa_mem_base + 0xa0000, 0x8000);
2272 kvm_log_stop(isa_mem_base + 0xa8000, 0x8000);
2273 }
2274 s1 = s2 = 0;
2275 }
2276
2277 static void vga_map(PCIDevice *pci_dev, int region_num,
2278 uint32_t addr, uint32_t size, int type)
2279 {
2280 PCIVGAState *d = (PCIVGAState *)pci_dev;
2281 VGAState *s = &d->vga_state;
2282 if (region_num == PCI_ROM_SLOT) {
2283 cpu_register_physical_memory(addr, s->bios_size, s->bios_offset);
2284 } else {
2285 cpu_register_physical_memory(addr, s->vram_size, s->vram_offset);
2286 }
2287
2288 s->map_addr = addr;
2289 s->map_end = addr + VGA_RAM_SIZE;
2290
2291 vga_dirty_log_start(s);
2292 }
2293
2294 void vga_common_init(VGAState *s, uint8_t *vga_ram_base,
2295 ram_addr_t vga_ram_offset, int vga_ram_size)
2296 {
2297 int i, j, v, b;
2298
2299 for(i = 0;i < 256; i++) {
2300 v = 0;
2301 for(j = 0; j < 8; j++) {
2302 v |= ((i >> j) & 1) << (j * 4);
2303 }
2304 expand4[i] = v;
2305
2306 v = 0;
2307 for(j = 0; j < 4; j++) {
2308 v |= ((i >> (2 * j)) & 3) << (j * 4);
2309 }
2310 expand2[i] = v;
2311 }
2312 for(i = 0; i < 16; i++) {
2313 v = 0;
2314 for(j = 0; j < 4; j++) {
2315 b = ((i >> j) & 1);
2316 v |= b << (2 * j);
2317 v |= b << (2 * j + 1);
2318 }
2319 expand4to8[i] = v;
2320 }
2321
2322 s->vram_ptr = vga_ram_base;
2323 s->vram_offset = vga_ram_offset;
2324 s->vram_size = vga_ram_size;
2325 s->get_bpp = vga_get_bpp;
2326 s->get_offsets = vga_get_offsets;
2327 s->get_resolution = vga_get_resolution;
2328 s->update = vga_update_display;
2329 s->invalidate = vga_invalidate_display;
2330 s->screen_dump = vga_screen_dump;
2331 s->text_update = vga_update_text;
2332 switch (vga_retrace_method) {
2333 case VGA_RETRACE_DUMB:
2334 s->retrace = vga_dumb_retrace;
2335 s->update_retrace_info = vga_dumb_update_retrace_info;
2336 break;
2337
2338 case VGA_RETRACE_PRECISE:
2339 s->retrace = vga_precise_retrace;
2340 s->update_retrace_info = vga_precise_update_retrace_info;
2341 break;
2342 }
2343 vga_reset(s);
2344 }
2345
2346 /* used by both ISA and PCI */
2347 void vga_init(VGAState *s)
2348 {
2349 int vga_io_memory;
2350
2351 qemu_register_reset(vga_reset, s);
2352 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2353
2354 register_ioport_write(0x3c0, 16, 1, vga_ioport_write, s);
2355
2356 register_ioport_write(0x3b4, 2, 1, vga_ioport_write, s);
2357 register_ioport_write(0x3d4, 2, 1, vga_ioport_write, s);
2358 register_ioport_write(0x3ba, 1, 1, vga_ioport_write, s);
2359 register_ioport_write(0x3da, 1, 1, vga_ioport_write, s);
2360
2361 register_ioport_read(0x3c0, 16, 1, vga_ioport_read, s);
2362
2363 register_ioport_read(0x3b4, 2, 1, vga_ioport_read, s);
2364 register_ioport_read(0x3d4, 2, 1, vga_ioport_read, s);
2365 register_ioport_read(0x3ba, 1, 1, vga_ioport_read, s);
2366 register_ioport_read(0x3da, 1, 1, vga_ioport_read, s);
2367 s->bank_offset = 0;
2368
2369 #ifdef CONFIG_BOCHS_VBE
2370 #if defined (TARGET_I386)
2371 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2372 register_ioport_read(0x1cf, 1, 2, vbe_ioport_read_data, s);
2373
2374 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2375 register_ioport_write(0x1cf, 1, 2, vbe_ioport_write_data, s);
2376
2377 /* old Bochs IO ports */
2378 register_ioport_read(0xff80, 1, 2, vbe_ioport_read_index, s);
2379 register_ioport_read(0xff81, 1, 2, vbe_ioport_read_data, s);
2380
2381 register_ioport_write(0xff80, 1, 2, vbe_ioport_write_index, s);
2382 register_ioport_write(0xff81, 1, 2, vbe_ioport_write_data, s);
2383 #else
2384 register_ioport_read(0x1ce, 1, 2, vbe_ioport_read_index, s);
2385 register_ioport_read(0x1d0, 1, 2, vbe_ioport_read_data, s);
2386
2387 register_ioport_write(0x1ce, 1, 2, vbe_ioport_write_index, s);
2388 register_ioport_write(0x1d0, 1, 2, vbe_ioport_write_data, s);
2389 #endif
2390 #endif /* CONFIG_BOCHS_VBE */
2391
2392 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2393 cpu_register_physical_memory(isa_mem_base + 0x000a0000, 0x20000,
2394 vga_io_memory);
2395 qemu_register_coalesced_mmio(isa_mem_base + 0x000a0000, 0x20000);
2396 }
2397
2398 /* Memory mapped interface */
2399 static uint32_t vga_mm_readb (void *opaque, target_phys_addr_t addr)
2400 {
2401 VGAState *s = opaque;
2402
2403 return vga_ioport_read(s, addr >> s->it_shift) & 0xff;
2404 }
2405
2406 static void vga_mm_writeb (void *opaque,
2407 target_phys_addr_t addr, uint32_t value)
2408 {
2409 VGAState *s = opaque;
2410
2411 vga_ioport_write(s, addr >> s->it_shift, value & 0xff);
2412 }
2413
2414 static uint32_t vga_mm_readw (void *opaque, target_phys_addr_t addr)
2415 {
2416 VGAState *s = opaque;
2417
2418 return vga_ioport_read(s, addr >> s->it_shift) & 0xffff;
2419 }
2420
2421 static void vga_mm_writew (void *opaque,
2422 target_phys_addr_t addr, uint32_t value)
2423 {
2424 VGAState *s = opaque;
2425
2426 vga_ioport_write(s, addr >> s->it_shift, value & 0xffff);
2427 }
2428
2429 static uint32_t vga_mm_readl (void *opaque, target_phys_addr_t addr)
2430 {
2431 VGAState *s = opaque;
2432
2433 return vga_ioport_read(s, addr >> s->it_shift);
2434 }
2435
2436 static void vga_mm_writel (void *opaque,
2437 target_phys_addr_t addr, uint32_t value)
2438 {
2439 VGAState *s = opaque;
2440
2441 vga_ioport_write(s, addr >> s->it_shift, value);
2442 }
2443
2444 static CPUReadMemoryFunc *vga_mm_read_ctrl[] = {
2445 &vga_mm_readb,
2446 &vga_mm_readw,
2447 &vga_mm_readl,
2448 };
2449
2450 static CPUWriteMemoryFunc *vga_mm_write_ctrl[] = {
2451 &vga_mm_writeb,
2452 &vga_mm_writew,
2453 &vga_mm_writel,
2454 };
2455
2456 static void vga_mm_init(VGAState *s, target_phys_addr_t vram_base,
2457 target_phys_addr_t ctrl_base, int it_shift)
2458 {
2459 int s_ioport_ctrl, vga_io_memory;
2460
2461 s->it_shift = it_shift;
2462 s_ioport_ctrl = cpu_register_io_memory(0, vga_mm_read_ctrl, vga_mm_write_ctrl, s);
2463 vga_io_memory = cpu_register_io_memory(0, vga_mem_read, vga_mem_write, s);
2464
2465 register_savevm("vga", 0, 2, vga_save, vga_load, s);
2466
2467 cpu_register_physical_memory(ctrl_base, 0x100000, s_ioport_ctrl);
2468 s->bank_offset = 0;
2469 cpu_register_physical_memory(vram_base + 0x000a0000, 0x20000, vga_io_memory);
2470 qemu_register_coalesced_mmio(vram_base + 0x000a0000, 0x20000);
2471 }
2472
2473 int isa_vga_init(uint8_t *vga_ram_base,
2474 unsigned long vga_ram_offset, int vga_ram_size)
2475 {
2476 VGAState *s;
2477
2478 s = qemu_mallocz(sizeof(VGAState));
2479
2480 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2481 vga_init(s);
2482
2483 s->ds = graphic_console_init(s->update, s->invalidate,
2484 s->screen_dump, s->text_update, s);
2485
2486 #ifdef CONFIG_BOCHS_VBE
2487 /* XXX: use optimized standard vga accesses */
2488 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2489 vga_ram_size, vga_ram_offset);
2490 #endif
2491 return 0;
2492 }
2493
2494 int isa_vga_mm_init(uint8_t *vga_ram_base,
2495 unsigned long vga_ram_offset, int vga_ram_size,
2496 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
2497 int it_shift)
2498 {
2499 VGAState *s;
2500
2501 s = qemu_mallocz(sizeof(VGAState));
2502
2503 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2504 vga_mm_init(s, vram_base, ctrl_base, it_shift);
2505
2506 s->ds = graphic_console_init(s->update, s->invalidate,
2507 s->screen_dump, s->text_update, s);
2508
2509 #ifdef CONFIG_BOCHS_VBE
2510 /* XXX: use optimized standard vga accesses */
2511 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2512 vga_ram_size, vga_ram_offset);
2513 #endif
2514 return 0;
2515 }
2516
2517 static void pci_vga_write_config(PCIDevice *d,
2518 uint32_t address, uint32_t val, int len)
2519 {
2520 PCIVGAState *pvs = container_of(d, PCIVGAState, dev);
2521 VGAState *s = &pvs->vga_state;
2522
2523 vga_dirty_log_stop(s);
2524 pci_default_write_config(d, address, val, len);
2525 if (s->map_addr && pvs->dev.io_regions[0].addr == -1)
2526 s->map_addr = 0;
2527 vga_dirty_log_start(s);
2528 }
2529
2530 int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
2531 unsigned long vga_ram_offset, int vga_ram_size,
2532 unsigned long vga_bios_offset, int vga_bios_size)
2533 {
2534 PCIVGAState *d;
2535 VGAState *s;
2536 uint8_t *pci_conf;
2537
2538 d = (PCIVGAState *)pci_register_device(bus, "VGA",
2539 sizeof(PCIVGAState),
2540 -1, NULL, pci_vga_write_config);
2541 if (!d)
2542 return -1;
2543 s = &d->vga_state;
2544
2545 vga_common_init(s, vga_ram_base, vga_ram_offset, vga_ram_size);
2546 vga_init(s);
2547
2548 s->ds = graphic_console_init(s->update, s->invalidate,
2549 s->screen_dump, s->text_update, s);
2550
2551 s->pci_dev = &d->dev;
2552
2553 pci_conf = d->dev.config;
2554 // dummy VGA (same as Bochs ID)
2555 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_QEMU);
2556 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_QEMU_VGA);
2557 pci_config_set_class(pci_conf, PCI_CLASS_DISPLAY_VGA);
2558 pci_conf[0x0e] = 0x00; // header_type
2559
2560 /* XXX: vga_ram_size must be a power of two */
2561 pci_register_io_region(&d->dev, 0, vga_ram_size,
2562 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2563 if (vga_bios_size != 0) {
2564 unsigned int bios_total_size;
2565 s->bios_offset = vga_bios_offset;
2566 s->bios_size = vga_bios_size;
2567 /* must be a power of two */
2568 bios_total_size = 1;
2569 while (bios_total_size < vga_bios_size)
2570 bios_total_size <<= 1;
2571 pci_register_io_region(&d->dev, PCI_ROM_SLOT, bios_total_size,
2572 PCI_ADDRESS_SPACE_MEM_PREFETCH, vga_map);
2573 }
2574 return 0;
2575 }
2576
2577 /********************************************************/
2578 /* vga screen dump */
2579
2580 static void vga_save_dpy_update(DisplayState *s,
2581 int x, int y, int w, int h)
2582 {
2583 }
2584
2585 static void vga_save_dpy_resize(DisplayState *s)
2586 {
2587 }
2588
2589 static void vga_save_dpy_refresh(DisplayState *s)
2590 {
2591 }
2592
2593 int ppm_save(const char *filename, struct DisplaySurface *ds)
2594 {
2595 FILE *f;
2596 uint8_t *d, *d1;
2597 uint32_t v;
2598 int y, x;
2599 uint8_t r, g, b;
2600
2601 f = fopen(filename, "wb");
2602 if (!f)
2603 return -1;
2604 fprintf(f, "P6\n%d %d\n%d\n",
2605 ds->width, ds->height, 255);
2606 d1 = ds->data;
2607 for(y = 0; y < ds->height; y++) {
2608 d = d1;
2609 for(x = 0; x < ds->width; x++) {
2610 if (ds->pf.bits_per_pixel == 32)
2611 v = *(uint32_t *)d;
2612 else
2613 v = (uint32_t) (*(uint16_t *)d);
2614 r = ((v >> ds->pf.rshift) & ds->pf.rmax) * 256 /
2615 (ds->pf.rmax + 1);
2616 g = ((v >> ds->pf.gshift) & ds->pf.gmax) * 256 /
2617 (ds->pf.gmax + 1);
2618 b = ((v >> ds->pf.bshift) & ds->pf.bmax) * 256 /
2619 (ds->pf.bmax + 1);
2620 fputc(r, f);
2621 fputc(g, f);
2622 fputc(b, f);
2623 d += ds->pf.bytes_per_pixel;
2624 }
2625 d1 += ds->linesize;
2626 }
2627 fclose(f);
2628 return 0;
2629 }
2630
2631 static void vga_screen_dump_blank(VGAState *s, const char *filename)
2632 {
2633 FILE *f;
2634 unsigned int y, x, w, h;
2635
2636 w = s->last_scr_width * sizeof(uint32_t);
2637 h = s->last_scr_height;
2638
2639 f = fopen(filename, "wb");
2640 if (!f)
2641 return;
2642 fprintf(f, "P6\n%d %d\n%d\n", w, h, 255);
2643 for (y = 0; y < h; y++) {
2644 for (x = 0; x < w; x++) {
2645 fputc(0, f);
2646 }
2647 }
2648 fclose(f);
2649 }
2650
2651 static void vga_screen_dump_common(VGAState *s, const char *filename,
2652 int w, int h)
2653 {
2654 DisplayState *saved_ds, ds1, *ds = &ds1;
2655 DisplayChangeListener dcl;
2656
2657 /* XXX: this is a little hackish */
2658 vga_invalidate_display(s);
2659 saved_ds = s->ds;
2660
2661 memset(ds, 0, sizeof(DisplayState));
2662 memset(&dcl, 0, sizeof(DisplayChangeListener));
2663 dcl.dpy_update = vga_save_dpy_update;
2664 dcl.dpy_resize = vga_save_dpy_resize;
2665 dcl.dpy_refresh = vga_save_dpy_refresh;
2666 register_displaychangelistener(ds, &dcl);
2667 ds->allocator = &default_allocator;
2668 ds->surface = qemu_create_displaysurface(ds, w, h);
2669
2670 s->ds = ds;
2671 s->graphic_mode = -1;
2672 vga_update_display(s);
2673
2674 ppm_save(filename, ds->surface);
2675
2676 qemu_free_displaysurface(ds);
2677 s->ds = saved_ds;
2678 }
2679
2680 static void vga_screen_dump_graphic(VGAState *s, const char *filename)
2681 {
2682 int w, h;
2683
2684 s->get_resolution(s, &w, &h);
2685 vga_screen_dump_common(s, filename, w, h);
2686 }
2687
2688 static void vga_screen_dump_text(VGAState *s, const char *filename)
2689 {
2690 int w, h, cwidth, cheight;
2691
2692 vga_get_text_resolution(s, &w, &h, &cwidth, &cheight);
2693 vga_screen_dump_common(s, filename, w * cwidth, h * cheight);
2694 }
2695
2696 /* save the vga display in a PPM image even if no display is
2697 available */
2698 static void vga_screen_dump(void *opaque, const char *filename)
2699 {
2700 VGAState *s = (VGAState *)opaque;
2701
2702 if (!(s->ar_index & 0x20))
2703 vga_screen_dump_blank(s, filename);
2704 else if (s->gr[6] & 1)
2705 vga_screen_dump_graphic(s, filename);
2706 else
2707 vga_screen_dump_text(s, filename);
2708 vga_invalidate_display(s);
2709 }
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