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kvm: qemu: propagate errors on failed migration.
[kvm-userspace.git] / qemu / hw / acpi.c
blob3ae858b151411c1cf8cb4333812ffd7e8147facd
1 /*
2 * ACPI implementation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
9 *
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
14 *
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
18 */
19 #include "hw.h"
20 #include "pc.h"
21 #include "pci.h"
22 #include "qemu-timer.h"
23 #include "sysemu.h"
24 #include "i2c.h"
25 #include "smbus.h"
26 #include "kvm.h"
27 #include "qemu-kvm.h"
28 #include "string.h"
29
30 //#define DEBUG
31
32 /* i82731AB (PIIX4) compatible power management function */
33 #define PM_FREQ 3579545
34
35 #define ACPI_DBG_IO_ADDR 0xb044
36
37 typedef struct PIIX4PMState {
38 PCIDevice dev;
39 uint16_t pmsts;
40 uint16_t pmen;
41 uint16_t pmcntrl;
42 uint8_t apmc;
43 uint8_t apms;
44 QEMUTimer *tmr_timer;
45 int64_t tmr_overflow_time;
46 i2c_bus *smbus;
47 uint8_t smb_stat;
48 uint8_t smb_ctl;
49 uint8_t smb_cmd;
50 uint8_t smb_addr;
51 uint8_t smb_data0;
52 uint8_t smb_data1;
53 uint8_t smb_data[32];
54 uint8_t smb_index;
55 qemu_irq irq;
56 } PIIX4PMState;
57
58 #define RSM_STS (1 << 15)
59 #define PWRBTN_STS (1 << 8)
60 #define RTC_EN (1 << 10)
61 #define PWRBTN_EN (1 << 8)
62 #define GBL_EN (1 << 5)
63 #define TMROF_EN (1 << 0)
64
65 #define SCI_EN (1 << 0)
66
67 #define SUS_EN (1 << 13)
68
69 #define ACPI_ENABLE 0xf1
70 #define ACPI_DISABLE 0xf0
71
72 #define SMBHSTSTS 0x00
73 #define SMBHSTCNT 0x02
74 #define SMBHSTCMD 0x03
75 #define SMBHSTADD 0x04
76 #define SMBHSTDAT0 0x05
77 #define SMBHSTDAT1 0x06
78 #define SMBBLKDAT 0x07
79
80 static PIIX4PMState *pm_state;
81
82 static uint32_t get_pmtmr(PIIX4PMState *s)
83 {
84 uint32_t d;
85 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
86 return d & 0xffffff;
87 }
88
89 static int get_pmsts(PIIX4PMState *s)
90 {
91 int64_t d;
92 int pmsts;
93 pmsts = s->pmsts;
94 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
95 if (d >= s->tmr_overflow_time)
96 s->pmsts |= TMROF_EN;
97 return s->pmsts;
98 }
99
100 static void pm_update_sci(PIIX4PMState *s)
101 {
102 int sci_level, pmsts;
103 int64_t expire_time;
104
105 pmsts = get_pmsts(s);
106 sci_level = (((pmsts & s->pmen) &
107 (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
108 qemu_set_irq(s->irq, sci_level);
109 /* schedule a timer interruption if needed */
110 if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
111 expire_time = muldiv64(s->tmr_overflow_time, ticks_per_sec, PM_FREQ);
112 qemu_mod_timer(s->tmr_timer, expire_time);
113 } else {
114 qemu_del_timer(s->tmr_timer);
115 }
116 }
117
118 static void pm_tmr_timer(void *opaque)
119 {
120 PIIX4PMState *s = opaque;
121 pm_update_sci(s);
122 }
123
124 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
125 {
126 PIIX4PMState *s = opaque;
127 addr &= 0x3f;
128 switch(addr) {
129 case 0x00:
130 {
131 int64_t d;
132 int pmsts;
133 pmsts = get_pmsts(s);
134 if (pmsts & val & TMROF_EN) {
135 /* if TMRSTS is reset, then compute the new overflow time */
136 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, ticks_per_sec);
137 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
138 }
139 s->pmsts &= ~val;
140 pm_update_sci(s);
141 }
142 break;
143 case 0x02:
144 s->pmen = val;
145 pm_update_sci(s);
146 break;
147 case 0x04:
148 {
149 int sus_typ;
150 s->pmcntrl = val & ~(SUS_EN);
151 if (val & SUS_EN) {
152 /* change suspend type */
153 sus_typ = (val >> 10) & 7;
154 switch(sus_typ) {
155 case 0: /* soft power off */
156 qemu_system_shutdown_request();
157 break;
158 case 1:
159 /* RSM_STS should be set on resume. Pretend that resume
160 was caused by power button */
161 s->pmsts |= (RSM_STS | PWRBTN_STS);
162 qemu_system_reset_request();
163 #if defined(TARGET_I386)
164 cmos_set_s3_resume();
165 #endif
166 default:
167 break;
168 }
169 }
170 }
171 break;
172 default:
173 break;
174 }
175 #ifdef DEBUG
176 printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
177 #endif
178 }
179
180 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
181 {
182 PIIX4PMState *s = opaque;
183 uint32_t val;
184
185 addr &= 0x3f;
186 switch(addr) {
187 case 0x00:
188 val = get_pmsts(s);
189 break;
190 case 0x02:
191 val = s->pmen;
192 break;
193 case 0x04:
194 val = s->pmcntrl;
195 break;
196 default:
197 val = 0;
198 break;
199 }
200 #ifdef DEBUG
201 printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
202 #endif
203 return val;
204 }
205
206 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
207 {
208 // PIIX4PMState *s = opaque;
209 addr &= 0x3f;
210 #ifdef DEBUG
211 printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
212 #endif
213 }
214
215 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
216 {
217 PIIX4PMState *s = opaque;
218 uint32_t val;
219
220 addr &= 0x3f;
221 switch(addr) {
222 case 0x08:
223 val = get_pmtmr(s);
224 break;
225 default:
226 val = 0;
227 break;
228 }
229 #ifdef DEBUG
230 printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
231 #endif
232 return val;
233 }
234
235 static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val)
236 {
237 PIIX4PMState *s = opaque;
238 addr &= 1;
239 #ifdef DEBUG
240 printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr, val);
241 #endif
242 if (addr == 0) {
243 s->apmc = val;
244
245 /* ACPI specs 3.0, 4.7.2.5 */
246 if (val == ACPI_ENABLE) {
247 s->pmcntrl |= SCI_EN;
248 } else if (val == ACPI_DISABLE) {
249 s->pmcntrl &= ~SCI_EN;
250 }
251
252 if (s->dev.config[0x5b] & (1 << 1)) {
253 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
254 }
255 } else {
256 s->apms = val;
257 }
258 }
259
260 static uint32_t pm_smi_readb(void *opaque, uint32_t addr)
261 {
262 PIIX4PMState *s = opaque;
263 uint32_t val;
264
265 addr &= 1;
266 if (addr == 0) {
267 val = s->apmc;
268 } else {
269 val = s->apms;
270 }
271 #ifdef DEBUG
272 printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr, val);
273 #endif
274 return val;
275 }
276
277 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
278 {
279 #if defined(DEBUG)
280 printf("ACPI: DBG: 0x%08x\n", val);
281 #endif
282 }
283
284 static void smb_transaction(PIIX4PMState *s)
285 {
286 uint8_t prot = (s->smb_ctl >> 2) & 0x07;
287 uint8_t read = s->smb_addr & 0x01;
288 uint8_t cmd = s->smb_cmd;
289 uint8_t addr = s->smb_addr >> 1;
290 i2c_bus *bus = s->smbus;
291
292 #ifdef DEBUG
293 printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
294 #endif
295 switch(prot) {
296 case 0x0:
297 smbus_quick_command(bus, addr, read);
298 break;
299 case 0x1:
300 if (read) {
301 s->smb_data0 = smbus_receive_byte(bus, addr);
302 } else {
303 smbus_send_byte(bus, addr, cmd);
304 }
305 break;
306 case 0x2:
307 if (read) {
308 s->smb_data0 = smbus_read_byte(bus, addr, cmd);
309 } else {
310 smbus_write_byte(bus, addr, cmd, s->smb_data0);
311 }
312 break;
313 case 0x3:
314 if (read) {
315 uint16_t val;
316 val = smbus_read_word(bus, addr, cmd);
317 s->smb_data0 = val;
318 s->smb_data1 = val >> 8;
319 } else {
320 smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
321 }
322 break;
323 case 0x5:
324 if (read) {
325 s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
326 } else {
327 smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
328 }
329 break;
330 default:
331 goto error;
332 }
333 return;
334
335 error:
336 s->smb_stat |= 0x04;
337 }
338
339 static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
340 {
341 PIIX4PMState *s = opaque;
342 addr &= 0x3f;
343 #ifdef DEBUG
344 printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
345 #endif
346 switch(addr) {
347 case SMBHSTSTS:
348 s->smb_stat = 0;
349 s->smb_index = 0;
350 break;
351 case SMBHSTCNT:
352 s->smb_ctl = val;
353 if (val & 0x40)
354 smb_transaction(s);
355 break;
356 case SMBHSTCMD:
357 s->smb_cmd = val;
358 break;
359 case SMBHSTADD:
360 s->smb_addr = val;
361 break;
362 case SMBHSTDAT0:
363 s->smb_data0 = val;
364 break;
365 case SMBHSTDAT1:
366 s->smb_data1 = val;
367 break;
368 case SMBBLKDAT:
369 s->smb_data[s->smb_index++] = val;
370 if (s->smb_index > 31)
371 s->smb_index = 0;
372 break;
373 default:
374 break;
375 }
376 }
377
378 static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
379 {
380 PIIX4PMState *s = opaque;
381 uint32_t val;
382
383 addr &= 0x3f;
384 switch(addr) {
385 case SMBHSTSTS:
386 val = s->smb_stat;
387 break;
388 case SMBHSTCNT:
389 s->smb_index = 0;
390 val = s->smb_ctl & 0x1f;
391 break;
392 case SMBHSTCMD:
393 val = s->smb_cmd;
394 break;
395 case SMBHSTADD:
396 val = s->smb_addr;
397 break;
398 case SMBHSTDAT0:
399 val = s->smb_data0;
400 break;
401 case SMBHSTDAT1:
402 val = s->smb_data1;
403 break;
404 case SMBBLKDAT:
405 val = s->smb_data[s->smb_index++];
406 if (s->smb_index > 31)
407 s->smb_index = 0;
408 break;
409 default:
410 val = 0;
411 break;
412 }
413 #ifdef DEBUG
414 printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
415 #endif
416 return val;
417 }
418
419 static void pm_io_space_update(PIIX4PMState *s)
420 {
421 uint32_t pm_io_base;
422
423 if (s->dev.config[0x80] & 1) {
424 pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
425 pm_io_base &= 0xffc0;
426
427 /* XXX: need to improve memory and ioport allocation */
428 #if defined(DEBUG)
429 printf("PM: mapping to 0x%x\n", pm_io_base);
430 #endif
431 register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
432 register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
433 register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
434 register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
435 }
436 }
437
438 static void pm_write_config(PCIDevice *d,
439 uint32_t address, uint32_t val, int len)
440 {
441 pci_default_write_config(d, address, val, len);
442 if (address == 0x80)
443 pm_io_space_update((PIIX4PMState *)d);
444 }
445
446 static void pm_save(QEMUFile* f,void *opaque)
447 {
448 PIIX4PMState *s = opaque;
449
450 pci_device_save(&s->dev, f);
451
452 qemu_put_be16s(f, &s->pmsts);
453 qemu_put_be16s(f, &s->pmen);
454 qemu_put_be16s(f, &s->pmcntrl);
455 qemu_put_8s(f, &s->apmc);
456 qemu_put_8s(f, &s->apms);
457 qemu_put_timer(f, s->tmr_timer);
458 qemu_put_be64(f, s->tmr_overflow_time);
459 }
460
461 static int pm_load(QEMUFile* f,void* opaque,int version_id)
462 {
463 PIIX4PMState *s = opaque;
464 int ret;
465
466 if (version_id > 1)
467 return -EINVAL;
468
469 ret = pci_device_load(&s->dev, f);
470 if (ret < 0)
471 return ret;
472
473 qemu_get_be16s(f, &s->pmsts);
474 qemu_get_be16s(f, &s->pmen);
475 qemu_get_be16s(f, &s->pmcntrl);
476 qemu_get_8s(f, &s->apmc);
477 qemu_get_8s(f, &s->apms);
478 qemu_get_timer(f, s->tmr_timer);
479 s->tmr_overflow_time=qemu_get_be64(f);
480
481 pm_io_space_update(s);
482
483 return 0;
484 }
485
486 static void piix4_reset(void *opaque)
487 {
488 PIIX4PMState *s = opaque;
489 uint8_t *pci_conf = s->dev.config;
490
491 pci_conf[0x58] = 0;
492 pci_conf[0x59] = 0;
493 pci_conf[0x5a] = 0;
494 pci_conf[0x5b] = 0;
495 }
496
497 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
498 qemu_irq sci_irq)
499 {
500 PIIX4PMState *s;
501 uint8_t *pci_conf;
502
503 s = (PIIX4PMState *)pci_register_device(bus,
504 "PM", sizeof(PIIX4PMState),
505 devfn, NULL, pm_write_config);
506 pm_state = s;
507 pci_conf = s->dev.config;
508 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
509 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
510 pci_conf[0x06] = 0x80;
511 pci_conf[0x07] = 0x02;
512 pci_conf[0x08] = 0x03; // revision number
513 pci_conf[0x09] = 0x00;
514 pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
515 pci_conf[0x0e] = 0x00; // header_type
516 pci_conf[0x3d] = 0x01; // interrupt pin 1
517
518 pci_conf[0x40] = 0x01; /* PM io base read only bit */
519
520 #if defined(TARGET_IA64)
521 pci_conf[0x40] = 0x41; /* PM io base read only bit */
522 pci_conf[0x41] = 0x1f;
523 pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
524 s->pmcntrl = SCI_EN;
525 #endif
526
527 register_ioport_write(0xb2, 2, 1, pm_smi_writeb, s);
528 register_ioport_read(0xb2, 2, 1, pm_smi_readb, s);
529
530 register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
531
532 if (kvm_enabled()) {
533 /* Mark SMM as already inited to prevent SMM from running. KVM does not
534 * support SMM mode. */
535 pci_conf[0x5B] = 0x02;
536 }
537
538 /* XXX: which specification is used ? The i82731AB has different
539 mappings */
540 pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
541 pci_conf[0x63] = 0x60;
542 pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
543 (serial_hds[1] != NULL ? 0x90 : 0);
544
545 pci_conf[0x90] = smb_io_base | 1;
546 pci_conf[0x91] = smb_io_base >> 8;
547 pci_conf[0xd2] = 0x09;
548 register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
549 register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
550
551 s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
552
553 register_savevm("piix4_pm", 0, 1, pm_save, pm_load, s);
554
555 s->smbus = i2c_init_bus();
556 s->irq = sci_irq;
557 qemu_register_reset(piix4_reset, s);
558
559 return s->smbus;
560 }
561
562 #if defined(TARGET_I386)
563 void qemu_system_powerdown(void)
564 {
565 if (!pm_state) {
566 qemu_system_shutdown_request();
567 } else if (pm_state->pmen & PWRBTN_EN) {
568 pm_state->pmsts |= PWRBTN_EN;
569 pm_update_sci(pm_state);
570 }
571 }
572 #endif
573
574 #define GPE_BASE 0xafe0
575 #define PROC_BASE 0xaf00
576 #define PCI_BASE 0xae00
577 #define PCI_EJ_BASE 0xae08
578
579 struct gpe_regs {
580 uint16_t sts; /* status */
581 uint16_t en; /* enabled */
582 uint8_t cpus_sts[32];
583 };
584
585 struct pci_status {
586 uint32_t up;
587 uint32_t down;
588 };
589
590 static struct gpe_regs gpe;
591 static struct pci_status pci0_status;
592
593 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
594 {
595 if (addr & 1)
596 return (val >> 8) & 0xff;
597 return val & 0xff;
598 }
599
600 static uint32_t gpe_readb(void *opaque, uint32_t addr)
601 {
602 uint32_t val = 0;
603 struct gpe_regs *g = opaque;
604 switch (addr) {
605 case PROC_BASE ... PROC_BASE+31:
606 val = g->cpus_sts[addr - PROC_BASE];
607 break;
608
609 case GPE_BASE:
610 case GPE_BASE + 1:
611 val = gpe_read_val(g->sts, addr);
612 break;
613 case GPE_BASE + 2:
614 case GPE_BASE + 3:
615 val = gpe_read_val(g->en, addr);
616 break;
617 default:
618 break;
619 }
620
621 #if defined(DEBUG)
622 printf("gpe read %x == %x\n", addr, val);
623 #endif
624 return val;
625 }
626
627 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
628 {
629 if (addr & 1)
630 *cur = (*cur & 0xff) | (val << 8);
631 else
632 *cur = (*cur & 0xff00) | (val & 0xff);
633 }
634
635 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
636 {
637 uint16_t x1, x0 = val & 0xff;
638 int shift = (addr & 1) ? 8 : 0;
639
640 x1 = (*cur >> shift) & 0xff;
641
642 x1 = x1 & ~x0;
643
644 *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
645 }
646
647 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
648 {
649 struct gpe_regs *g = opaque;
650 switch (addr) {
651 case PROC_BASE ... PROC_BASE + 31:
652 /* don't allow to change cpus_sts from inside a guest */
653 break;
654
655 case GPE_BASE:
656 case GPE_BASE + 1:
657 gpe_reset_val(&g->sts, addr, val);
658 break;
659 case GPE_BASE + 2:
660 case GPE_BASE + 3:
661 gpe_write_val(&g->en, addr, val);
662 break;
663 default:
664 break;
665 }
666
667 #if defined(DEBUG)
668 printf("gpe write %x <== %d\n", addr, val);
669 #endif
670 }
671
672 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
673 {
674 uint32_t val = 0;
675 struct pci_status *g = opaque;
676 switch (addr) {
677 case PCI_BASE:
678 val = g->up;
679 break;
680 case PCI_BASE + 4:
681 val = g->down;
682 break;
683 default:
684 break;
685 }
686
687 #if defined(DEBUG)
688 printf("pcihotplug read %x == %x\n", addr, val);
689 #endif
690 return val;
691 }
692
693 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
694 {
695 struct pci_status *g = opaque;
696 switch (addr) {
697 case PCI_BASE:
698 g->up = val;
699 break;
700 case PCI_BASE + 4:
701 g->down = val;
702 break;
703 }
704
705 #if defined(DEBUG)
706 printf("pcihotplug write %x <== %d\n", addr, val);
707 #endif
708 }
709
710 static uint32_t pciej_read(void *opaque, uint32_t addr)
711 {
712 #if defined(DEBUG)
713 printf("pciej read %x\n", addr);
714 #endif
715 return 0;
716 }
717
718 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
719 {
720 #if defined (TARGET_I386)
721 int slot = ffs(val) - 1;
722
723 pci_device_hot_remove_success(0, slot);
724 #endif
725
726 #if defined(DEBUG)
727 printf("pciej write %x <== %d\n", addr, val);
728 #endif
729 }
730
731 static const char *model;
732
733 void qemu_system_hot_add_init(const char *cpu_model)
734 {
735 int i = 0, cpus = smp_cpus;
736
737 while (cpus > 0) {
738 gpe.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
739 cpus -= 8;
740 }
741 register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
742 register_ioport_read(GPE_BASE, 4, 1, gpe_readb, &gpe);
743
744 register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, &gpe);
745 register_ioport_read(PROC_BASE, 32, 1, gpe_readb, &gpe);
746
747 register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
748 register_ioport_read(PCI_BASE, 8, 4, pcihotplug_read, &pci0_status);
749
750 register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, NULL);
751 register_ioport_read(PCI_EJ_BASE, 4, 4, pciej_read, NULL);
752
753 model = cpu_model;
754 }
755
756 static void enable_processor(struct gpe_regs *g, int cpu)
757 {
758 g->sts |= 4;
759 g->cpus_sts[cpu/8] |= (1 << (cpu%8));
760 }
761
762 static void disable_processor(struct gpe_regs *g, int cpu)
763 {
764 g->sts |= 4;
765 g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
766 }
767
768 #if defined(TARGET_I386) || defined(TARGET_X86_64)
769 #ifdef USE_KVM
770 static CPUState *qemu_kvm_cpu_env(int index)
771 {
772 CPUState *penv;
773
774 penv = first_cpu;
775
776 while (penv) {
777 if (penv->cpu_index == index)
778 return penv;
779 penv = (CPUState *)penv->next_cpu;
780 }
781
782 return NULL;
783 }
784 #endif
785
786
787 void qemu_system_cpu_hot_add(int cpu, int state)
788 {
789 CPUState *env;
790
791 if (state
792 #ifdef USE_KVM
793 && (!qemu_kvm_cpu_env(cpu))
794 #endif
795 ) {
796 env = pc_new_cpu(cpu, model, 1);
797 if (!env) {
798 fprintf(stderr, "cpu %d creation failed\n", cpu);
799 return;
800 }
801 }
802
803 if (state)
804 enable_processor(&gpe, cpu);
805 else
806 disable_processor(&gpe, cpu);
807 if (gpe.en & 4) {
808 qemu_set_irq(pm_state->irq, 1);
809 qemu_set_irq(pm_state->irq, 0);
810 }
811 }
812 #endif
813
814 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
815 {
816 g->sts |= 2;
817 p->up |= (1 << slot);
818 }
819
820 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
821 {
822 g->sts |= 2;
823 p->down |= (1 << slot);
824 }
825
826 void qemu_system_device_hot_add(int bus, int slot, int state)
827 {
828 pci0_status.up = 0;
829 pci0_status.down = 0;
830 if (state)
831 enable_device(&pci0_status, &gpe, slot);
832 else
833 disable_device(&pci0_status, &gpe, slot);
834 if (gpe.en & 2) {
835 qemu_set_irq(pm_state->irq, 1);
836 qemu_set_irq(pm_state->irq, 0);
837 }
838 }
839
840 struct acpi_table_header
841 {
842 char signature [4]; /* ACPI signature (4 ASCII characters) */
843 uint32_t length; /* Length of table, in bytes, including header */
844 uint8_t revision; /* ACPI Specification minor version # */
845 uint8_t checksum; /* To make sum of entire table == 0 */
846 char oem_id [6]; /* OEM identification */
847 char oem_table_id [8]; /* OEM table identification */
848 uint32_t oem_revision; /* OEM revision number */
849 char asl_compiler_id [4]; /* ASL compiler vendor ID */
850 uint32_t asl_compiler_revision; /* ASL compiler revision number */
851 } __attribute__((packed));
852
853 char *acpi_tables;
854 size_t acpi_tables_len;
855
856 static int acpi_checksum(const uint8_t *data, int len)
857 {
858 int sum, i;
859 sum = 0;
860 for(i = 0; i < len; i++)
861 sum += data[i];
862 return (-sum) & 0xff;
863 }
864
865 int acpi_table_add(const char *t)
866 {
867 static const char *dfl_id = "QEMUQEMU";
868 char buf[1024], *p, *f;
869 struct acpi_table_header acpi_hdr;
870 unsigned long val;
871 size_t off;
872
873 memset(&acpi_hdr, 0, sizeof(acpi_hdr));
874
875 if (get_param_value(buf, sizeof(buf), "sig", t)) {
876 strncpy(acpi_hdr.signature, buf, 4);
877 } else {
878 strncpy(acpi_hdr.signature, dfl_id, 4);
879 }
880 if (get_param_value(buf, sizeof(buf), "rev", t)) {
881 val = strtoul(buf, &p, 10);
882 if (val > 255 || *p != '\0')
883 goto out;
884 } else {
885 val = 1;
886 }
887 acpi_hdr.revision = (int8_t)val;
888
889 if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
890 strncpy(acpi_hdr.oem_id, buf, 6);
891 } else {
892 strncpy(acpi_hdr.oem_id, dfl_id, 6);
893 }
894
895 if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
896 strncpy(acpi_hdr.oem_table_id, buf, 8);
897 } else {
898 strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
899 }
900
901 if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
902 val = strtol(buf, &p, 10);
903 if(*p != '\0')
904 goto out;
905 } else {
906 val = 1;
907 }
908 acpi_hdr.oem_revision = cpu_to_le32(val);
909
910 if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
911 strncpy(acpi_hdr.asl_compiler_id, buf, 4);
912 } else {
913 strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
914 }
915
916 if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
917 val = strtol(buf, &p, 10);
918 if(*p != '\0')
919 goto out;
920 } else {
921 val = 1;
922 }
923 acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
924
925 if (!get_param_value(buf, sizeof(buf), "data", t)) {
926 buf[0] = '\0';
927 }
928
929 acpi_hdr.length = sizeof(acpi_hdr);
930
931 f = buf;
932 while (buf[0]) {
933 struct stat s;
934 char *n = strchr(f, ':');
935 if (n)
936 *n = '\0';
937 if(stat(f, &s) < 0) {
938 fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
939 goto out;
940 }
941 acpi_hdr.length += s.st_size;
942 if (!n)
943 break;
944 *n = ':';
945 f = n + 1;
946 }
947
948 if (!acpi_tables) {
949 acpi_tables_len = sizeof(uint16_t);
950 acpi_tables = qemu_mallocz(acpi_tables_len);
951 }
952 p = acpi_tables + acpi_tables_len;
953 acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
954 acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len);
955
956 acpi_hdr.length = cpu_to_le32(acpi_hdr.length);
957 *(uint16_t*)p = acpi_hdr.length;
958 p += sizeof(uint16_t);
959 memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
960 off = sizeof(acpi_hdr);
961
962 f = buf;
963 while (buf[0]) {
964 struct stat s;
965 int fd;
966 char *n = strchr(f, ':');
967 if (n)
968 *n = '\0';
969 fd = open(f, O_RDONLY);
970
971 if(fd < 0)
972 goto out;
973 if(fstat(fd, &s) < 0) {
974 close(fd);
975 goto out;
976 }
977
978 do {
979 int r;
980 r = read(fd, p + off, s.st_size);
981 if (r > 0) {
982 off += r;
983 s.st_size -= r;
984 } else if ((r < 0 && errno != EINTR) || r == 0) {
985 close(fd);
986 goto out;
987 }
988 } while(s.st_size);
989
990 close(fd);
991 if (!n)
992 break;
993 f = n + 1;
994 }
995
996 ((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
997 /* increase number of tables */
998 (*(uint16_t*)acpi_tables) =
999 cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
1000 return 0;
1001 out:
1002 if (acpi_tables) {
1003 free(acpi_tables);
1004 acpi_tables = NULL;
1005 }
1006 return -1;
1007 }
kvm userspace components