qemu/hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
  19  */
  20 #include "hw.h"
  21 #include "pc.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24
  25 #include "qemu-kvm.h"
  26
  27 //#define DEBUG_APIC
  28
  29 /* APIC Local Vector Table */
  30 #define APIC_LVT_TIMER   0
  31 #define APIC_LVT_THERMAL 1
  32 #define APIC_LVT_PERFORM 2
  33 #define APIC_LVT_LINT0   3
  34 #define APIC_LVT_LINT1   4
  35 #define APIC_LVT_ERROR   5
  36 #define APIC_LVT_NB      6
  37
  38 /* APIC delivery modes */
  39 #define APIC_DM_FIXED   0
  40 #define APIC_DM_LOWPRI  1
  41 #define APIC_DM_SMI     2
  42 #define APIC_DM_NMI     4
  43 #define APIC_DM_INIT    5
  44 #define APIC_DM_SIPI    6
  45 #define APIC_DM_EXTINT  7
  46
  47 /* APIC destination mode */
  48 #define APIC_DESTMODE_FLAT      0xf
  49 #define APIC_DESTMODE_CLUSTER   1
  50
  51 #define APIC_TRIGGER_EDGE  0
  52 #define APIC_TRIGGER_LEVEL 1
  53
  54 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  55 #define APIC_LVT_MASKED                 (1<<16)
  56 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  57 #define APIC_LVT_REMOTE_IRR             (1<<14)
  58 #define APIC_INPUT_POLARITY             (1<<13)
  59 #define APIC_SEND_PENDING               (1<<12)
  60
  61 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  62
  63 #define APIC_SV_ENABLE (1 << 8)
  64
  65 #define MAX_APICS 255
  66 #define MAX_APIC_WORDS 8
  67
  68 typedef struct APICState {
  69     CPUState *cpu_env;
  70     uint32_t apicbase;
  71     uint8_t id;
  72     uint8_t arb_id;
  73     uint8_t tpr;
  74     uint32_t spurious_vec;
  75     uint8_t log_dest;
  76     uint8_t dest_mode;
  77     uint32_t isr[8];  /* in service register */
  78     uint32_t tmr[8];  /* trigger mode register */
  79     uint32_t irr[8]; /* interrupt request register */
  80     uint32_t lvt[APIC_LVT_NB];
  81     uint32_t esr; /* error register */
  82     uint32_t icr[2];
  83
  84     uint32_t divide_conf;
  85     int count_shift;
  86     uint32_t initial_count;
  87     int64_t initial_count_load_time, next_time;
  88     QEMUTimer *timer;
  89 } APICState;
  90
  91 static int apic_io_memory;
  92 static APICState *local_apics[MAX_APICS + 1];
  93 static int last_apic_id = 0;
  94 static int apic_irq_delivered;
  95
  96
  97 static void apic_init_ipi(APICState *s);
  98 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
  99 static void apic_update_irq(APICState *s);
 100 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 101                                       uint8_t dest, uint8_t dest_mode);
 102
 103 /* Find first bit starting from msb */
 104 static int fls_bit(uint32_t value)
 105 {
 106     return 31 - clz32(value);
 107 }
 108
 109 /* Find first bit starting from lsb */
 110 static int ffs_bit(uint32_t value)
 111 {
 112     return ctz32(value);
 113 }
 114
 115 static inline void set_bit(uint32_t *tab, int index)
 116 {
 117     int i, mask;
 118     i = index >> 5;
 119     mask = 1 << (index & 0x1f);
 120     tab[i] |= mask;
 121 }
 122
 123 static inline void reset_bit(uint32_t *tab, int index)
 124 {
 125     int i, mask;
 126     i = index >> 5;
 127     mask = 1 << (index & 0x1f);
 128     tab[i] &= ~mask;
 129 }
 130
 131 static inline int get_bit(uint32_t *tab, int index)
 132 {
 133     int i, mask;
 134     i = index >> 5;
 135     mask = 1 << (index & 0x1f);
 136     return !!(tab[i] & mask);
 137 }
 138
 139 static void apic_local_deliver(CPUState *env, int vector)
 140 {
 141     APICState *s = env->apic_state;
 142     uint32_t lvt = s->lvt[vector];
 143     int trigger_mode;
 144
 145     if (lvt & APIC_LVT_MASKED)
 146         return;
 147
 148     switch ((lvt >> 8) & 7) {
 149     case APIC_DM_SMI:
 150         cpu_interrupt(env, CPU_INTERRUPT_SMI);
 151         break;
 152
 153     case APIC_DM_NMI:
 154         cpu_interrupt(env, CPU_INTERRUPT_NMI);
 155         break;
 156
 157     case APIC_DM_EXTINT:
 158         cpu_interrupt(env, CPU_INTERRUPT_HARD);
 159         break;
 160
 161     case APIC_DM_FIXED:
 162         trigger_mode = APIC_TRIGGER_EDGE;
 163         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 164             (lvt & APIC_LVT_LEVEL_TRIGGER))
 165             trigger_mode = APIC_TRIGGER_LEVEL;
 166         apic_set_irq(s, lvt & 0xff, trigger_mode);
 167     }
 168 }
 169
 170 void apic_deliver_pic_intr(CPUState *env, int level)
 171 {
 172     if (level)
 173         apic_local_deliver(env, APIC_LVT_LINT0);
 174     else {
 175         APICState *s = env->apic_state;
 176         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 177
 178         switch ((lvt >> 8) & 7) {
 179         case APIC_DM_FIXED:
 180             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 181                 break;
 182             reset_bit(s->irr, lvt & 0xff);
 183             /* fall through */
 184         case APIC_DM_EXTINT:
 185             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 186             break;
 187         }
 188     }
 189 }
 190
 191 #define foreach_apic(apic, deliver_bitmask, code) \
 192 {\
 193     int __i, __j, __mask;\
 194     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 195         __mask = deliver_bitmask[__i];\
 196         if (__mask) {\
 197             for(__j = 0; __j < 32; __j++) {\
 198                 if (__mask & (1 << __j)) {\
 199                     apic = local_apics[__i * 32 + __j];\
 200                     if (apic) {\
 201                         code;\
 202                     }\
 203                 }\
 204             }\
 205         }\
 206     }\
 207 }
 208
 209 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 210                              uint8_t delivery_mode,
 211                              uint8_t vector_num, uint8_t polarity,
 212                              uint8_t trigger_mode)
 213 {
 214     APICState *apic_iter;
 215
 216     switch (delivery_mode) {
 217         case APIC_DM_LOWPRI:
 218             /* XXX: search for focus processor, arbitration */
 219             {
 220                 int i, d;
 221                 d = -1;
 222                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 223                     if (deliver_bitmask[i]) {
 224                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 225                         break;
 226                     }
 227                 }
 228                 if (d >= 0) {
 229                     apic_iter = local_apics[d];
 230                     if (apic_iter) {
 231                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 232                     }
 233                 }
 234             }
 235             return;
 236
 237         case APIC_DM_FIXED:
 238             break;
 239
 240         case APIC_DM_SMI:
 241             foreach_apic(apic_iter, deliver_bitmask,
 242                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 243             return;
 244
 245         case APIC_DM_NMI:
 246             foreach_apic(apic_iter, deliver_bitmask,
 247                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 248             return;
 249
 250         case APIC_DM_INIT:
 251             /* normal INIT IPI sent to processors */
 252             foreach_apic(apic_iter, deliver_bitmask,
 253                          apic_init_ipi(apic_iter) );
 254             return;
 255
 256         case APIC_DM_EXTINT:
 257             /* handled in I/O APIC code */
 258             break;
 259
 260         default:
 261             return;
 262     }
 263
 264     foreach_apic(apic_iter, deliver_bitmask,
 265                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 266 }
 267
 268 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 269                       uint8_t delivery_mode, uint8_t vector_num,
 270                       uint8_t polarity, uint8_t trigger_mode)
 271 {
 272     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 273
 274     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 275     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 276                      trigger_mode);
 277 }
 278
 279 void cpu_set_apic_base(CPUState *env, uint64_t val)
 280 {
 281     APICState *s = env->apic_state;
 282 #ifdef DEBUG_APIC
 283     printf("cpu_set_apic_base: %016" PRIx64 "\n", val);
 284 #endif
 285     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel())
 286         s->apicbase = val;
 287     else
 288         s->apicbase = (val & 0xfffff000) |
 289             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 290     /* if disabled, cannot be enabled again */
 291     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 292         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 293         env->cpuid_features &= ~CPUID_APIC;
 294         s->spurious_vec &= ~APIC_SV_ENABLE;
 295     }
 296 }
 297
 298 uint64_t cpu_get_apic_base(CPUState *env)
 299 {
 300     APICState *s = env->apic_state;
 301 #ifdef DEBUG_APIC
 302     printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase);
 303 #endif
 304     return s->apicbase;
 305 }
 306
 307 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
 308 {
 309     APICState *s = env->apic_state;
 310     s->tpr = (val & 0x0f) << 4;
 311     apic_update_irq(s);
 312 }
 313
 314 uint8_t cpu_get_apic_tpr(CPUX86State *env)
 315 {
 316     APICState *s = env->apic_state;
 317     return s->tpr >> 4;
 318 }
 319
 320 /* return -1 if no bit is set */
 321 static int get_highest_priority_int(uint32_t *tab)
 322 {
 323     int i;
 324     for(i = 7; i >= 0; i--) {
 325         if (tab[i] != 0) {
 326             return i * 32 + fls_bit(tab[i]);
 327         }
 328     }
 329     return -1;
 330 }
 331
 332 static int apic_get_ppr(APICState *s)
 333 {
 334     int tpr, isrv, ppr;
 335
 336     tpr = (s->tpr >> 4);
 337     isrv = get_highest_priority_int(s->isr);
 338     if (isrv < 0)
 339         isrv = 0;
 340     isrv >>= 4;
 341     if (tpr >= isrv)
 342         ppr = s->tpr;
 343     else
 344         ppr = isrv << 4;
 345     return ppr;
 346 }
 347
 348 static int apic_get_arb_pri(APICState *s)
 349 {
 350     /* XXX: arbitration */
 351     return 0;
 352 }
 353
 354 /* signal the CPU if an irq is pending */
 355 static void apic_update_irq(APICState *s)
 356 {
 357     int irrv, ppr;
 358     if (!(s->spurious_vec & APIC_SV_ENABLE))
 359         return;
 360     irrv = get_highest_priority_int(s->irr);
 361     if (irrv < 0)
 362         return;
 363     ppr = apic_get_ppr(s);
 364     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
 365         return;
 366     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 367 }
 368
 369 void apic_reset_irq_delivered(void)
 370 {
 371     apic_irq_delivered = 0;
 372 }
 373
 374 int apic_get_irq_delivered(void)
 375 {
 376     return apic_irq_delivered;
 377 }
 378
 379 void apic_set_irq_delivered(void)
 380 {
 381     apic_irq_delivered = 1;
 382 }
 383
 384 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 385 {
 386     apic_irq_delivered += !get_bit(s->irr, vector_num);
 387
 388     set_bit(s->irr, vector_num);
 389     if (trigger_mode)
 390         set_bit(s->tmr, vector_num);
 391     else
 392         reset_bit(s->tmr, vector_num);
 393     apic_update_irq(s);
 394 }
 395
 396 static void apic_eoi(APICState *s)
 397 {
 398     int isrv;
 399     isrv = get_highest_priority_int(s->isr);
 400     if (isrv < 0)
 401         return;
 402     reset_bit(s->isr, isrv);
 403     /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
 404             set the remote IRR bit for level triggered interrupts. */
 405     apic_update_irq(s);
 406 }
 407
 408 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 409                                       uint8_t dest, uint8_t dest_mode)
 410 {
 411     APICState *apic_iter;
 412     int i;
 413
 414     if (dest_mode == 0) {
 415         if (dest == 0xff) {
 416             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 417         } else {
 418             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 419             set_bit(deliver_bitmask, dest);
 420         }
 421     } else {
 422         /* XXX: cluster mode */
 423         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 424         for(i = 0; i < MAX_APICS; i++) {
 425             apic_iter = local_apics[i];
 426             if (apic_iter) {
 427                 if (apic_iter->dest_mode == 0xf) {
 428                     if (dest & apic_iter->log_dest)
 429                         set_bit(deliver_bitmask, i);
 430                 } else if (apic_iter->dest_mode == 0x0) {
 431                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 432                         (dest & apic_iter->log_dest & 0x0f)) {
 433                         set_bit(deliver_bitmask, i);
 434                     }
 435                 }
 436             }
 437         }
 438     }
 439 }
 440
 441
 442 static void apic_init_ipi(APICState *s)
 443 {
 444     int i;
 445
 446     s->tpr = 0;
 447     s->spurious_vec = 0xff;
 448     s->log_dest = 0;
 449     s->dest_mode = 0xf;
 450     memset(s->isr, 0, sizeof(s->isr));
 451     memset(s->tmr, 0, sizeof(s->tmr));
 452     memset(s->irr, 0, sizeof(s->irr));
 453     for(i = 0; i < APIC_LVT_NB; i++)
 454         s->lvt[i] = 1 << 16; /* mask LVT */
 455     s->esr = 0;
 456     memset(s->icr, 0, sizeof(s->icr));
 457     s->divide_conf = 0;
 458     s->count_shift = 0;
 459     s->initial_count = 0;
 460     s->initial_count_load_time = 0;
 461     s->next_time = 0;
 462
 463     cpu_reset(s->cpu_env);
 464
 465     if (!(s->apicbase & MSR_IA32_APICBASE_BSP) &&
 466         (!kvm_enabled() || !qemu_kvm_irqchip_in_kernel()))
 467         s->cpu_env->halted = 1;
 468
 469     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 470         if (s->cpu_env)
 471             kvm_apic_init(s->cpu_env);
 472 }
 473
 474 /* send a SIPI message to the CPU to start it */
 475 static void apic_startup(APICState *s, int vector_num)
 476 {
 477     CPUState *env = s->cpu_env;
 478     if (!env->halted)
 479         return;
 480     env->eip = 0;
 481     cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
 482                            0xffff, 0);
 483     env->halted = 0;
 484     if (kvm_enabled() && !qemu_kvm_irqchip_in_kernel())
 485         kvm_update_after_sipi(env);
 486 }
 487
 488 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
 489                          uint8_t delivery_mode, uint8_t vector_num,
 490                          uint8_t polarity, uint8_t trigger_mode)
 491 {
 492     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 493     int dest_shorthand = (s->icr[0] >> 18) & 3;
 494     APICState *apic_iter;
 495
 496     switch (dest_shorthand) {
 497     case 0:
 498         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 499         break;
 500     case 1:
 501         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 502         set_bit(deliver_bitmask, s->id);
 503         break;
 504     case 2:
 505         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 506         break;
 507     case 3:
 508         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 509         reset_bit(deliver_bitmask, s->id);
 510         break;
 511     }
 512
 513     switch (delivery_mode) {
 514         case APIC_DM_INIT:
 515             {
 516                 int trig_mode = (s->icr[0] >> 15) & 1;
 517                 int level = (s->icr[0] >> 14) & 1;
 518                 if (level == 0 && trig_mode == 1) {
 519                     foreach_apic(apic_iter, deliver_bitmask,
 520                                  apic_iter->arb_id = apic_iter->id );
 521                     return;
 522                 }
 523             }
 524             break;
 525
 526         case APIC_DM_SIPI:
 527             foreach_apic(apic_iter, deliver_bitmask,
 528                          apic_startup(apic_iter, vector_num) );
 529             return;
 530     }
 531
 532     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 533                      trigger_mode);
 534 }
 535
 536 int apic_get_interrupt(CPUState *env)
 537 {
 538     APICState *s = env->apic_state;
 539     int intno;
 540
 541     /* if the APIC is installed or enabled, we let the 8259 handle the
 542        IRQs */
 543     if (!s)
 544         return -1;
 545     if (!(s->spurious_vec & APIC_SV_ENABLE))
 546         return -1;
 547
 548     /* XXX: spurious IRQ handling */
 549     intno = get_highest_priority_int(s->irr);
 550     if (intno < 0)
 551         return -1;
 552     if (s->tpr && intno <= s->tpr)
 553         return s->spurious_vec & 0xff;
 554     reset_bit(s->irr, intno);
 555     set_bit(s->isr, intno);
 556     apic_update_irq(s);
 557     return intno;
 558 }
 559
 560 int apic_accept_pic_intr(CPUState *env)
 561 {
 562     APICState *s = env->apic_state;
 563     uint32_t lvt0;
 564
 565     if (!s)
 566         return -1;
 567
 568     lvt0 = s->lvt[APIC_LVT_LINT0];
 569
 570     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 571         (lvt0 & APIC_LVT_MASKED) == 0)
 572         return 1;
 573
 574     return 0;
 575 }
 576
 577 static uint32_t apic_get_current_count(APICState *s)
 578 {
 579     int64_t d;
 580     uint32_t val;
 581     d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
 582         s->count_shift;
 583     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 584         /* periodic */
 585         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 586     } else {
 587         if (d >= s->initial_count)
 588             val = 0;
 589         else
 590             val = s->initial_count - d;
 591     }
 592     return val;
 593 }
 594
 595 static void apic_timer_update(APICState *s, int64_t current_time)
 596 {
 597     int64_t next_time, d;
 598
 599     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 600         d = (current_time - s->initial_count_load_time) >>
 601             s->count_shift;
 602         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 603             if (!s->initial_count)
 604                 goto no_timer;
 605             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 606         } else {
 607             if (d >= s->initial_count)
 608                 goto no_timer;
 609             d = (uint64_t)s->initial_count + 1;
 610         }
 611         next_time = s->initial_count_load_time + (d << s->count_shift);
 612         qemu_mod_timer(s->timer, next_time);
 613         s->next_time = next_time;
 614     } else {
 615     no_timer:
 616         qemu_del_timer(s->timer);
 617     }
 618 }
 619
 620 static void apic_timer(void *opaque)
 621 {
 622     APICState *s = opaque;
 623
 624     apic_local_deliver(s->cpu_env, APIC_LVT_TIMER);
 625     apic_timer_update(s, s->next_time);
 626 }
 627
 628 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 629 {
 630     return 0;
 631 }
 632
 633 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 634 {
 635     return 0;
 636 }
 637
 638 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 639 {
 640 }
 641
 642 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 643 {
 644 }
 645
 646 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 647 {
 648     CPUState *env;
 649     APICState *s;
 650     uint32_t val;
 651     int index;
 652
 653     env = cpu_single_env;
 654     if (!env)
 655         return 0;
 656     s = env->apic_state;
 657
 658     index = (addr >> 4) & 0xff;
 659     switch(index) {
 660     case 0x02: /* id */
 661         val = s->id << 24;
 662         break;
 663     case 0x03: /* version */
 664         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 665         break;
 666     case 0x08:
 667         val = s->tpr;
 668         break;
 669     case 0x09:
 670         val = apic_get_arb_pri(s);
 671         break;
 672     case 0x0a:
 673         /* ppr */
 674         val = apic_get_ppr(s);
 675         break;
 676     case 0x0b:
 677         val = 0;
 678         break;
 679     case 0x0d:
 680         val = s->log_dest << 24;
 681         break;
 682     case 0x0e:
 683         val = s->dest_mode << 28;
 684         break;
 685     case 0x0f:
 686         val = s->spurious_vec;
 687         break;
 688     case 0x10 ... 0x17:
 689         val = s->isr[index & 7];
 690         break;
 691     case 0x18 ... 0x1f:
 692         val = s->tmr[index & 7];
 693         break;
 694     case 0x20 ... 0x27:
 695         val = s->irr[index & 7];
 696         break;
 697     case 0x28:
 698         val = s->esr;
 699         break;
 700     case 0x30:
 701     case 0x31:
 702         val = s->icr[index & 1];
 703         break;
 704     case 0x32 ... 0x37:
 705         val = s->lvt[index - 0x32];
 706         break;
 707     case 0x38:
 708         val = s->initial_count;
 709         break;
 710     case 0x39:
 711         val = apic_get_current_count(s);
 712         break;
 713     case 0x3e:
 714         val = s->divide_conf;
 715         break;
 716     default:
 717         s->esr |= ESR_ILLEGAL_ADDRESS;
 718         val = 0;
 719         break;
 720     }
 721 #ifdef DEBUG_APIC
 722     printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
 723 #endif
 724     return val;
 725 }
 726
 727 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 728 {
 729     CPUState *env;
 730     APICState *s;
 731     int index;
 732
 733     env = cpu_single_env;
 734     if (!env)
 735         return;
 736     s = env->apic_state;
 737
 738 #ifdef DEBUG_APIC
 739     printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
 740 #endif
 741
 742     index = (addr >> 4) & 0xff;
 743     switch(index) {
 744     case 0x02:
 745         s->id = (val >> 24);
 746         break;
 747     case 0x03:
 748         break;
 749     case 0x08:
 750         s->tpr = val;
 751         apic_update_irq(s);
 752         break;
 753     case 0x09:
 754     case 0x0a:
 755         break;
 756     case 0x0b: /* EOI */
 757         apic_eoi(s);
 758         break;
 759     case 0x0d:
 760         s->log_dest = val >> 24;
 761         break;
 762     case 0x0e:
 763         s->dest_mode = val >> 28;
 764         break;
 765     case 0x0f:
 766         s->spurious_vec = val & 0x1ff;
 767         apic_update_irq(s);
 768         break;
 769     case 0x10 ... 0x17:
 770     case 0x18 ... 0x1f:
 771     case 0x20 ... 0x27:
 772     case 0x28:
 773         break;
 774     case 0x30:
 775         s->icr[0] = val;
 776         apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 777                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 778                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 779         break;
 780     case 0x31:
 781         s->icr[1] = val;
 782         break;
 783     case 0x32 ... 0x37:
 784         {
 785             int n = index - 0x32;
 786             s->lvt[n] = val;
 787             if (n == APIC_LVT_TIMER)
 788                 apic_timer_update(s, qemu_get_clock(vm_clock));
 789         }
 790         break;
 791     case 0x38:
 792         s->initial_count = val;
 793         s->initial_count_load_time = qemu_get_clock(vm_clock);
 794         apic_timer_update(s, s->initial_count_load_time);
 795         break;
 796     case 0x39:
 797         break;
 798     case 0x3e:
 799         {
 800             int v;
 801             s->divide_conf = val & 0xb;
 802             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 803             s->count_shift = (v + 1) & 7;
 804         }
 805         break;
 806     default:
 807         s->esr |= ESR_ILLEGAL_ADDRESS;
 808         break;
 809     }
 810 }
 811
 812 #ifdef KVM_CAP_IRQCHIP
 813
 814 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 815 {
 816     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 817 }
 818
 819 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 820                                  int reg_id, uint32_t val)
 821 {
 822     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 823 }
 824
 825 static void kvm_kernel_lapic_save_to_user(APICState *s)
 826 {
 827     struct kvm_lapic_state apic;
 828     struct kvm_lapic_state *kapic = &apic;
 829     int i, v;
 830
 831     kvm_get_lapic(kvm_context, s->cpu_env->cpu_index, kapic);
 832
 833     s->id = kapic_reg(kapic, 0x2);
 834     s->tpr = kapic_reg(kapic, 0x8);
 835     s->arb_id = kapic_reg(kapic, 0x9);
 836     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 837     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 838     s->spurious_vec = kapic_reg(kapic, 0xf);
 839     for (i = 0; i < 8; i++) {
 840         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 841         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 842         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 843     }
 844     s->esr = kapic_reg(kapic, 0x28);
 845     s->icr[0] = kapic_reg(kapic, 0x30);
 846     s->icr[1] = kapic_reg(kapic, 0x31);
 847     for (i = 0; i < APIC_LVT_NB; i++)
 848         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 849     s->initial_count = kapic_reg(kapic, 0x38);
 850     s->divide_conf = kapic_reg(kapic, 0x3e);
 851
 852     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 853     s->count_shift = (v + 1) & 7;
 854
 855     s->initial_count_load_time = qemu_get_clock(vm_clock);
 856     apic_timer_update(s, s->initial_count_load_time);
 857 }
 858
 859 static void kvm_kernel_lapic_load_from_user(APICState *s)
 860 {
 861     struct kvm_lapic_state apic;
 862     struct kvm_lapic_state *klapic = &apic;
 863     int i;
 864
 865     memset(klapic, 0, sizeof apic);
 866     kapic_set_reg(klapic, 0x2, s->id);
 867     kapic_set_reg(klapic, 0x8, s->tpr);
 868     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 869     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 870     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 871     for (i = 0; i < 8; i++) {
 872         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 873         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 874         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 875     }
 876     kapic_set_reg(klapic, 0x28, s->esr);
 877     kapic_set_reg(klapic, 0x30, s->icr[0]);
 878     kapic_set_reg(klapic, 0x31, s->icr[1]);
 879     for (i = 0; i < APIC_LVT_NB; i++)
 880         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 881     kapic_set_reg(klapic, 0x38, s->initial_count);
 882     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 883
 884     kvm_set_lapic(kvm_context, s->cpu_env->cpu_index, klapic);
 885 }
 886
 887 #endif
 888
 889 static void apic_save(QEMUFile *f, void *opaque)
 890 {
 891     APICState *s = opaque;
 892     int i;
 893
 894 #ifdef KVM_CAP_IRQCHIP
 895     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 896         kvm_kernel_lapic_save_to_user(s);
 897     }
 898 #endif
 899
 900     qemu_put_be32s(f, &s->apicbase);
 901     qemu_put_8s(f, &s->id);
 902     qemu_put_8s(f, &s->arb_id);
 903     qemu_put_8s(f, &s->tpr);
 904     qemu_put_be32s(f, &s->spurious_vec);
 905     qemu_put_8s(f, &s->log_dest);
 906     qemu_put_8s(f, &s->dest_mode);
 907     for (i = 0; i < 8; i++) {
 908         qemu_put_be32s(f, &s->isr[i]);
 909         qemu_put_be32s(f, &s->tmr[i]);
 910         qemu_put_be32s(f, &s->irr[i]);
 911     }
 912     for (i = 0; i < APIC_LVT_NB; i++) {
 913         qemu_put_be32s(f, &s->lvt[i]);
 914     }
 915     qemu_put_be32s(f, &s->esr);
 916     qemu_put_be32s(f, &s->icr[0]);
 917     qemu_put_be32s(f, &s->icr[1]);
 918     qemu_put_be32s(f, &s->divide_conf);
 919     qemu_put_be32(f, s->count_shift);
 920     qemu_put_be32s(f, &s->initial_count);
 921     qemu_put_be64(f, s->initial_count_load_time);
 922     qemu_put_be64(f, s->next_time);
 923
 924     qemu_put_timer(f, s->timer);
 925 }
 926
 927 static int apic_load(QEMUFile *f, void *opaque, int version_id)
 928 {
 929     APICState *s = opaque;
 930     int i;
 931
 932     if (version_id > 2)
 933         return -EINVAL;
 934
 935     /* XXX: what if the base changes? (registered memory regions) */
 936     qemu_get_be32s(f, &s->apicbase);
 937     qemu_get_8s(f, &s->id);
 938     qemu_get_8s(f, &s->arb_id);
 939     qemu_get_8s(f, &s->tpr);
 940     qemu_get_be32s(f, &s->spurious_vec);
 941     qemu_get_8s(f, &s->log_dest);
 942     qemu_get_8s(f, &s->dest_mode);
 943     for (i = 0; i < 8; i++) {
 944         qemu_get_be32s(f, &s->isr[i]);
 945         qemu_get_be32s(f, &s->tmr[i]);
 946         qemu_get_be32s(f, &s->irr[i]);
 947     }
 948     for (i = 0; i < APIC_LVT_NB; i++) {
 949         qemu_get_be32s(f, &s->lvt[i]);
 950     }
 951     qemu_get_be32s(f, &s->esr);
 952     qemu_get_be32s(f, &s->icr[0]);
 953     qemu_get_be32s(f, &s->icr[1]);
 954     qemu_get_be32s(f, &s->divide_conf);
 955     s->count_shift=qemu_get_be32(f);
 956     qemu_get_be32s(f, &s->initial_count);
 957     s->initial_count_load_time=qemu_get_be64(f);
 958     s->next_time=qemu_get_be64(f);
 959
 960     if (version_id >= 2)
 961         qemu_get_timer(f, s->timer);
 962
 963 #ifdef KVM_CAP_IRQCHIP
 964     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 965         kvm_kernel_lapic_load_from_user(s);
 966     }
 967 #endif
 968
 969     return 0;
 970 }
 971
 972 static void apic_reset(void *opaque)
 973 {
 974     APICState *s = opaque;
 975
 976     s->apicbase = 0xfee00000 |
 977         (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
 978
 979     apic_init_ipi(s);
 980
 981     if (s->id == 0) {
 982         /*
 983          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 984          * time typically by BIOS, so PIC interrupt can be delivered to the
 985          * processor when local APIC is enabled.
 986          */
 987         s->lvt[APIC_LVT_LINT0] = 0x700;
 988     }
 989 #ifdef KVM_CAP_IRQCHIP
 990     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 991         kvm_kernel_lapic_load_from_user(s);
 992     }
 993 #endif
 994 }
 995
 996 static CPUReadMemoryFunc *apic_mem_read[3] = {
 997     apic_mem_readb,
 998     apic_mem_readw,
 999     apic_mem_readl,
1000 };
1001
1002 static CPUWriteMemoryFunc *apic_mem_write[3] = {
1003     apic_mem_writeb,
1004     apic_mem_writew,
1005     apic_mem_writel,
1006 };
1007
1008 int apic_init(CPUState *env)
1009 {
1010     APICState *s;
1011
1012     if (last_apic_id >= MAX_APICS)
1013         return -1;
1014     s = qemu_mallocz(sizeof(APICState));
1015     env->apic_state = s;
1016     s->id = last_apic_id++;
1017     env->cpuid_apic_id = s->id;
1018     s->cpu_env = env;
1019
1020     apic_reset(s);
1021
1022     /* XXX: mapping more APICs at the same memory location */
1023     if (apic_io_memory == 0) {
1024         /* NOTE: the APIC is directly connected to the CPU - it is not
1025            on the global memory bus. */
1026         apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
1027                                                 apic_mem_write, NULL);
1028         cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
1029                                      apic_io_memory);
1030     }
1031     s->timer = qemu_new_timer(vm_clock, apic_timer, s);
1032
1033     register_savevm("apic", s->id, 2, apic_save, apic_load, s);
1034     qemu_register_reset(apic_reset, s);
1035
1036     local_apics[s->id] = s;
1037     return 0;
1038 }
1039