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kvm: qemu: propagate errors on failed migration.
[kvm-userspace.git] / qemu / hw / lsi53c895a.c
blob1f4f8b7ef7ea865bb0213102d3cb82cbdb06a2a6
1 /*
2 * QEMU LSI53C895A SCSI Host Bus Adapter emulation
3 *
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licenced under the LGPL.
8 */
9
10 /* ??? Need to check if the {read,write}[wl] routines work properly on
11 big-endian targets. */
12
13 #include "hw.h"
14 #include "pci.h"
15 #include "scsi-disk.h"
16 #include "block_int.h"
17
18 //#define DEBUG_LSI
19 //#define DEBUG_LSI_REG
20
21 #ifdef DEBUG_LSI
22 #define DPRINTF(fmt, args...) \
23 do { printf("lsi_scsi: " fmt , ##args); } while (0)
24 #define BADF(fmt, args...) \
25 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args); exit(1);} while (0)
26 #else
27 #define DPRINTF(fmt, args...) do {} while(0)
28 #define BADF(fmt, args...) \
29 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args);} while (0)
30 #endif
31
32 #define LSI_SCNTL0_TRG 0x01
33 #define LSI_SCNTL0_AAP 0x02
34 #define LSI_SCNTL0_EPC 0x08
35 #define LSI_SCNTL0_WATN 0x10
36 #define LSI_SCNTL0_START 0x20
37
38 #define LSI_SCNTL1_SST 0x01
39 #define LSI_SCNTL1_IARB 0x02
40 #define LSI_SCNTL1_AESP 0x04
41 #define LSI_SCNTL1_RST 0x08
42 #define LSI_SCNTL1_CON 0x10
43 #define LSI_SCNTL1_DHP 0x20
44 #define LSI_SCNTL1_ADB 0x40
45 #define LSI_SCNTL1_EXC 0x80
46
47 #define LSI_SCNTL2_WSR 0x01
48 #define LSI_SCNTL2_VUE0 0x02
49 #define LSI_SCNTL2_VUE1 0x04
50 #define LSI_SCNTL2_WSS 0x08
51 #define LSI_SCNTL2_SLPHBEN 0x10
52 #define LSI_SCNTL2_SLPMD 0x20
53 #define LSI_SCNTL2_CHM 0x40
54 #define LSI_SCNTL2_SDU 0x80
55
56 #define LSI_ISTAT0_DIP 0x01
57 #define LSI_ISTAT0_SIP 0x02
58 #define LSI_ISTAT0_INTF 0x04
59 #define LSI_ISTAT0_CON 0x08
60 #define LSI_ISTAT0_SEM 0x10
61 #define LSI_ISTAT0_SIGP 0x20
62 #define LSI_ISTAT0_SRST 0x40
63 #define LSI_ISTAT0_ABRT 0x80
64
65 #define LSI_ISTAT1_SI 0x01
66 #define LSI_ISTAT1_SRUN 0x02
67 #define LSI_ISTAT1_FLSH 0x04
68
69 #define LSI_SSTAT0_SDP0 0x01
70 #define LSI_SSTAT0_RST 0x02
71 #define LSI_SSTAT0_WOA 0x04
72 #define LSI_SSTAT0_LOA 0x08
73 #define LSI_SSTAT0_AIP 0x10
74 #define LSI_SSTAT0_OLF 0x20
75 #define LSI_SSTAT0_ORF 0x40
76 #define LSI_SSTAT0_ILF 0x80
77
78 #define LSI_SIST0_PAR 0x01
79 #define LSI_SIST0_RST 0x02
80 #define LSI_SIST0_UDC 0x04
81 #define LSI_SIST0_SGE 0x08
82 #define LSI_SIST0_RSL 0x10
83 #define LSI_SIST0_SEL 0x20
84 #define LSI_SIST0_CMP 0x40
85 #define LSI_SIST0_MA 0x80
86
87 #define LSI_SIST1_HTH 0x01
88 #define LSI_SIST1_GEN 0x02
89 #define LSI_SIST1_STO 0x04
90 #define LSI_SIST1_SBMC 0x10
91
92 #define LSI_SOCL_IO 0x01
93 #define LSI_SOCL_CD 0x02
94 #define LSI_SOCL_MSG 0x04
95 #define LSI_SOCL_ATN 0x08
96 #define LSI_SOCL_SEL 0x10
97 #define LSI_SOCL_BSY 0x20
98 #define LSI_SOCL_ACK 0x40
99 #define LSI_SOCL_REQ 0x80
100
101 #define LSI_DSTAT_IID 0x01
102 #define LSI_DSTAT_SIR 0x04
103 #define LSI_DSTAT_SSI 0x08
104 #define LSI_DSTAT_ABRT 0x10
105 #define LSI_DSTAT_BF 0x20
106 #define LSI_DSTAT_MDPE 0x40
107 #define LSI_DSTAT_DFE 0x80
108
109 #define LSI_DCNTL_COM 0x01
110 #define LSI_DCNTL_IRQD 0x02
111 #define LSI_DCNTL_STD 0x04
112 #define LSI_DCNTL_IRQM 0x08
113 #define LSI_DCNTL_SSM 0x10
114 #define LSI_DCNTL_PFEN 0x20
115 #define LSI_DCNTL_PFF 0x40
116 #define LSI_DCNTL_CLSE 0x80
117
118 #define LSI_DMODE_MAN 0x01
119 #define LSI_DMODE_BOF 0x02
120 #define LSI_DMODE_ERMP 0x04
121 #define LSI_DMODE_ERL 0x08
122 #define LSI_DMODE_DIOM 0x10
123 #define LSI_DMODE_SIOM 0x20
124
125 #define LSI_CTEST2_DACK 0x01
126 #define LSI_CTEST2_DREQ 0x02
127 #define LSI_CTEST2_TEOP 0x04
128 #define LSI_CTEST2_PCICIE 0x08
129 #define LSI_CTEST2_CM 0x10
130 #define LSI_CTEST2_CIO 0x20
131 #define LSI_CTEST2_SIGP 0x40
132 #define LSI_CTEST2_DDIR 0x80
133
134 #define LSI_CTEST5_BL2 0x04
135 #define LSI_CTEST5_DDIR 0x08
136 #define LSI_CTEST5_MASR 0x10
137 #define LSI_CTEST5_DFSN 0x20
138 #define LSI_CTEST5_BBCK 0x40
139 #define LSI_CTEST5_ADCK 0x80
140
141 #define LSI_CCNTL0_DILS 0x01
142 #define LSI_CCNTL0_DISFC 0x10
143 #define LSI_CCNTL0_ENNDJ 0x20
144 #define LSI_CCNTL0_PMJCTL 0x40
145 #define LSI_CCNTL0_ENPMJ 0x80
146
147 #define LSI_CCNTL1_EN64DBMV 0x01
148 #define LSI_CCNTL1_EN64TIBMV 0x02
149 #define LSI_CCNTL1_64TIMOD 0x04
150 #define LSI_CCNTL1_DDAC 0x08
151 #define LSI_CCNTL1_ZMOD 0x80
152
153 #define LSI_CCNTL1_40BIT (LSI_CCNTL1_EN64TIBMV|LSI_CCNTL1_64TIMOD)
154
155 #define PHASE_DO 0
156 #define PHASE_DI 1
157 #define PHASE_CMD 2
158 #define PHASE_ST 3
159 #define PHASE_MO 6
160 #define PHASE_MI 7
161 #define PHASE_MASK 7
162
163 /* Maximum length of MSG IN data. */
164 #define LSI_MAX_MSGIN_LEN 8
165
166 /* Flag set if this is a tagged command. */
167 #define LSI_TAG_VALID (1 << 16)
168
169 typedef struct {
170 uint32_t tag;
171 uint32_t pending;
172 int out;
173 } lsi_queue;
174
175 typedef struct {
176 PCIDevice pci_dev;
177 int mmio_io_addr;
178 int ram_io_addr;
179 uint32_t script_ram_base;
180
181 int carry; /* ??? Should this be an a visible register somewhere? */
182 int sense;
183 /* Action to take at the end of a MSG IN phase.
184 0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN. */
185 int msg_action;
186 int msg_len;
187 uint8_t msg[LSI_MAX_MSGIN_LEN];
188 /* 0 if SCRIPTS are running or stopped.
189 * 1 if a Wait Reselect instruction has been issued.
190 * 2 if processing DMA from lsi_execute_script.
191 * 3 if a DMA operation is in progress. */
192 int waiting;
193 SCSIDevice *scsi_dev[LSI_MAX_DEVS];
194 SCSIDevice *current_dev;
195 int current_lun;
196 /* The tag is a combination of the device ID and the SCSI tag. */
197 uint32_t current_tag;
198 uint32_t current_dma_len;
199 int command_complete;
200 uint8_t *dma_buf;
201 lsi_queue *queue;
202 int queue_len;
203 int active_commands;
204
205 uint32_t dsa;
206 uint32_t temp;
207 uint32_t dnad;
208 uint32_t dbc;
209 uint8_t istat0;
210 uint8_t istat1;
211 uint8_t dcmd;
212 uint8_t dstat;
213 uint8_t dien;
214 uint8_t sist0;
215 uint8_t sist1;
216 uint8_t sien0;
217 uint8_t sien1;
218 uint8_t mbox0;
219 uint8_t mbox1;
220 uint8_t dfifo;
221 uint8_t ctest2;
222 uint8_t ctest3;
223 uint8_t ctest4;
224 uint8_t ctest5;
225 uint8_t ccntl0;
226 uint8_t ccntl1;
227 uint32_t dsp;
228 uint32_t dsps;
229 uint8_t dmode;
230 uint8_t dcntl;
231 uint8_t scntl0;
232 uint8_t scntl1;
233 uint8_t scntl2;
234 uint8_t scntl3;
235 uint8_t sstat0;
236 uint8_t sstat1;
237 uint8_t scid;
238 uint8_t sxfer;
239 uint8_t socl;
240 uint8_t sdid;
241 uint8_t ssid;
242 uint8_t sfbr;
243 uint8_t stest1;
244 uint8_t stest2;
245 uint8_t stest3;
246 uint8_t sidl;
247 uint8_t stime0;
248 uint8_t respid0;
249 uint8_t respid1;
250 uint32_t mmrs;
251 uint32_t mmws;
252 uint32_t sfs;
253 uint32_t drs;
254 uint32_t sbms;
255 uint32_t dbms;
256 uint32_t dnad64;
257 uint32_t pmjad1;
258 uint32_t pmjad2;
259 uint32_t rbc;
260 uint32_t ua;
261 uint32_t ia;
262 uint32_t sbc;
263 uint32_t csbc;
264 uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
265
266 /* Script ram is stored as 32-bit words in host byteorder. */
267 uint32_t script_ram[2048];
268 } LSIState;
269
270 static void lsi_soft_reset(LSIState *s)
271 {
272 DPRINTF("Reset\n");
273 s->carry = 0;
274
275 s->waiting = 0;
276 s->dsa = 0;
277 s->dnad = 0;
278 s->dbc = 0;
279 s->temp = 0;
280 memset(s->scratch, 0, sizeof(s->scratch));
281 s->istat0 = 0;
282 s->istat1 = 0;
283 s->dcmd = 0;
284 s->dstat = 0;
285 s->dien = 0;
286 s->sist0 = 0;
287 s->sist1 = 0;
288 s->sien0 = 0;
289 s->sien1 = 0;
290 s->mbox0 = 0;
291 s->mbox1 = 0;
292 s->dfifo = 0;
293 s->ctest2 = 0;
294 s->ctest3 = 0;
295 s->ctest4 = 0;
296 s->ctest5 = 0;
297 s->ccntl0 = 0;
298 s->ccntl1 = 0;
299 s->dsp = 0;
300 s->dsps = 0;
301 s->dmode = 0;
302 s->dcntl = 0;
303 s->scntl0 = 0xc0;
304 s->scntl1 = 0;
305 s->scntl2 = 0;
306 s->scntl3 = 0;
307 s->sstat0 = 0;
308 s->sstat1 = 0;
309 s->scid = 7;
310 s->sxfer = 0;
311 s->socl = 0;
312 s->stest1 = 0;
313 s->stest2 = 0;
314 s->stest3 = 0;
315 s->sidl = 0;
316 s->stime0 = 0;
317 s->respid0 = 0x80;
318 s->respid1 = 0;
319 s->mmrs = 0;
320 s->mmws = 0;
321 s->sfs = 0;
322 s->drs = 0;
323 s->sbms = 0;
324 s->dbms = 0;
325 s->dnad64 = 0;
326 s->pmjad1 = 0;
327 s->pmjad2 = 0;
328 s->rbc = 0;
329 s->ua = 0;
330 s->ia = 0;
331 s->sbc = 0;
332 s->csbc = 0;
333 }
334
335 static int lsi_dma_40bit(LSIState *s)
336 {
337 if ((s->ccntl1 & LSI_CCNTL1_40BIT) == LSI_CCNTL1_40BIT)
338 return 1;
339 return 0;
340 }
341
342 static int lsi_dma_ti64bit(LSIState *s)
343 {
344 if ((s->ccntl1 & LSI_CCNTL1_EN64TIBMV) == LSI_CCNTL1_EN64TIBMV)
345 return 1;
346 return 0;
347 }
348
349 static int lsi_dma_64bit(LSIState *s)
350 {
351 if ((s->ccntl1 & LSI_CCNTL1_EN64DBMV) == LSI_CCNTL1_EN64DBMV)
352 return 1;
353 return 0;
354 }
355
356 static uint8_t lsi_reg_readb(LSIState *s, int offset);
357 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
358 static void lsi_execute_script(LSIState *s);
359
360 static inline uint32_t read_dword(LSIState *s, uint32_t addr)
361 {
362 uint32_t buf;
363
364 /* Optimize reading from SCRIPTS RAM. */
365 if ((addr & 0xffffe000) == s->script_ram_base) {
366 return s->script_ram[(addr & 0x1fff) >> 2];
367 }
368 cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
369 return cpu_to_le32(buf);
370 }
371
372 static void lsi_stop_script(LSIState *s)
373 {
374 s->istat1 &= ~LSI_ISTAT1_SRUN;
375 }
376
377 static void lsi_update_irq(LSIState *s)
378 {
379 int level;
380 static int last_level;
381
382 /* It's unclear whether the DIP/SIP bits should be cleared when the
383 Interrupt Status Registers are cleared or when istat0 is read.
384 We currently do the formwer, which seems to work. */
385 level = 0;
386 if (s->dstat) {
387 if (s->dstat & s->dien)
388 level = 1;
389 s->istat0 |= LSI_ISTAT0_DIP;
390 } else {
391 s->istat0 &= ~LSI_ISTAT0_DIP;
392 }
393
394 if (s->sist0 || s->sist1) {
395 if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
396 level = 1;
397 s->istat0 |= LSI_ISTAT0_SIP;
398 } else {
399 s->istat0 &= ~LSI_ISTAT0_SIP;
400 }
401 if (s->istat0 & LSI_ISTAT0_INTF)
402 level = 1;
403
404 if (level != last_level) {
405 DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
406 level, s->dstat, s->sist1, s->sist0);
407 last_level = level;
408 }
409 qemu_set_irq(s->pci_dev.irq[0], level);
410 }
411
412 /* Stop SCRIPTS execution and raise a SCSI interrupt. */
413 static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
414 {
415 uint32_t mask0;
416 uint32_t mask1;
417
418 DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
419 stat1, stat0, s->sist1, s->sist0);
420 s->sist0 |= stat0;
421 s->sist1 |= stat1;
422 /* Stop processor on fatal or unmasked interrupt. As a special hack
423 we don't stop processing when raising STO. Instead continue
424 execution and stop at the next insn that accesses the SCSI bus. */
425 mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
426 mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
427 mask1 &= ~LSI_SIST1_STO;
428 if (s->sist0 & mask0 || s->sist1 & mask1) {
429 lsi_stop_script(s);
430 }
431 lsi_update_irq(s);
432 }
433
434 /* Stop SCRIPTS execution and raise a DMA interrupt. */
435 static void lsi_script_dma_interrupt(LSIState *s, int stat)
436 {
437 DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
438 s->dstat |= stat;
439 lsi_update_irq(s);
440 lsi_stop_script(s);
441 }
442
443 static inline void lsi_set_phase(LSIState *s, int phase)
444 {
445 s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
446 }
447
448 static void lsi_bad_phase(LSIState *s, int out, int new_phase)
449 {
450 /* Trigger a phase mismatch. */
451 if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
452 if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
453 s->dsp = s->pmjad1;
454 } else {
455 s->dsp = s->pmjad2;
456 }
457 DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
458 } else {
459 DPRINTF("Phase mismatch interrupt\n");
460 lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
461 lsi_stop_script(s);
462 }
463 lsi_set_phase(s, new_phase);
464 }
465
466
467 /* Resume SCRIPTS execution after a DMA operation. */
468 static void lsi_resume_script(LSIState *s)
469 {
470 if (s->waiting != 2) {
471 s->waiting = 0;
472 lsi_execute_script(s);
473 } else {
474 s->waiting = 0;
475 }
476 }
477
478 /* Initiate a SCSI layer data transfer. */
479 static void lsi_do_dma(LSIState *s, int out)
480 {
481 uint32_t count;
482 target_phys_addr_t addr;
483
484 if (!s->current_dma_len) {
485 /* Wait until data is available. */
486 DPRINTF("DMA no data available\n");
487 return;
488 }
489
490 count = s->dbc;
491 if (count > s->current_dma_len)
492 count = s->current_dma_len;
493
494 addr = s->dnad;
495 /* both 40 and Table Indirect 64-bit DMAs store upper bits in dnad64 */
496 if (lsi_dma_40bit(s) || lsi_dma_ti64bit(s))
497 addr |= ((uint64_t)s->dnad64 << 32);
498 else if (s->dbms)
499 addr |= ((uint64_t)s->dbms << 32);
500 else if (s->sbms)
501 addr |= ((uint64_t)s->sbms << 32);
502
503 DPRINTF("DMA addr=0x" TARGET_FMT_plx " len=%d\n", addr, count);
504 s->csbc += count;
505 s->dnad += count;
506 s->dbc -= count;
507
508 if (s->dma_buf == NULL) {
509 s->dma_buf = s->current_dev->get_buf(s->current_dev,
510 s->current_tag);
511 }
512
513 /* ??? Set SFBR to first data byte. */
514 if (out) {
515 cpu_physical_memory_read(addr, s->dma_buf, count);
516 } else {
517 cpu_physical_memory_write(addr, s->dma_buf, count);
518 }
519 s->current_dma_len -= count;
520 if (s->current_dma_len == 0) {
521 s->dma_buf = NULL;
522 if (out) {
523 /* Write the data. */
524 s->current_dev->write_data(s->current_dev, s->current_tag);
525 } else {
526 /* Request any remaining data. */
527 s->current_dev->read_data(s->current_dev, s->current_tag);
528 }
529 } else {
530 s->dma_buf += count;
531 lsi_resume_script(s);
532 }
533 }
534
535
536 /* Add a command to the queue. */
537 static void lsi_queue_command(LSIState *s)
538 {
539 lsi_queue *p;
540
541 DPRINTF("Queueing tag=0x%x\n", s->current_tag);
542 if (s->queue_len == s->active_commands) {
543 s->queue_len++;
544 s->queue = qemu_realloc(s->queue, s->queue_len * sizeof(lsi_queue));
545 }
546 p = &s->queue[s->active_commands++];
547 p->tag = s->current_tag;
548 p->pending = 0;
549 p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
550 }
551
552 /* Queue a byte for a MSG IN phase. */
553 static void lsi_add_msg_byte(LSIState *s, uint8_t data)
554 {
555 if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
556 BADF("MSG IN data too long\n");
557 } else {
558 DPRINTF("MSG IN 0x%02x\n", data);
559 s->msg[s->msg_len++] = data;
560 }
561 }
562
563 /* Perform reselection to continue a command. */
564 static void lsi_reselect(LSIState *s, uint32_t tag)
565 {
566 lsi_queue *p;
567 int n;
568 int id;
569
570 p = NULL;
571 for (n = 0; n < s->active_commands; n++) {
572 p = &s->queue[n];
573 if (p->tag == tag)
574 break;
575 }
576 if (n == s->active_commands) {
577 BADF("Reselected non-existant command tag=0x%x\n", tag);
578 return;
579 }
580 id = (tag >> 8) & 0xf;
581 s->ssid = id | 0x80;
582 DPRINTF("Reselected target %d\n", id);
583 s->current_dev = s->scsi_dev[id];
584 s->current_tag = tag;
585 s->scntl1 |= LSI_SCNTL1_CON;
586 lsi_set_phase(s, PHASE_MI);
587 s->msg_action = p->out ? 2 : 3;
588 s->current_dma_len = p->pending;
589 s->dma_buf = NULL;
590 lsi_add_msg_byte(s, 0x80);
591 if (s->current_tag & LSI_TAG_VALID) {
592 lsi_add_msg_byte(s, 0x20);
593 lsi_add_msg_byte(s, tag & 0xff);
594 }
595
596 s->active_commands--;
597 if (n != s->active_commands) {
598 s->queue[n] = s->queue[s->active_commands];
599 }
600 }
601
602 /* Record that data is available for a queued command. Returns zero if
603 the device was reselected, nonzero if the IO is deferred. */
604 static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg)
605 {
606 lsi_queue *p;
607 int i;
608 for (i = 0; i < s->active_commands; i++) {
609 p = &s->queue[i];
610 if (p->tag == tag) {
611 if (p->pending) {
612 BADF("Multiple IO pending for tag %d\n", tag);
613 }
614 p->pending = arg;
615 if (s->waiting == 1) {
616 /* Reselect device. */
617 lsi_reselect(s, tag);
618 return 0;
619 } else {
620 DPRINTF("Queueing IO tag=0x%x\n", tag);
621 p->pending = arg;
622 return 1;
623 }
624 }
625 }
626 BADF("IO with unknown tag %d\n", tag);
627 return 1;
628 }
629
630 /* Callback to indicate that the SCSI layer has completed a transfer. */
631 static void lsi_command_complete(void *opaque, int reason, uint32_t tag,
632 uint32_t arg)
633 {
634 LSIState *s = (LSIState *)opaque;
635 int out;
636
637 out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
638 if (reason == SCSI_REASON_DONE) {
639 DPRINTF("Command complete sense=%d\n", (int)arg);
640 s->sense = arg;
641 s->command_complete = 2;
642 if (s->waiting && s->dbc != 0) {
643 /* Raise phase mismatch for short transfers. */
644 lsi_bad_phase(s, out, PHASE_ST);
645 } else {
646 lsi_set_phase(s, PHASE_ST);
647 }
648 lsi_resume_script(s);
649 return;
650 }
651
652 if (s->waiting == 1 || tag != s->current_tag) {
653 if (lsi_queue_tag(s, tag, arg))
654 return;
655 }
656 DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
657 s->current_dma_len = arg;
658 s->command_complete = 1;
659 if (!s->waiting)
660 return;
661 if (s->waiting == 1 || s->dbc == 0) {
662 lsi_resume_script(s);
663 } else {
664 lsi_do_dma(s, out);
665 }
666 }
667
668 static void lsi_do_command(LSIState *s)
669 {
670 uint8_t buf[16];
671 int n;
672
673 DPRINTF("Send command len=%d\n", s->dbc);
674 if (s->dbc > 16)
675 s->dbc = 16;
676 cpu_physical_memory_read(s->dnad, buf, s->dbc);
677 s->sfbr = buf[0];
678 s->command_complete = 0;
679 n = s->current_dev->send_command(s->current_dev, s->current_tag, buf,
680 s->current_lun);
681 if (n > 0) {
682 lsi_set_phase(s, PHASE_DI);
683 s->current_dev->read_data(s->current_dev, s->current_tag);
684 } else if (n < 0) {
685 lsi_set_phase(s, PHASE_DO);
686 s->current_dev->write_data(s->current_dev, s->current_tag);
687 }
688
689 if (!s->command_complete) {
690 if (n) {
691 /* Command did not complete immediately so disconnect. */
692 lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
693 lsi_add_msg_byte(s, 4); /* DISCONNECT */
694 /* wait data */
695 lsi_set_phase(s, PHASE_MI);
696 s->msg_action = 1;
697 lsi_queue_command(s);
698 } else {
699 /* wait command complete */
700 lsi_set_phase(s, PHASE_DI);
701 }
702 }
703 }
704
705 static void lsi_do_status(LSIState *s)
706 {
707 uint8_t sense;
708 DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
709 if (s->dbc != 1)
710 BADF("Bad Status move\n");
711 s->dbc = 1;
712 sense = s->sense;
713 s->sfbr = sense;
714 cpu_physical_memory_write(s->dnad, &sense, 1);
715 lsi_set_phase(s, PHASE_MI);
716 s->msg_action = 1;
717 lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
718 }
719
720 static void lsi_disconnect(LSIState *s)
721 {
722 s->scntl1 &= ~LSI_SCNTL1_CON;
723 s->sstat1 &= ~PHASE_MASK;
724 }
725
726 static void lsi_do_msgin(LSIState *s)
727 {
728 int len;
729 DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
730 s->sfbr = s->msg[0];
731 len = s->msg_len;
732 if (len > s->dbc)
733 len = s->dbc;
734 cpu_physical_memory_write(s->dnad, s->msg, len);
735 /* Linux drivers rely on the last byte being in the SIDL. */
736 s->sidl = s->msg[len - 1];
737 s->msg_len -= len;
738 if (s->msg_len) {
739 memmove(s->msg, s->msg + len, s->msg_len);
740 } else {
741 /* ??? Check if ATN (not yet implemented) is asserted and maybe
742 switch to PHASE_MO. */
743 switch (s->msg_action) {
744 case 0:
745 lsi_set_phase(s, PHASE_CMD);
746 break;
747 case 1:
748 lsi_disconnect(s);
749 break;
750 case 2:
751 lsi_set_phase(s, PHASE_DO);
752 break;
753 case 3:
754 lsi_set_phase(s, PHASE_DI);
755 break;
756 default:
757 abort();
758 }
759 }
760 }
761
762 /* Read the next byte during a MSGOUT phase. */
763 static uint8_t lsi_get_msgbyte(LSIState *s)
764 {
765 uint8_t data;
766 cpu_physical_memory_read(s->dnad, &data, 1);
767 s->dnad++;
768 s->dbc--;
769 return data;
770 }
771
772 static void lsi_do_msgout(LSIState *s)
773 {
774 uint8_t msg;
775 int len;
776
777 DPRINTF("MSG out len=%d\n", s->dbc);
778 while (s->dbc) {
779 msg = lsi_get_msgbyte(s);
780 s->sfbr = msg;
781
782 switch (msg) {
783 case 0x00:
784 DPRINTF("MSG: Disconnect\n");
785 lsi_disconnect(s);
786 break;
787 case 0x08:
788 DPRINTF("MSG: No Operation\n");
789 lsi_set_phase(s, PHASE_CMD);
790 break;
791 case 0x01:
792 len = lsi_get_msgbyte(s);
793 msg = lsi_get_msgbyte(s);
794 DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
795 switch (msg) {
796 case 1:
797 DPRINTF("SDTR (ignored)\n");
798 s->dbc -= 2;
799 break;
800 case 3:
801 DPRINTF("WDTR (ignored)\n");
802 s->dbc -= 1;
803 break;
804 default:
805 goto bad;
806 }
807 break;
808 case 0x20: /* SIMPLE queue */
809 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
810 DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff);
811 break;
812 case 0x21: /* HEAD of queue */
813 BADF("HEAD queue not implemented\n");
814 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
815 break;
816 case 0x22: /* ORDERED queue */
817 BADF("ORDERED queue not implemented\n");
818 s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
819 break;
820 default:
821 if ((msg & 0x80) == 0) {
822 goto bad;
823 }
824 s->current_lun = msg & 7;
825 DPRINTF("Select LUN %d\n", s->current_lun);
826 lsi_set_phase(s, PHASE_CMD);
827 break;
828 }
829 }
830 return;
831 bad:
832 BADF("Unimplemented message 0x%02x\n", msg);
833 lsi_set_phase(s, PHASE_MI);
834 lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
835 s->msg_action = 0;
836 }
837
838 /* Sign extend a 24-bit value. */
839 static inline int32_t sxt24(int32_t n)
840 {
841 return (n << 8) >> 8;
842 }
843
844 static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
845 {
846 int n;
847 uint8_t buf[TARGET_PAGE_SIZE];
848
849 DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
850 while (count) {
851 n = (count > TARGET_PAGE_SIZE) ? TARGET_PAGE_SIZE : count;
852 cpu_physical_memory_read(src, buf, n);
853 cpu_physical_memory_write(dest, buf, n);
854 src += n;
855 dest += n;
856 count -= n;
857 }
858 }
859
860 static void lsi_wait_reselect(LSIState *s)
861 {
862 int i;
863 DPRINTF("Wait Reselect\n");
864 if (s->current_dma_len)
865 BADF("Reselect with pending DMA\n");
866 for (i = 0; i < s->active_commands; i++) {
867 if (s->queue[i].pending) {
868 lsi_reselect(s, s->queue[i].tag);
869 break;
870 }
871 }
872 if (s->current_dma_len == 0) {
873 s->waiting = 1;
874 }
875 }
876
877 static void lsi_execute_script(LSIState *s)
878 {
879 uint32_t insn;
880 uint32_t addr, addr_high;
881 int opcode;
882 int insn_processed = 0;
883
884 s->istat1 |= LSI_ISTAT1_SRUN;
885 again:
886 insn_processed++;
887 insn = read_dword(s, s->dsp);
888 if (!insn) {
889 /* If we receive an empty opcode increment the DSP by 4 bytes
890 instead of 8 and execute the next opcode at that location */
891 s->dsp += 4;
892 goto again;
893 }
894 addr = read_dword(s, s->dsp + 4);
895 addr_high = 0;
896 DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
897 s->dsps = addr;
898 s->dcmd = insn >> 24;
899 s->dsp += 8;
900 switch (insn >> 30) {
901 case 0: /* Block move. */
902 if (s->sist1 & LSI_SIST1_STO) {
903 DPRINTF("Delayed select timeout\n");
904 lsi_stop_script(s);
905 break;
906 }
907 s->dbc = insn & 0xffffff;
908 s->rbc = s->dbc;
909 /* ??? Set ESA. */
910 s->ia = s->dsp - 8;
911 if (insn & (1 << 29)) {
912 /* Indirect addressing. */
913 addr = read_dword(s, addr);
914 } else if (insn & (1 << 28)) {
915 uint32_t buf[2];
916 int32_t offset;
917 /* Table indirect addressing. */
918
919 /* 32-bit Table indirect */
920 offset = sxt24(addr);
921 cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
922 /* byte count is stored in bits 0:23 only */
923 s->dbc = cpu_to_le32(buf[0]) & 0xffffff;
924 s->rbc = s->dbc;
925 addr = cpu_to_le32(buf[1]);
926
927 /* 40-bit DMA, upper addr bits [39:32] stored in first DWORD of
928 * table, bits [31:24] */
929 if (lsi_dma_40bit(s))
930 addr_high = cpu_to_le32(buf[0]) >> 24;
931 else if (lsi_dma_ti64bit(s)) {
932 int selector = (cpu_to_le32(buf[0]) >> 24) & 0x1f;
933 switch (selector) {
934 case 0 ... 0x0f:
935 /* offset index into scratch registers since
936 * TI64 mode can use registers C to R */
937 addr_high = s->scratch[2 + selector];
938 break;
939 case 0x10:
940 addr_high = s->mmrs;
941 break;
942 case 0x11:
943 addr_high = s->mmws;
944 break;
945 case 0x12:
946 addr_high = s->sfs;
947 break;
948 case 0x13:
949 addr_high = s->drs;
950 break;
951 case 0x14:
952 addr_high = s->sbms;
953 break;
954 case 0x15:
955 addr_high = s->dbms;
956 break;
957 default:
958 BADF("Illegal selector specified (0x%x > 0x15)"
959 " for 64-bit DMA block move", selector);
960 break;
961 }
962 }
963 } else if (lsi_dma_64bit(s)) {
964 /* fetch a 3rd dword if 64-bit direct move is enabled and
965 only if we're not doing table indirect or indirect addressing */
966 s->dbms = read_dword(s, s->dsp);
967 s->dsp += 4;
968 s->ia = s->dsp - 12;
969 }
970 if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
971 DPRINTF("Wrong phase got %d expected %d\n",
972 s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
973 lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
974 break;
975 }
976 s->dnad = addr;
977 s->dnad64 = addr_high;
978 switch (s->sstat1 & 0x7) {
979 case PHASE_DO:
980 s->waiting = 2;
981 lsi_do_dma(s, 1);
982 if (s->waiting)
983 s->waiting = 3;
984 break;
985 case PHASE_DI:
986 s->waiting = 2;
987 lsi_do_dma(s, 0);
988 if (s->waiting)
989 s->waiting = 3;
990 break;
991 case PHASE_CMD:
992 lsi_do_command(s);
993 break;
994 case PHASE_ST:
995 lsi_do_status(s);
996 break;
997 case PHASE_MO:
998 lsi_do_msgout(s);
999 break;
1000 case PHASE_MI:
1001 lsi_do_msgin(s);
1002 break;
1003 default:
1004 BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
1005 exit(1);
1006 }
1007 s->dfifo = s->dbc & 0xff;
1008 s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
1009 s->sbc = s->dbc;
1010 s->rbc -= s->dbc;
1011 s->ua = addr + s->dbc;
1012 break;
1013
1014 case 1: /* IO or Read/Write instruction. */
1015 opcode = (insn >> 27) & 7;
1016 if (opcode < 5) {
1017 uint32_t id;
1018
1019 if (insn & (1 << 25)) {
1020 id = read_dword(s, s->dsa + sxt24(insn));
1021 } else {
1022 id = addr;
1023 }
1024 id = (id >> 16) & 0xf;
1025 if (insn & (1 << 26)) {
1026 addr = s->dsp + sxt24(addr);
1027 }
1028 s->dnad = addr;
1029 switch (opcode) {
1030 case 0: /* Select */
1031 s->sdid = id;
1032 if (s->current_dma_len && (s->ssid & 0xf) == id) {
1033 DPRINTF("Already reselected by target %d\n", id);
1034 break;
1035 }
1036 s->sstat0 |= LSI_SSTAT0_WOA;
1037 s->scntl1 &= ~LSI_SCNTL1_IARB;
1038 if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
1039 DPRINTF("Selected absent target %d\n", id);
1040 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
1041 lsi_disconnect(s);
1042 break;
1043 }
1044 DPRINTF("Selected target %d%s\n",
1045 id, insn & (1 << 3) ? " ATN" : "");
1046 /* ??? Linux drivers compain when this is set. Maybe
1047 it only applies in low-level mode (unimplemented).
1048 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
1049 s->current_dev = s->scsi_dev[id];
1050 s->current_tag = id << 8;
1051 s->scntl1 |= LSI_SCNTL1_CON;
1052 if (insn & (1 << 3)) {
1053 s->socl |= LSI_SOCL_ATN;
1054 }
1055 lsi_set_phase(s, PHASE_MO);
1056 break;
1057 case 1: /* Disconnect */
1058 DPRINTF("Wait Disconect\n");
1059 s->scntl1 &= ~LSI_SCNTL1_CON;
1060 break;
1061 case 2: /* Wait Reselect */
1062 lsi_wait_reselect(s);
1063 break;
1064 case 3: /* Set */
1065 DPRINTF("Set%s%s%s%s\n",
1066 insn & (1 << 3) ? " ATN" : "",
1067 insn & (1 << 6) ? " ACK" : "",
1068 insn & (1 << 9) ? " TM" : "",
1069 insn & (1 << 10) ? " CC" : "");
1070 if (insn & (1 << 3)) {
1071 s->socl |= LSI_SOCL_ATN;
1072 lsi_set_phase(s, PHASE_MO);
1073 }
1074 if (insn & (1 << 9)) {
1075 BADF("Target mode not implemented\n");
1076 exit(1);
1077 }
1078 if (insn & (1 << 10))
1079 s->carry = 1;
1080 break;
1081 case 4: /* Clear */
1082 DPRINTF("Clear%s%s%s%s\n",
1083 insn & (1 << 3) ? " ATN" : "",
1084 insn & (1 << 6) ? " ACK" : "",
1085 insn & (1 << 9) ? " TM" : "",
1086 insn & (1 << 10) ? " CC" : "");
1087 if (insn & (1 << 3)) {
1088 s->socl &= ~LSI_SOCL_ATN;
1089 }
1090 if (insn & (1 << 10))
1091 s->carry = 0;
1092 break;
1093 }
1094 } else {
1095 uint8_t op0;
1096 uint8_t op1;
1097 uint8_t data8;
1098 int reg;
1099 int operator;
1100 #ifdef DEBUG_LSI
1101 static const char *opcode_names[3] =
1102 {"Write", "Read", "Read-Modify-Write"};
1103 static const char *operator_names[8] =
1104 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1105 #endif
1106
1107 reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
1108 data8 = (insn >> 8) & 0xff;
1109 opcode = (insn >> 27) & 7;
1110 operator = (insn >> 24) & 7;
1111 DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1112 opcode_names[opcode - 5], reg,
1113 operator_names[operator], data8, s->sfbr,
1114 (insn & (1 << 23)) ? " SFBR" : "");
1115 op0 = op1 = 0;
1116 switch (opcode) {
1117 case 5: /* From SFBR */
1118 op0 = s->sfbr;
1119 op1 = data8;
1120 break;
1121 case 6: /* To SFBR */
1122 if (operator)
1123 op0 = lsi_reg_readb(s, reg);
1124 op1 = data8;
1125 break;
1126 case 7: /* Read-modify-write */
1127 if (operator)
1128 op0 = lsi_reg_readb(s, reg);
1129 if (insn & (1 << 23)) {
1130 op1 = s->sfbr;
1131 } else {
1132 op1 = data8;
1133 }
1134 break;
1135 }
1136
1137 switch (operator) {
1138 case 0: /* move */
1139 op0 = op1;
1140 break;
1141 case 1: /* Shift left */
1142 op1 = op0 >> 7;
1143 op0 = (op0 << 1) | s->carry;
1144 s->carry = op1;
1145 break;
1146 case 2: /* OR */
1147 op0 |= op1;
1148 break;
1149 case 3: /* XOR */
1150 op0 ^= op1;
1151 break;
1152 case 4: /* AND */
1153 op0 &= op1;
1154 break;
1155 case 5: /* SHR */
1156 op1 = op0 & 1;
1157 op0 = (op0 >> 1) | (s->carry << 7);
1158 s->carry = op1;
1159 break;
1160 case 6: /* ADD */
1161 op0 += op1;
1162 s->carry = op0 < op1;
1163 break;
1164 case 7: /* ADC */
1165 op0 += op1 + s->carry;
1166 if (s->carry)
1167 s->carry = op0 <= op1;
1168 else
1169 s->carry = op0 < op1;
1170 break;
1171 }
1172
1173 switch (opcode) {
1174 case 5: /* From SFBR */
1175 case 7: /* Read-modify-write */
1176 lsi_reg_writeb(s, reg, op0);
1177 break;
1178 case 6: /* To SFBR */
1179 s->sfbr = op0;
1180 break;
1181 }
1182 }
1183 break;
1184
1185 case 2: /* Transfer Control. */
1186 {
1187 int cond;
1188 int jmp;
1189
1190 if ((insn & 0x002e0000) == 0) {
1191 DPRINTF("NOP\n");
1192 break;
1193 }
1194 if (s->sist1 & LSI_SIST1_STO) {
1195 DPRINTF("Delayed select timeout\n");
1196 lsi_stop_script(s);
1197 break;
1198 }
1199 cond = jmp = (insn & (1 << 19)) != 0;
1200 if (cond == jmp && (insn & (1 << 21))) {
1201 DPRINTF("Compare carry %d\n", s->carry == jmp);
1202 cond = s->carry != 0;
1203 }
1204 if (cond == jmp && (insn & (1 << 17))) {
1205 DPRINTF("Compare phase %d %c= %d\n",
1206 (s->sstat1 & PHASE_MASK),
1207 jmp ? '=' : '!',
1208 ((insn >> 24) & 7));
1209 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
1210 }
1211 if (cond == jmp && (insn & (1 << 18))) {
1212 uint8_t mask;
1213
1214 mask = (~insn >> 8) & 0xff;
1215 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1216 s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1217 cond = (s->sfbr & mask) == (insn & mask);
1218 }
1219 if (cond == jmp) {
1220 if (insn & (1 << 23)) {
1221 /* Relative address. */
1222 addr = s->dsp + sxt24(addr);
1223 }
1224 switch ((insn >> 27) & 7) {
1225 case 0: /* Jump */
1226 DPRINTF("Jump to 0x%08x\n", addr);
1227 s->dsp = addr;
1228 break;
1229 case 1: /* Call */
1230 DPRINTF("Call 0x%08x\n", addr);
1231 s->temp = s->dsp;
1232 s->dsp = addr;
1233 break;
1234 case 2: /* Return */
1235 DPRINTF("Return to 0x%08x\n", s->temp);
1236 s->dsp = s->temp;
1237 break;
1238 case 3: /* Interrupt */
1239 DPRINTF("Interrupt 0x%08x\n", s->dsps);
1240 if ((insn & (1 << 20)) != 0) {
1241 s->istat0 |= LSI_ISTAT0_INTF;
1242 lsi_update_irq(s);
1243 } else {
1244 lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1245 }
1246 break;
1247 default:
1248 DPRINTF("Illegal transfer control\n");
1249 lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1250 break;
1251 }
1252 } else {
1253 DPRINTF("Control condition failed\n");
1254 }
1255 }
1256 break;
1257
1258 case 3:
1259 if ((insn & (1 << 29)) == 0) {
1260 /* Memory move. */
1261 uint32_t dest;
1262 /* ??? The docs imply the destination address is loaded into
1263 the TEMP register. However the Linux drivers rely on
1264 the value being presrved. */
1265 dest = read_dword(s, s->dsp);
1266 s->dsp += 4;
1267 lsi_memcpy(s, dest, addr, insn & 0xffffff);
1268 } else {
1269 uint8_t data[7];
1270 int reg;
1271 int n;
1272 int i;
1273
1274 if (insn & (1 << 28)) {
1275 addr = s->dsa + sxt24(addr);
1276 }
1277 n = (insn & 7);
1278 reg = (insn >> 16) & 0xff;
1279 if (insn & (1 << 24)) {
1280 cpu_physical_memory_read(addr, data, n);
1281 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1282 addr, *(int *)data);
1283 for (i = 0; i < n; i++) {
1284 lsi_reg_writeb(s, reg + i, data[i]);
1285 }
1286 } else {
1287 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1288 for (i = 0; i < n; i++) {
1289 data[i] = lsi_reg_readb(s, reg + i);
1290 }
1291 cpu_physical_memory_write(addr, data, n);
1292 }
1293 }
1294 }
1295 if (insn_processed > 10000 && !s->waiting) {
1296 /* Some windows drivers make the device spin waiting for a memory
1297 location to change. If we have been executed a lot of code then
1298 assume this is the case and force an unexpected device disconnect.
1299 This is apparently sufficient to beat the drivers into submission.
1300 */
1301 if (!(s->sien0 & LSI_SIST0_UDC))
1302 fprintf(stderr, "inf. loop with UDC masked\n");
1303 lsi_script_scsi_interrupt(s, LSI_SIST0_UDC, 0);
1304 lsi_disconnect(s);
1305 } else if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
1306 if (s->dcntl & LSI_DCNTL_SSM) {
1307 lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1308 } else {
1309 goto again;
1310 }
1311 }
1312 DPRINTF("SCRIPTS execution stopped\n");
1313 }
1314
1315 static uint8_t lsi_reg_readb(LSIState *s, int offset)
1316 {
1317 uint8_t tmp;
1318 #define CASE_GET_REG24(name, addr) \
1319 case addr: return s->name & 0xff; \
1320 case addr + 1: return (s->name >> 8) & 0xff; \
1321 case addr + 2: return (s->name >> 16) & 0xff;
1322
1323 #define CASE_GET_REG32(name, addr) \
1324 case addr: return s->name & 0xff; \
1325 case addr + 1: return (s->name >> 8) & 0xff; \
1326 case addr + 2: return (s->name >> 16) & 0xff; \
1327 case addr + 3: return (s->name >> 24) & 0xff;
1328
1329 #ifdef DEBUG_LSI_REG
1330 DPRINTF("Read reg %x\n", offset);
1331 #endif
1332 switch (offset) {
1333 case 0x00: /* SCNTL0 */
1334 return s->scntl0;
1335 case 0x01: /* SCNTL1 */
1336 return s->scntl1;
1337 case 0x02: /* SCNTL2 */
1338 return s->scntl2;
1339 case 0x03: /* SCNTL3 */
1340 return s->scntl3;
1341 case 0x04: /* SCID */
1342 return s->scid;
1343 case 0x05: /* SXFER */
1344 return s->sxfer;
1345 case 0x06: /* SDID */
1346 return s->sdid;
1347 case 0x07: /* GPREG0 */
1348 return 0x7f;
1349 case 0x08: /* Revision ID */
1350 return 0x00;
1351 case 0xa: /* SSID */
1352 return s->ssid;
1353 case 0xb: /* SBCL */
1354 /* ??? This is not correct. However it's (hopefully) only
1355 used for diagnostics, so should be ok. */
1356 return 0;
1357 case 0xc: /* DSTAT */
1358 tmp = s->dstat | 0x80;
1359 if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1360 s->dstat = 0;
1361 lsi_update_irq(s);
1362 return tmp;
1363 case 0x0d: /* SSTAT0 */
1364 return s->sstat0;
1365 case 0x0e: /* SSTAT1 */
1366 return s->sstat1;
1367 case 0x0f: /* SSTAT2 */
1368 return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1369 CASE_GET_REG32(dsa, 0x10)
1370 case 0x14: /* ISTAT0 */
1371 return s->istat0;
1372 case 0x15: /* ISTAT1 */
1373 return s->istat1;
1374 case 0x16: /* MBOX0 */
1375 return s->mbox0;
1376 case 0x17: /* MBOX1 */
1377 return s->mbox1;
1378 case 0x18: /* CTEST0 */
1379 return 0xff;
1380 case 0x19: /* CTEST1 */
1381 return 0;
1382 case 0x1a: /* CTEST2 */
1383 tmp = s->ctest2 | LSI_CTEST2_DACK | LSI_CTEST2_CM;
1384 if (s->istat0 & LSI_ISTAT0_SIGP) {
1385 s->istat0 &= ~LSI_ISTAT0_SIGP;
1386 tmp |= LSI_CTEST2_SIGP;
1387 }
1388 return tmp;
1389 case 0x1b: /* CTEST3 */
1390 return s->ctest3;
1391 CASE_GET_REG32(temp, 0x1c)
1392 case 0x20: /* DFIFO */
1393 return 0;
1394 case 0x21: /* CTEST4 */
1395 return s->ctest4;
1396 case 0x22: /* CTEST5 */
1397 return s->ctest5;
1398 case 0x23: /* CTEST6 */
1399 return 0;
1400 CASE_GET_REG24(dbc, 0x24)
1401 case 0x27: /* DCMD */
1402 return s->dcmd;
1403 CASE_GET_REG32(dsp, 0x2c)
1404 CASE_GET_REG32(dsps, 0x30)
1405 CASE_GET_REG32(scratch[0], 0x34)
1406 case 0x38: /* DMODE */
1407 return s->dmode;
1408 case 0x39: /* DIEN */
1409 return s->dien;
1410 case 0x3b: /* DCNTL */
1411 return s->dcntl;
1412 case 0x40: /* SIEN0 */
1413 return s->sien0;
1414 case 0x41: /* SIEN1 */
1415 return s->sien1;
1416 case 0x42: /* SIST0 */
1417 tmp = s->sist0;
1418 s->sist0 = 0;
1419 lsi_update_irq(s);
1420 return tmp;
1421 case 0x43: /* SIST1 */
1422 tmp = s->sist1;
1423 s->sist1 = 0;
1424 lsi_update_irq(s);
1425 return tmp;
1426 case 0x46: /* MACNTL */
1427 return 0x0f;
1428 case 0x47: /* GPCNTL0 */
1429 return 0x0f;
1430 case 0x48: /* STIME0 */
1431 return s->stime0;
1432 case 0x4a: /* RESPID0 */
1433 return s->respid0;
1434 case 0x4b: /* RESPID1 */
1435 return s->respid1;
1436 case 0x4d: /* STEST1 */
1437 return s->stest1;
1438 case 0x4e: /* STEST2 */
1439 return s->stest2;
1440 case 0x4f: /* STEST3 */
1441 return s->stest3;
1442 case 0x50: /* SIDL */
1443 /* This is needed by the linux drivers. We currently only update it
1444 during the MSG IN phase. */
1445 return s->sidl;
1446 case 0x52: /* STEST4 */
1447 return 0xe0;
1448 case 0x56: /* CCNTL0 */
1449 return s->ccntl0;
1450 case 0x57: /* CCNTL1 */
1451 return s->ccntl1;
1452 case 0x58: /* SBDL */
1453 /* Some drivers peek at the data bus during the MSG IN phase. */
1454 if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1455 return s->msg[0];
1456 return 0;
1457 case 0x59: /* SBDL high */
1458 return 0;
1459 CASE_GET_REG32(mmrs, 0xa0)
1460 CASE_GET_REG32(mmws, 0xa4)
1461 CASE_GET_REG32(sfs, 0xa8)
1462 CASE_GET_REG32(drs, 0xac)
1463 CASE_GET_REG32(sbms, 0xb0)
1464 CASE_GET_REG32(dbms, 0xb4)
1465 CASE_GET_REG32(dnad64, 0xb8)
1466 CASE_GET_REG32(pmjad1, 0xc0)
1467 CASE_GET_REG32(pmjad2, 0xc4)
1468 CASE_GET_REG32(rbc, 0xc8)
1469 CASE_GET_REG32(ua, 0xcc)
1470 CASE_GET_REG32(ia, 0xd4)
1471 CASE_GET_REG32(sbc, 0xd8)
1472 CASE_GET_REG32(csbc, 0xdc)
1473 }
1474 if (offset >= 0x5c && offset < 0xa0) {
1475 int n;
1476 int shift;
1477 n = (offset - 0x58) >> 2;
1478 shift = (offset & 3) * 8;
1479 return (s->scratch[n] >> shift) & 0xff;
1480 }
1481 BADF("readb 0x%x\n", offset);
1482 exit(1);
1483 #undef CASE_GET_REG24
1484 #undef CASE_GET_REG32
1485 }
1486
1487 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1488 {
1489 #define CASE_SET_REG32(name, addr) \
1490 case addr : s->name &= 0xffffff00; s->name |= val; break; \
1491 case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8; break; \
1492 case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1493 case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1494
1495 #ifdef DEBUG_LSI_REG
1496 DPRINTF("Write reg %x = %02x\n", offset, val);
1497 #endif
1498 switch (offset) {
1499 case 0x00: /* SCNTL0 */
1500 s->scntl0 = val;
1501 if (val & LSI_SCNTL0_START) {
1502 BADF("Start sequence not implemented\n");
1503 }
1504 break;
1505 case 0x01: /* SCNTL1 */
1506 s->scntl1 = val & ~LSI_SCNTL1_SST;
1507 if (val & LSI_SCNTL1_IARB) {
1508 BADF("Immediate Arbritration not implemented\n");
1509 }
1510 if (val & LSI_SCNTL1_RST) {
1511 s->sstat0 |= LSI_SSTAT0_RST;
1512 lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1513 } else {
1514 s->sstat0 &= ~LSI_SSTAT0_RST;
1515 }
1516 break;
1517 case 0x02: /* SCNTL2 */
1518 val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1519 s->scntl2 = val;
1520 break;
1521 case 0x03: /* SCNTL3 */
1522 s->scntl3 = val;
1523 break;
1524 case 0x04: /* SCID */
1525 s->scid = val;
1526 break;
1527 case 0x05: /* SXFER */
1528 s->sxfer = val;
1529 break;
1530 case 0x06: /* SDID */
1531 if ((val & 0xf) != (s->ssid & 0xf))
1532 BADF("Destination ID does not match SSID\n");
1533 s->sdid = val & 0xf;
1534 break;
1535 case 0x07: /* GPREG0 */
1536 break;
1537 case 0x08: /* SFBR */
1538 /* The CPU is not allowed to write to this register. However the
1539 SCRIPTS register move instructions are. */
1540 s->sfbr = val;
1541 break;
1542 case 0x0a: case 0x0b:
1543 /* Openserver writes to these readonly registers on startup */
1544 return;
1545 case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1546 /* Linux writes to these readonly registers on startup. */
1547 return;
1548 CASE_SET_REG32(dsa, 0x10)
1549 case 0x14: /* ISTAT0 */
1550 s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1551 if (val & LSI_ISTAT0_ABRT) {
1552 lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1553 }
1554 if (val & LSI_ISTAT0_INTF) {
1555 s->istat0 &= ~LSI_ISTAT0_INTF;
1556 lsi_update_irq(s);
1557 }
1558 if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1559 DPRINTF("Woken by SIGP\n");
1560 s->waiting = 0;
1561 s->dsp = s->dnad;
1562 lsi_execute_script(s);
1563 }
1564 if (val & LSI_ISTAT0_SRST) {
1565 lsi_soft_reset(s);
1566 }
1567 break;
1568 case 0x16: /* MBOX0 */
1569 s->mbox0 = val;
1570 break;
1571 case 0x17: /* MBOX1 */
1572 s->mbox1 = val;
1573 break;
1574 case 0x1a: /* CTEST2 */
1575 s->ctest2 = val & LSI_CTEST2_PCICIE;
1576 break;
1577 case 0x1b: /* CTEST3 */
1578 s->ctest3 = val & 0x0f;
1579 break;
1580 CASE_SET_REG32(temp, 0x1c)
1581 case 0x21: /* CTEST4 */
1582 if (val & 7) {
1583 BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1584 }
1585 s->ctest4 = val;
1586 break;
1587 case 0x22: /* CTEST5 */
1588 if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1589 BADF("CTEST5 DMA increment not implemented\n");
1590 }
1591 s->ctest5 = val;
1592 break;
1593 case 0x2c: /* DSP[0:7] */
1594 s->dsp &= 0xffffff00;
1595 s->dsp |= val;
1596 break;
1597 case 0x2d: /* DSP[8:15] */
1598 s->dsp &= 0xffff00ff;
1599 s->dsp |= val << 8;
1600 break;
1601 case 0x2e: /* DSP[16:23] */
1602 s->dsp &= 0xff00ffff;
1603 s->dsp |= val << 16;
1604 break;
1605 case 0x2f: /* DSP[24:31] */
1606 s->dsp &= 0x00ffffff;
1607 s->dsp |= val << 24;
1608 if ((s->dmode & LSI_DMODE_MAN) == 0
1609 && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1610 lsi_execute_script(s);
1611 break;
1612 CASE_SET_REG32(dsps, 0x30)
1613 CASE_SET_REG32(scratch[0], 0x34)
1614 case 0x38: /* DMODE */
1615 if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1616 BADF("IO mappings not implemented\n");
1617 }
1618 s->dmode = val;
1619 break;
1620 case 0x39: /* DIEN */
1621 s->dien = val;
1622 lsi_update_irq(s);
1623 break;
1624 case 0x3b: /* DCNTL */
1625 s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1626 if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1627 lsi_execute_script(s);
1628 break;
1629 case 0x40: /* SIEN0 */
1630 s->sien0 = val;
1631 lsi_update_irq(s);
1632 break;
1633 case 0x41: /* SIEN1 */
1634 s->sien1 = val;
1635 lsi_update_irq(s);
1636 break;
1637 case 0x47: /* GPCNTL0 */
1638 break;
1639 case 0x48: /* STIME0 */
1640 s->stime0 = val;
1641 break;
1642 case 0x49: /* STIME1 */
1643 if (val & 0xf) {
1644 DPRINTF("General purpose timer not implemented\n");
1645 /* ??? Raising the interrupt immediately seems to be sufficient
1646 to keep the FreeBSD driver happy. */
1647 lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1648 }
1649 break;
1650 case 0x4a: /* RESPID0 */
1651 s->respid0 = val;
1652 break;
1653 case 0x4b: /* RESPID1 */
1654 s->respid1 = val;
1655 break;
1656 case 0x4d: /* STEST1 */
1657 s->stest1 = val;
1658 break;
1659 case 0x4e: /* STEST2 */
1660 if (val & 1) {
1661 BADF("Low level mode not implemented\n");
1662 }
1663 s->stest2 = val;
1664 break;
1665 case 0x4f: /* STEST3 */
1666 if (val & 0x41) {
1667 BADF("SCSI FIFO test mode not implemented\n");
1668 }
1669 s->stest3 = val;
1670 break;
1671 case 0x56: /* CCNTL0 */
1672 s->ccntl0 = val;
1673 break;
1674 case 0x57: /* CCNTL1 */
1675 s->ccntl1 = val;
1676 break;
1677 CASE_SET_REG32(mmrs, 0xa0)
1678 CASE_SET_REG32(mmws, 0xa4)
1679 CASE_SET_REG32(sfs, 0xa8)
1680 CASE_SET_REG32(drs, 0xac)
1681 CASE_SET_REG32(sbms, 0xb0)
1682 CASE_SET_REG32(dbms, 0xb4)
1683 CASE_SET_REG32(dnad64, 0xb8)
1684 CASE_SET_REG32(pmjad1, 0xc0)
1685 CASE_SET_REG32(pmjad2, 0xc4)
1686 CASE_SET_REG32(rbc, 0xc8)
1687 CASE_SET_REG32(ua, 0xcc)
1688 CASE_SET_REG32(ia, 0xd4)
1689 CASE_SET_REG32(sbc, 0xd8)
1690 CASE_SET_REG32(csbc, 0xdc)
1691 default:
1692 if (offset >= 0x5c && offset < 0xa0) {
1693 int n;
1694 int shift;
1695 n = (offset - 0x58) >> 2;
1696 shift = (offset & 3) * 8;
1697 s->scratch[n] &= ~(0xff << shift);
1698 s->scratch[n] |= (val & 0xff) << shift;
1699 } else {
1700 BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1701 }
1702 }
1703 #undef CASE_SET_REG32
1704 }
1705
1706 static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1707 {
1708 LSIState *s = (LSIState *)opaque;
1709
1710 lsi_reg_writeb(s, addr & 0xff, val);
1711 }
1712
1713 static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1714 {
1715 LSIState *s = (LSIState *)opaque;
1716
1717 addr &= 0xff;
1718 lsi_reg_writeb(s, addr, val & 0xff);
1719 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1720 }
1721
1722 static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1723 {
1724 LSIState *s = (LSIState *)opaque;
1725
1726 addr &= 0xff;
1727 lsi_reg_writeb(s, addr, val & 0xff);
1728 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1729 lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1730 lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1731 }
1732
1733 static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1734 {
1735 LSIState *s = (LSIState *)opaque;
1736
1737 return lsi_reg_readb(s, addr & 0xff);
1738 }
1739
1740 static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1741 {
1742 LSIState *s = (LSIState *)opaque;
1743 uint32_t val;
1744
1745 addr &= 0xff;
1746 val = lsi_reg_readb(s, addr);
1747 val |= lsi_reg_readb(s, addr + 1) << 8;
1748 return val;
1749 }
1750
1751 static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1752 {
1753 LSIState *s = (LSIState *)opaque;
1754 uint32_t val;
1755 addr &= 0xff;
1756 val = lsi_reg_readb(s, addr);
1757 val |= lsi_reg_readb(s, addr + 1) << 8;
1758 val |= lsi_reg_readb(s, addr + 2) << 16;
1759 val |= lsi_reg_readb(s, addr + 3) << 24;
1760 return val;
1761 }
1762
1763 static CPUReadMemoryFunc *lsi_mmio_readfn[3] = {
1764 lsi_mmio_readb,
1765 lsi_mmio_readw,
1766 lsi_mmio_readl,
1767 };
1768
1769 static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = {
1770 lsi_mmio_writeb,
1771 lsi_mmio_writew,
1772 lsi_mmio_writel,
1773 };
1774
1775 static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1776 {
1777 LSIState *s = (LSIState *)opaque;
1778 uint32_t newval;
1779 int shift;
1780
1781 addr &= 0x1fff;
1782 newval = s->script_ram[addr >> 2];
1783 shift = (addr & 3) * 8;
1784 newval &= ~(0xff << shift);
1785 newval |= val << shift;
1786 s->script_ram[addr >> 2] = newval;
1787 }
1788
1789 static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1790 {
1791 LSIState *s = (LSIState *)opaque;
1792 uint32_t newval;
1793
1794 addr &= 0x1fff;
1795 newval = s->script_ram[addr >> 2];
1796 if (addr & 2) {
1797 newval = (newval & 0xffff) | (val << 16);
1798 } else {
1799 newval = (newval & 0xffff0000) | val;
1800 }
1801 s->script_ram[addr >> 2] = newval;
1802 }
1803
1804
1805 static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1806 {
1807 LSIState *s = (LSIState *)opaque;
1808
1809 addr &= 0x1fff;
1810 s->script_ram[addr >> 2] = val;
1811 }
1812
1813 static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1814 {
1815 LSIState *s = (LSIState *)opaque;
1816 uint32_t val;
1817
1818 addr &= 0x1fff;
1819 val = s->script_ram[addr >> 2];
1820 val >>= (addr & 3) * 8;
1821 return val & 0xff;
1822 }
1823
1824 static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1825 {
1826 LSIState *s = (LSIState *)opaque;
1827 uint32_t val;
1828
1829 addr &= 0x1fff;
1830 val = s->script_ram[addr >> 2];
1831 if (addr & 2)
1832 val >>= 16;
1833 return le16_to_cpu(val);
1834 }
1835
1836 static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1837 {
1838 LSIState *s = (LSIState *)opaque;
1839
1840 addr &= 0x1fff;
1841 return le32_to_cpu(s->script_ram[addr >> 2]);
1842 }
1843
1844 static CPUReadMemoryFunc *lsi_ram_readfn[3] = {
1845 lsi_ram_readb,
1846 lsi_ram_readw,
1847 lsi_ram_readl,
1848 };
1849
1850 static CPUWriteMemoryFunc *lsi_ram_writefn[3] = {
1851 lsi_ram_writeb,
1852 lsi_ram_writew,
1853 lsi_ram_writel,
1854 };
1855
1856 static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1857 {
1858 LSIState *s = (LSIState *)opaque;
1859 return lsi_reg_readb(s, addr & 0xff);
1860 }
1861
1862 static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1863 {
1864 LSIState *s = (LSIState *)opaque;
1865 uint32_t val;
1866 addr &= 0xff;
1867 val = lsi_reg_readb(s, addr);
1868 val |= lsi_reg_readb(s, addr + 1) << 8;
1869 return val;
1870 }
1871
1872 static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1873 {
1874 LSIState *s = (LSIState *)opaque;
1875 uint32_t val;
1876 addr &= 0xff;
1877 val = lsi_reg_readb(s, addr);
1878 val |= lsi_reg_readb(s, addr + 1) << 8;
1879 val |= lsi_reg_readb(s, addr + 2) << 16;
1880 val |= lsi_reg_readb(s, addr + 3) << 24;
1881 return val;
1882 }
1883
1884 static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1885 {
1886 LSIState *s = (LSIState *)opaque;
1887 lsi_reg_writeb(s, addr & 0xff, val);
1888 }
1889
1890 static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1891 {
1892 LSIState *s = (LSIState *)opaque;
1893 addr &= 0xff;
1894 lsi_reg_writeb(s, addr, val & 0xff);
1895 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1896 }
1897
1898 static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1899 {
1900 LSIState *s = (LSIState *)opaque;
1901 addr &= 0xff;
1902 lsi_reg_writeb(s, addr, val & 0xff);
1903 lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1904 lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1905 lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1906 }
1907
1908 static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
1909 uint32_t addr, uint32_t size, int type)
1910 {
1911 LSIState *s = (LSIState *)pci_dev;
1912
1913 DPRINTF("Mapping IO at %08x\n", addr);
1914
1915 register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1916 register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1917 register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1918 register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1919 register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1920 register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1921 }
1922
1923 static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
1924 uint32_t addr, uint32_t size, int type)
1925 {
1926 LSIState *s = (LSIState *)pci_dev;
1927
1928 DPRINTF("Mapping ram at %08x\n", addr);
1929 s->script_ram_base = addr;
1930 cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1931 }
1932
1933 static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
1934 uint32_t addr, uint32_t size, int type)
1935 {
1936 LSIState *s = (LSIState *)pci_dev;
1937
1938 DPRINTF("Mapping registers at %08x\n", addr);
1939 cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
1940 }
1941
1942 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id)
1943 {
1944 LSIState *s = (LSIState *)opaque;
1945
1946 if (id < 0) {
1947 for (id = 0; id < LSI_MAX_DEVS; id++) {
1948 if (s->scsi_dev[id] == NULL)
1949 break;
1950 }
1951 }
1952 if (id >= LSI_MAX_DEVS) {
1953 BADF("Bad Device ID %d\n", id);
1954 return;
1955 }
1956 if (s->scsi_dev[id]) {
1957 DPRINTF("Destroying device %d\n", id);
1958 s->scsi_dev[id]->destroy(s->scsi_dev[id]);
1959 }
1960 DPRINTF("Attaching block device %d\n", id);
1961 s->scsi_dev[id] = scsi_generic_init(bd, 1, lsi_command_complete, s);
1962 if (s->scsi_dev[id] == NULL)
1963 s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
1964 bd->private = &s->pci_dev;
1965 }
1966
1967 static int lsi_scsi_uninit(PCIDevice *d)
1968 {
1969 LSIState *s = (LSIState *) d;
1970
1971 cpu_unregister_io_memory(s->mmio_io_addr);
1972 cpu_unregister_io_memory(s->ram_io_addr);
1973
1974 qemu_free(s->queue);
1975
1976 return 0;
1977 }
1978
1979 void *lsi_scsi_init(PCIBus *bus, int devfn)
1980 {
1981 LSIState *s;
1982 uint8_t *pci_conf;
1983
1984 s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA",
1985 sizeof(*s), devfn, NULL, NULL);
1986 if (s == NULL) {
1987 fprintf(stderr, "lsi-scsi: Failed to register PCI device\n");
1988 return NULL;
1989 }
1990
1991 pci_conf = s->pci_dev.config;
1992
1993 /* PCI Vendor ID (word) */
1994 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_LSI_LOGIC);
1995 /* PCI device ID (word) */
1996 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_LSI_53C895A);
1997 /* PCI base class code */
1998 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_SCSI);
1999 /* PCI subsystem ID */
2000 pci_conf[0x2e] = 0x00;
2001 pci_conf[0x2f] = 0x10;
2002 /* PCI latency timer = 255 */
2003 pci_conf[0x0d] = 0xff;
2004 /* Interrupt pin 1 */
2005 pci_conf[0x3d] = 0x01;
2006
2007 s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn,
2008 lsi_mmio_writefn, s);
2009 s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn,
2010 lsi_ram_writefn, s);
2011
2012 pci_register_io_region((struct PCIDevice *)s, 0, 256,
2013 PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);
2014 pci_register_io_region((struct PCIDevice *)s, 1, 0x400,
2015 PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);
2016 pci_register_io_region((struct PCIDevice *)s, 2, 0x2000,
2017 PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);
2018 s->queue = qemu_malloc(sizeof(lsi_queue));
2019 s->queue_len = 1;
2020 s->active_commands = 0;
2021 s->pci_dev.unregister = lsi_scsi_uninit;
2022
2023 lsi_soft_reset(s);
2024
2025 return s;
2026 }
kvm userspace components