qemu/qemu-kvm-x86.c

   1 /*
   2  * qemu/kvm integration, x86 specific code
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  *
   6  * Licensed under the terms of the GNU GPL version 2 or higher.
   7  */
   8
   9 #include "config.h"
  10 #include "config-host.h"
  11
  12 #include <string.h>
  13 #include "hw/hw.h"
  14 #include "gdbstub.h"
  15 #include <sys/io.h>
  16
  17 #include "qemu-kvm.h"
  18 #include <libkvm.h>
  19 #include <pthread.h>
  20 #include <sys/utsname.h>
  21 #include <linux/kvm_para.h>
  22
  23 #define MSR_IA32_TSC            0x10
  24
  25 static struct kvm_msr_list *kvm_msr_list;
  26 extern unsigned int kvm_shadow_memory;
  27 static int kvm_has_msr_star;
  28
  29 static int lm_capable_kernel;
  30
  31 int kvm_qemu_create_memory_alias(uint64_t phys_start,
  32                                  uint64_t len,
  33                                  uint64_t target_phys)
  34 {
  35     return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
  36 }
  37
  38 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
  39 {
  40         return kvm_destroy_memory_alias(kvm_context, phys_start);
  41 }
  42
  43 int kvm_arch_qemu_create_context(void)
  44 {
  45     int i;
  46     struct utsname utsname;
  47
  48     uname(&utsname);
  49     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
  50
  51     if (kvm_shadow_memory)
  52         kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
  53
  54     kvm_msr_list = kvm_get_msr_list(kvm_context);
  55     if (!kvm_msr_list)
  56                 return -1;
  57     for (i = 0; i < kvm_msr_list->nmsrs; ++i)
  58         if (kvm_msr_list->indices[i] == MSR_STAR)
  59             kvm_has_msr_star = 1;
  60         return 0;
  61 }
  62
  63 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
  64                           uint64_t data)
  65 {
  66     entry->index = index;
  67     entry->data  = data;
  68 }
  69
  70 /* returns 0 on success, non-0 on failure */
  71 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
  72 {
  73         switch (entry->index) {
  74         case MSR_IA32_SYSENTER_CS:
  75             env->sysenter_cs  = entry->data;
  76             break;
  77         case MSR_IA32_SYSENTER_ESP:
  78             env->sysenter_esp = entry->data;
  79             break;
  80         case MSR_IA32_SYSENTER_EIP:
  81             env->sysenter_eip = entry->data;
  82             break;
  83         case MSR_STAR:
  84             env->star         = entry->data;
  85             break;
  86 #ifdef TARGET_X86_64
  87         case MSR_CSTAR:
  88             env->cstar        = entry->data;
  89             break;
  90         case MSR_KERNELGSBASE:
  91             env->kernelgsbase = entry->data;
  92             break;
  93         case MSR_FMASK:
  94             env->fmask        = entry->data;
  95             break;
  96         case MSR_LSTAR:
  97             env->lstar        = entry->data;
  98             break;
  99 #endif
 100         case MSR_IA32_TSC:
 101             env->tsc          = entry->data;
 102             break;
 103         case MSR_VM_HSAVE_PA:
 104             env->vm_hsave     = entry->data;
 105             break;
 106         default:
 107             printf("Warning unknown msr index 0x%x\n", entry->index);
 108             return 1;
 109         }
 110         return 0;
 111 }
 112
 113 #ifdef TARGET_X86_64
 114 #define MSR_COUNT 9
 115 #else
 116 #define MSR_COUNT 5
 117 #endif
 118
 119 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 120 {
 121     lhs->selector = rhs->selector;
 122     lhs->base = rhs->base;
 123     lhs->limit = rhs->limit;
 124     lhs->type = 3;
 125     lhs->present = 1;
 126     lhs->dpl = 3;
 127     lhs->db = 0;
 128     lhs->s = 1;
 129     lhs->l = 0;
 130     lhs->g = 0;
 131     lhs->avl = 0;
 132     lhs->unusable = 0;
 133 }
 134
 135 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 136 {
 137     unsigned flags = rhs->flags;
 138     lhs->selector = rhs->selector;
 139     lhs->base = rhs->base;
 140     lhs->limit = rhs->limit;
 141     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 142     lhs->present = (flags & DESC_P_MASK) != 0;
 143     lhs->dpl = rhs->selector & 3;
 144     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 145     lhs->s = (flags & DESC_S_MASK) != 0;
 146     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 147     lhs->g = (flags & DESC_G_MASK) != 0;
 148     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 149     lhs->unusable = 0;
 150 }
 151
 152 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 153 {
 154     lhs->selector = rhs->selector;
 155     lhs->base = rhs->base;
 156     lhs->limit = rhs->limit;
 157     lhs->flags =
 158         (rhs->type << DESC_TYPE_SHIFT)
 159         | (rhs->present * DESC_P_MASK)
 160         | (rhs->dpl << DESC_DPL_SHIFT)
 161         | (rhs->db << DESC_B_SHIFT)
 162         | (rhs->s * DESC_S_MASK)
 163         | (rhs->l << DESC_L_SHIFT)
 164         | (rhs->g * DESC_G_MASK)
 165         | (rhs->avl * DESC_AVL_MASK);
 166 }
 167
 168 void kvm_arch_load_regs(CPUState *env)
 169 {
 170     struct kvm_regs regs;
 171     struct kvm_fpu fpu;
 172     struct kvm_sregs sregs;
 173     struct kvm_msr_entry msrs[MSR_COUNT];
 174     int rc, n, i;
 175
 176     regs.rax = env->regs[R_EAX];
 177     regs.rbx = env->regs[R_EBX];
 178     regs.rcx = env->regs[R_ECX];
 179     regs.rdx = env->regs[R_EDX];
 180     regs.rsi = env->regs[R_ESI];
 181     regs.rdi = env->regs[R_EDI];
 182     regs.rsp = env->regs[R_ESP];
 183     regs.rbp = env->regs[R_EBP];
 184 #ifdef TARGET_X86_64
 185     regs.r8 = env->regs[8];
 186     regs.r9 = env->regs[9];
 187     regs.r10 = env->regs[10];
 188     regs.r11 = env->regs[11];
 189     regs.r12 = env->regs[12];
 190     regs.r13 = env->regs[13];
 191     regs.r14 = env->regs[14];
 192     regs.r15 = env->regs[15];
 193 #endif
 194
 195     regs.rflags = env->eflags;
 196     regs.rip = env->eip;
 197
 198     kvm_set_regs(kvm_context, env->cpu_index, &regs);
 199
 200     memset(&fpu, 0, sizeof fpu);
 201     fpu.fsw = env->fpus & ~(7 << 11);
 202     fpu.fsw |= (env->fpstt & 7) << 11;
 203     fpu.fcw = env->fpuc;
 204     for (i = 0; i < 8; ++i)
 205         fpu.ftwx |= (!env->fptags[i]) << i;
 206     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 207     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 208     fpu.mxcsr = env->mxcsr;
 209     kvm_set_fpu(kvm_context, env->cpu_index, &fpu);
 210
 211     memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
 212
 213     if ((env->eflags & VM_MASK)) {
 214             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 215             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 216             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 217             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 218             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 219             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 220     } else {
 221             set_seg(&sregs.cs, &env->segs[R_CS]);
 222             set_seg(&sregs.ds, &env->segs[R_DS]);
 223             set_seg(&sregs.es, &env->segs[R_ES]);
 224             set_seg(&sregs.fs, &env->segs[R_FS]);
 225             set_seg(&sregs.gs, &env->segs[R_GS]);
 226             set_seg(&sregs.ss, &env->segs[R_SS]);
 227
 228             if (env->cr[0] & CR0_PE_MASK) {
 229                 /* force ss cpl to cs cpl */
 230                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 231                         (sregs.cs.selector & 3);
 232                 sregs.ss.dpl = sregs.ss.selector & 3;
 233             }
 234     }
 235
 236     set_seg(&sregs.tr, &env->tr);
 237     set_seg(&sregs.ldt, &env->ldt);
 238
 239     sregs.idt.limit = env->idt.limit;
 240     sregs.idt.base = env->idt.base;
 241     sregs.gdt.limit = env->gdt.limit;
 242     sregs.gdt.base = env->gdt.base;
 243
 244     sregs.cr0 = env->cr[0];
 245     sregs.cr2 = env->cr[2];
 246     sregs.cr3 = env->cr[3];
 247     sregs.cr4 = env->cr[4];
 248
 249     sregs.cr8 = cpu_get_apic_tpr(env);
 250     sregs.apic_base = cpu_get_apic_base(env);
 251
 252     sregs.efer = env->efer;
 253
 254     kvm_set_sregs(kvm_context, env->cpu_index, &sregs);
 255
 256     /* msrs */
 257     n = 0;
 258     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS,  env->sysenter_cs);
 259     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 260     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 261     if (kvm_has_msr_star)
 262         set_msr_entry(&msrs[n++], MSR_STAR,              env->star);
 263     set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 264 #ifdef TARGET_X86_64
 265     if (lm_capable_kernel) {
 266         set_msr_entry(&msrs[n++], MSR_CSTAR,             env->cstar);
 267         set_msr_entry(&msrs[n++], MSR_KERNELGSBASE,      env->kernelgsbase);
 268         set_msr_entry(&msrs[n++], MSR_FMASK,             env->fmask);
 269         set_msr_entry(&msrs[n++], MSR_LSTAR  ,           env->lstar);
 270     }
 271 #endif
 272
 273     rc = kvm_set_msrs(kvm_context, env->cpu_index, msrs, n);
 274     if (rc == -1)
 275         perror("kvm_set_msrs FAILED");
 276 }
 277
 278 void kvm_load_tsc(CPUState *env)
 279 {
 280     int rc;
 281     struct kvm_msr_entry msr;
 282
 283     set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
 284
 285     rc = kvm_set_msrs(kvm_context, env->cpu_index, &msr, 1);
 286     if (rc == -1)
 287         perror("kvm_set_tsc FAILED.\n");
 288 }
 289
 290 void kvm_save_mpstate(CPUState *env)
 291 {
 292 #ifdef KVM_CAP_MP_STATE
 293     int r;
 294     struct kvm_mp_state mp_state;
 295
 296     r = kvm_get_mpstate(kvm_context, env->cpu_index, &mp_state);
 297     if (r < 0)
 298         env->mp_state = -1;
 299     else
 300         env->mp_state = mp_state.mp_state;
 301 #endif
 302 }
 303
 304 void kvm_load_mpstate(CPUState *env)
 305 {
 306 #ifdef KVM_CAP_MP_STATE
 307     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 308
 309     /*
 310      * -1 indicates that the host did not support GET_MP_STATE ioctl,
 311      *  so don't touch it.
 312      */
 313     if (env->mp_state != -1)
 314         kvm_set_mpstate(kvm_context, env->cpu_index, &mp_state);
 315 #endif
 316 }
 317
 318 void kvm_arch_save_regs(CPUState *env)
 319 {
 320     struct kvm_regs regs;
 321     struct kvm_fpu fpu;
 322     struct kvm_sregs sregs;
 323     struct kvm_msr_entry msrs[MSR_COUNT];
 324     uint32_t hflags;
 325     uint32_t i, n, rc;
 326
 327     kvm_get_regs(kvm_context, env->cpu_index, &regs);
 328
 329     env->regs[R_EAX] = regs.rax;
 330     env->regs[R_EBX] = regs.rbx;
 331     env->regs[R_ECX] = regs.rcx;
 332     env->regs[R_EDX] = regs.rdx;
 333     env->regs[R_ESI] = regs.rsi;
 334     env->regs[R_EDI] = regs.rdi;
 335     env->regs[R_ESP] = regs.rsp;
 336     env->regs[R_EBP] = regs.rbp;
 337 #ifdef TARGET_X86_64
 338     env->regs[8] = regs.r8;
 339     env->regs[9] = regs.r9;
 340     env->regs[10] = regs.r10;
 341     env->regs[11] = regs.r11;
 342     env->regs[12] = regs.r12;
 343     env->regs[13] = regs.r13;
 344     env->regs[14] = regs.r14;
 345     env->regs[15] = regs.r15;
 346 #endif
 347
 348     env->eflags = regs.rflags;
 349     env->eip = regs.rip;
 350
 351     kvm_get_fpu(kvm_context, env->cpu_index, &fpu);
 352     env->fpstt = (fpu.fsw >> 11) & 7;
 353     env->fpus = fpu.fsw;
 354     env->fpuc = fpu.fcw;
 355     for (i = 0; i < 8; ++i)
 356         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 357     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 358     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 359     env->mxcsr = fpu.mxcsr;
 360
 361     kvm_get_sregs(kvm_context, env->cpu_index, &sregs);
 362
 363     memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
 364
 365     get_seg(&env->segs[R_CS], &sregs.cs);
 366     get_seg(&env->segs[R_DS], &sregs.ds);
 367     get_seg(&env->segs[R_ES], &sregs.es);
 368     get_seg(&env->segs[R_FS], &sregs.fs);
 369     get_seg(&env->segs[R_GS], &sregs.gs);
 370     get_seg(&env->segs[R_SS], &sregs.ss);
 371
 372     get_seg(&env->tr, &sregs.tr);
 373     get_seg(&env->ldt, &sregs.ldt);
 374
 375     env->idt.limit = sregs.idt.limit;
 376     env->idt.base = sregs.idt.base;
 377     env->gdt.limit = sregs.gdt.limit;
 378     env->gdt.base = sregs.gdt.base;
 379
 380     env->cr[0] = sregs.cr0;
 381     env->cr[2] = sregs.cr2;
 382     env->cr[3] = sregs.cr3;
 383     env->cr[4] = sregs.cr4;
 384
 385     cpu_set_apic_base(env, sregs.apic_base);
 386
 387     env->efer = sregs.efer;
 388     //cpu_set_apic_tpr(env, sregs.cr8);
 389
 390 #define HFLAG_COPY_MASK ~( \
 391                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 392                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 393                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 394                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 395
 396
 397
 398     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 399     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 400     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 401             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 402     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 403     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 404             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 405
 406     if (env->efer & MSR_EFER_LMA) {
 407         hflags |= HF_LMA_MASK;
 408     }
 409
 410     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 411         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 412     } else {
 413         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 414                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 415         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 416                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 417         if (!(env->cr[0] & CR0_PE_MASK) ||
 418                    (env->eflags & VM_MASK) ||
 419                    !(hflags & HF_CS32_MASK)) {
 420                 hflags |= HF_ADDSEG_MASK;
 421             } else {
 422                 hflags |= ((env->segs[R_DS].base |
 423                                 env->segs[R_ES].base |
 424                                 env->segs[R_SS].base) != 0) <<
 425                     HF_ADDSEG_SHIFT;
 426             }
 427     }
 428     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 429
 430     /* msrs */
 431     n = 0;
 432     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 433     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 434     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 435     if (kvm_has_msr_star)
 436         msrs[n++].index = MSR_STAR;
 437     msrs[n++].index = MSR_IA32_TSC;
 438     msrs[n++].index = MSR_VM_HSAVE_PA;
 439 #ifdef TARGET_X86_64
 440     if (lm_capable_kernel) {
 441         msrs[n++].index = MSR_CSTAR;
 442         msrs[n++].index = MSR_KERNELGSBASE;
 443         msrs[n++].index = MSR_FMASK;
 444         msrs[n++].index = MSR_LSTAR;
 445     }
 446 #endif
 447     rc = kvm_get_msrs(kvm_context, env->cpu_index, msrs, n);
 448     if (rc == -1) {
 449         perror("kvm_get_msrs FAILED");
 450     }
 451     else {
 452         n = rc; /* actual number of MSRs */
 453         for (i=0 ; i<n; i++) {
 454             if (get_msr_entry(&msrs[i], env))
 455                 return;
 456         }
 457     }
 458 }
 459
 460 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
 461                          uint32_t count, CPUState *env)
 462 {
 463     env->regs[R_EAX] = function;
 464     env->regs[R_ECX] = count;
 465     qemu_kvm_cpuid_on_env(env);
 466     e->function = function;
 467     e->flags = 0;
 468     e->index = 0;
 469     e->eax = env->regs[R_EAX];
 470     e->ebx = env->regs[R_EBX];
 471     e->ecx = env->regs[R_ECX];
 472     e->edx = env->regs[R_EDX];
 473 }
 474
 475 struct kvm_para_features {
 476         int cap;
 477         int feature;
 478 } para_features[] = {
 479 #ifdef KVM_CAP_CLOCKSOURCE
 480         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 481 #endif
 482 #ifdef KVM_CAP_NOP_IO_DELAY
 483         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 484 #endif
 485 #ifdef KVM_CAP_PV_MMU
 486         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 487 #endif
 488 #ifdef KVM_CAP_CR3_CACHE
 489         { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
 490 #endif
 491         { -1, -1 }
 492 };
 493
 494 static int get_para_features(kvm_context_t kvm_context)
 495 {
 496         int i, features = 0;
 497
 498         for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
 499                 if (kvm_check_extension(kvm_context, para_features[i].cap))
 500                         features |= (1 << para_features[i].feature);
 501         }
 502
 503         return features;
 504 }
 505
 506 int kvm_arch_qemu_init_env(CPUState *cenv)
 507 {
 508     struct kvm_cpuid_entry2 cpuid_ent[100];
 509 #ifdef KVM_CPUID_SIGNATURE
 510     struct kvm_cpuid_entry2 *pv_ent;
 511     uint32_t signature[3];
 512 #endif
 513     int cpuid_nent = 0;
 514     CPUState copy;
 515     uint32_t i, j, limit;
 516
 517     copy = *cenv;
 518
 519 #ifdef KVM_CPUID_SIGNATURE
 520     /* Paravirtualization CPUIDs */
 521     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 522     pv_ent = &cpuid_ent[cpuid_nent++];
 523     memset(pv_ent, 0, sizeof(*pv_ent));
 524     pv_ent->function = KVM_CPUID_SIGNATURE;
 525     pv_ent->eax = 0;
 526     pv_ent->ebx = signature[0];
 527     pv_ent->ecx = signature[1];
 528     pv_ent->edx = signature[2];
 529
 530     pv_ent = &cpuid_ent[cpuid_nent++];
 531     memset(pv_ent, 0, sizeof(*pv_ent));
 532     pv_ent->function = KVM_CPUID_FEATURES;
 533     pv_ent->eax = get_para_features(kvm_context);
 534 #endif
 535
 536     copy.regs[R_EAX] = 0;
 537     qemu_kvm_cpuid_on_env(&copy);
 538     limit = copy.regs[R_EAX];
 539
 540     for (i = 0; i <= limit; ++i) {
 541         if (i == 4 || i == 0xb || i == 0xd) {
 542             for (j = 0; ; ++j) {
 543                 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
 544
 545                 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 546                 cpuid_ent[cpuid_nent].index = j;
 547
 548                 cpuid_nent++;
 549
 550                 if (i == 4 && copy.regs[R_EAX] == 0)
 551                     break;
 552                 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
 553                     break;
 554                 if (i == 0xd && copy.regs[R_EAX] == 0)
 555                     break;
 556             }
 557         } else
 558             do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
 559     }
 560
 561     copy.regs[R_EAX] = 0x80000000;
 562     qemu_kvm_cpuid_on_env(&copy);
 563     limit = copy.regs[R_EAX];
 564
 565     for (i = 0x80000000; i <= limit; ++i)
 566         do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
 567
 568     kvm_setup_cpuid2(kvm_context, cenv->cpu_index, cpuid_nent, cpuid_ent);
 569     return 0;
 570 }
 571
 572 int kvm_arch_halt(void *opaque, int vcpu)
 573 {
 574     CPUState *env = cpu_single_env;
 575
 576     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 577           (env->eflags & IF_MASK)) &&
 578         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 579             env->halted = 1;
 580             env->exception_index = EXCP_HLT;
 581     }
 582     return 1;
 583 }
 584
 585 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
 586 {
 587     if (!kvm_irqchip_in_kernel(kvm_context))
 588         kvm_set_cr8(kvm_context, env->cpu_index, cpu_get_apic_tpr(env));
 589 }
 590
 591 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
 592 {
 593     int vcpu = env->cpu_index;
 594
 595     cpu_single_env = env;
 596
 597     env->eflags = kvm_get_interrupt_flag(kvm_context, vcpu)
 598         ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
 599
 600     cpu_set_apic_tpr(env, kvm_get_cr8(kvm_context, vcpu));
 601     cpu_set_apic_base(env, kvm_get_apic_base(kvm_context, vcpu));
 602 }
 603
 604 int kvm_arch_has_work(CPUState *env)
 605 {
 606     if (env->exit_request ||
 607         ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 608          (env->eflags & IF_MASK)) ||
 609         (env->interrupt_request & CPU_INTERRUPT_NMI))
 610         return 1;
 611     return 0;
 612 }
 613
 614 int kvm_arch_try_push_interrupts(void *opaque)
 615 {
 616     CPUState *env = cpu_single_env;
 617     int r, irq;
 618
 619     if (kvm_is_ready_for_interrupt_injection(kvm_context, env->cpu_index) &&
 620         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 621         (env->eflags & IF_MASK)) {
 622             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 623             irq = cpu_get_pic_interrupt(env);
 624             if (irq >= 0) {
 625                 r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
 626                 if (r < 0)
 627                     printf("cpu %d fail inject %x\n", env->cpu_index, irq);
 628             }
 629     }
 630
 631     return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
 632 }
 633
 634 #ifdef KVM_CAP_USER_NMI
 635 void kvm_arch_push_nmi(void *opaque)
 636 {
 637     CPUState *env = cpu_single_env;
 638     int r;
 639
 640     if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
 641         return;
 642
 643     env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 644     r = kvm_inject_nmi(kvm_context, env->cpu_index);
 645     if (r < 0)
 646         printf("cpu %d fail inject NMI\n", env->cpu_index);
 647 }
 648 #endif /* KVM_CAP_USER_NMI */
 649
 650 void kvm_arch_update_regs_for_sipi(CPUState *env)
 651 {
 652     SegmentCache cs = env->segs[R_CS];
 653
 654     kvm_arch_save_regs(env);
 655     env->segs[R_CS] = cs;
 656     env->eip = 0;
 657     kvm_arch_load_regs(env);
 658 }
 659
 660 int handle_tpr_access(void *opaque, int vcpu,
 661                              uint64_t rip, int is_write)
 662 {
 663     kvm_tpr_access_report(cpu_single_env, rip, is_write);
 664     return 0;
 665 }
 666
 667 void kvm_arch_cpu_reset(CPUState *env)
 668 {
 669     kvm_arch_load_regs(env);
 670     if (env->cpu_index != 0) {
 671         if (kvm_irqchip_in_kernel(kvm_context)) {
 672 #ifdef KVM_CAP_MP_STATE
 673             kvm_reset_mpstate(kvm_context, env->cpu_index);
 674 #endif
 675         } else {
 676             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 677             env->halted = 1;
 678             env->exception_index = EXCP_HLT;
 679         }
 680     }
 681 }
 682
 683 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 684 {
 685     uint8_t int3 = 0xcc;
 686
 687     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 688         cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
 689         return -EINVAL;
 690     return 0;
 691 }
 692
 693 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 694 {
 695     uint8_t int3;
 696
 697     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 698         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 699         return -EINVAL;
 700     return 0;
 701 }
 702
 703 #ifdef KVM_CAP_SET_GUEST_DEBUG
 704 static struct {
 705     target_ulong addr;
 706     int len;
 707     int type;
 708 } hw_breakpoint[4];
 709
 710 static int nb_hw_breakpoint;
 711
 712 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 713 {
 714     int n;
 715
 716     for (n = 0; n < nb_hw_breakpoint; n++)
 717         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 718             (hw_breakpoint[n].len == len || len == -1))
 719             return n;
 720     return -1;
 721 }
 722
 723 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 724                                   target_ulong len, int type)
 725 {
 726     switch (type) {
 727     case GDB_BREAKPOINT_HW:
 728         len = 1;
 729         break;
 730     case GDB_WATCHPOINT_WRITE:
 731     case GDB_WATCHPOINT_ACCESS:
 732         switch (len) {
 733         case 1:
 734             break;
 735         case 2:
 736         case 4:
 737         case 8:
 738             if (addr & (len - 1))
 739                 return -EINVAL;
 740             break;
 741         default:
 742             return -EINVAL;
 743         }
 744         break;
 745     default:
 746         return -ENOSYS;
 747     }
 748
 749     if (nb_hw_breakpoint == 4)
 750         return -ENOBUFS;
 751
 752     if (find_hw_breakpoint(addr, len, type) >= 0)
 753         return -EEXIST;
 754
 755     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 756     hw_breakpoint[nb_hw_breakpoint].len = len;
 757     hw_breakpoint[nb_hw_breakpoint].type = type;
 758     nb_hw_breakpoint++;
 759
 760     return 0;
 761 }
 762
 763 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 764                                   target_ulong len, int type)
 765 {
 766     int n;
 767
 768     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
 769     if (n < 0)
 770         return -ENOENT;
 771
 772     nb_hw_breakpoint--;
 773     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
 774
 775     return 0;
 776 }
 777
 778 void kvm_arch_remove_all_hw_breakpoints(void)
 779 {
 780     nb_hw_breakpoint = 0;
 781 }
 782
 783 static CPUWatchpoint hw_watchpoint;
 784
 785 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
 786 {
 787     int handle = 0;
 788     int n;
 789
 790     if (arch_info->exception == 1) {
 791         if (arch_info->dr6 & (1 << 14)) {
 792             if (cpu_single_env->singlestep_enabled)
 793                 handle = 1;
 794         } else {
 795             for (n = 0; n < 4; n++)
 796                 if (arch_info->dr6 & (1 << n))
 797                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
 798                     case 0x0:
 799                         handle = 1;
 800                         break;
 801                     case 0x1:
 802                         handle = 1;
 803                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 804                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 805                         hw_watchpoint.flags = BP_MEM_WRITE;
 806                         break;
 807                     case 0x3:
 808                         handle = 1;
 809                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 810                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 811                         hw_watchpoint.flags = BP_MEM_ACCESS;
 812                         break;
 813                     }
 814         }
 815     } else if (kvm_find_sw_breakpoint(arch_info->pc))
 816         handle = 1;
 817
 818     if (!handle)
 819         kvm_update_guest_debug(cpu_single_env,
 820                         (arch_info->exception == 1) ?
 821                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
 822
 823     return handle;
 824 }
 825
 826 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
 827 {
 828     const uint8_t type_code[] = {
 829         [GDB_BREAKPOINT_HW] = 0x0,
 830         [GDB_WATCHPOINT_WRITE] = 0x1,
 831         [GDB_WATCHPOINT_ACCESS] = 0x3
 832     };
 833     const uint8_t len_code[] = {
 834         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
 835     };
 836     int n;
 837
 838     if (!TAILQ_EMPTY(&kvm_sw_breakpoints))
 839         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
 840
 841     if (nb_hw_breakpoint > 0) {
 842         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
 843         dbg->arch.debugreg[7] = 0x0600;
 844         for (n = 0; n < nb_hw_breakpoint; n++) {
 845             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
 846             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
 847                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
 848                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
 849         }
 850     }
 851 }
 852 #endif
 853
 854 void kvm_arch_do_ioperm(void *_data)
 855 {
 856     struct ioperm_data *data = _data;
 857     ioperm(data->start_port, data->num, data->turn_on);
 858 }