qemu/hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "vl.h"
  25
  26 #ifdef USE_KVM
  27 #include "qemu-kvm.h"
  28 #endif
  29
  30 /* debug PIC */
  31 //#define DEBUG_PIC
  32
  33 //#define DEBUG_IRQ_LATENCY
  34 //#define DEBUG_IRQ_COUNT
  35
  36 typedef struct PicState {
  37     uint8_t last_irr; /* edge detection */
  38     uint8_t irr; /* interrupt request register */
  39     uint8_t imr; /* interrupt mask register */
  40     uint8_t isr; /* interrupt service register */
  41     uint8_t priority_add; /* highest irq priority */
  42     uint8_t irq_base;
  43     uint8_t read_reg_select;
  44     uint8_t poll;
  45     uint8_t special_mask;
  46     uint8_t init_state;
  47     uint8_t auto_eoi;
  48     uint8_t rotate_on_auto_eoi;
  49     uint8_t special_fully_nested_mode;
  50     uint8_t init4; /* true if 4 byte init */
  51     uint8_t single_mode; /* true if slave pic is not initialized */
  52     uint8_t elcr; /* PIIX edge/trigger selection*/
  53     uint8_t elcr_mask;
  54     PicState2 *pics_state;
  55 } PicState;
  56
  57 struct PicState2 {
  58     /* 0 is master pic, 1 is slave pic */
  59     /* XXX: better separation between the two pics */
  60     PicState pics[2];
  61     qemu_irq parent_irq;
  62     void *irq_request_opaque;
  63     /* IOAPIC callback support */
  64     SetIRQFunc *alt_irq_func;
  65     void *alt_irq_opaque;
  66 };
  67
  68 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  69 static int irq_level[16];
  70 #endif
  71 #ifdef DEBUG_IRQ_COUNT
  72 static uint64_t irq_count[16];
  73 #endif
  74
  75 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  76 static inline void pic_set_irq1(PicState *s, int irq, int level)
  77 {
  78     int mask;
  79     mask = 1 << irq;
  80     if (s->elcr & mask) {
  81         /* level triggered */
  82         if (level) {
  83             s->irr |= mask;
  84             s->last_irr |= mask;
  85         } else {
  86             s->irr &= ~mask;
  87             s->last_irr &= ~mask;
  88         }
  89     } else {
  90         /* edge triggered */
  91         if (level) {
  92             if ((s->last_irr & mask) == 0)
  93                 s->irr |= mask;
  94             s->last_irr |= mask;
  95         } else {
  96             s->last_irr &= ~mask;
  97         }
  98     }
  99 }
 100
 101 /* return the highest priority found in mask (highest = smallest
 102    number). Return 8 if no irq */
 103 static inline int get_priority(PicState *s, int mask)
 104 {
 105     int priority;
 106     if (mask == 0)
 107         return 8;
 108     priority = 0;
 109     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 110         priority++;
 111     return priority;
 112 }
 113
 114 /* return the pic wanted interrupt. return -1 if none */
 115 static int pic_get_irq(PicState *s)
 116 {
 117     int mask, cur_priority, priority;
 118
 119     mask = s->irr & ~s->imr;
 120     priority = get_priority(s, mask);
 121     if (priority == 8)
 122         return -1;
 123     /* compute current priority. If special fully nested mode on the
 124        master, the IRQ coming from the slave is not taken into account
 125        for the priority computation. */
 126     mask = s->isr;
 127     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 128         mask &= ~(1 << 2);
 129     cur_priority = get_priority(s, mask);
 130     if (priority < cur_priority) {
 131         /* higher priority found: an irq should be generated */
 132         return (priority + s->priority_add) & 7;
 133     } else {
 134         return -1;
 135     }
 136 }
 137
 138 /* raise irq to CPU if necessary. must be called every time the active
 139    irq may change */
 140 /* XXX: should not export it, but it is needed for an APIC kludge */
 141 void pic_update_irq(PicState2 *s)
 142 {
 143     int irq2, irq;
 144
 145     /* first look at slave pic */
 146     irq2 = pic_get_irq(&s->pics[1]);
 147     if (irq2 >= 0) {
 148         /* if irq request by slave pic, signal master PIC */
 149         pic_set_irq1(&s->pics[0], 2, 1);
 150         pic_set_irq1(&s->pics[0], 2, 0);
 151     }
 152     /* look at requested irq */
 153     irq = pic_get_irq(&s->pics[0]);
 154     if (irq >= 0) {
 155 #if defined(DEBUG_PIC)
 156         {
 157             int i;
 158             for(i = 0; i < 2; i++) {
 159                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 160                        i, s->pics[i].imr, s->pics[i].irr,
 161                        s->pics[i].priority_add);
 162
 163             }
 164         }
 165         printf("pic: cpu_interrupt\n");
 166 #endif
 167         qemu_irq_raise(s->parent_irq);
 168     }
 169
 170 /* all targets should do this rather than acking the IRQ in the cpu */
 171 #if defined(TARGET_MIPS)
 172     else {
 173         qemu_irq_lower(s->parent_irq);
 174     }
 175 #endif
 176 }
 177
 178 #ifdef DEBUG_IRQ_LATENCY
 179 int64_t irq_time[16];
 180 #endif
 181
 182 void i8259_set_irq(void *opaque, int irq, int level)
 183 {
 184     PicState2 *s = opaque;
 185 #ifdef USE_KVM
 186 #ifdef KVM_CAP_IRQCHIP
 187     extern int kvm_set_irq(int irq, int level);
 188
 189     if (kvm_allowed)
 190         if (kvm_set_irq(irq, level))
 191             return;
 192 #endif
 193 #endif
 194 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 195     if (level != irq_level[irq]) {
 196 #if defined(DEBUG_PIC)
 197         printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
 198 #endif
 199         irq_level[irq] = level;
 200 #ifdef DEBUG_IRQ_COUNT
 201         if (level == 1)
 202             irq_count[irq]++;
 203 #endif
 204     }
 205 #endif
 206 #ifdef DEBUG_IRQ_LATENCY
 207     if (level) {
 208         irq_time[irq] = qemu_get_clock(vm_clock);
 209     }
 210 #endif
 211     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 212     /* used for IOAPIC irqs */
 213     if (s->alt_irq_func)
 214         s->alt_irq_func(s->alt_irq_opaque, irq, level);
 215     pic_update_irq(s);
 216 }
 217
 218 /* acknowledge interrupt 'irq' */
 219 static inline void pic_intack(PicState *s, int irq)
 220 {
 221     if (s->auto_eoi) {
 222         if (s->rotate_on_auto_eoi)
 223             s->priority_add = (irq + 1) & 7;
 224     } else {
 225         s->isr |= (1 << irq);
 226     }
 227
 228     /* We don't clear a level sensitive interrupt here */
 229     if (!(s->elcr & (1 << irq)))
 230         s->irr &= ~(1 << irq);
 231
 232 }
 233
 234 int pic_read_irq(PicState2 *s)
 235 {
 236     int irq, irq2, intno;
 237
 238     irq = pic_get_irq(&s->pics[0]);
 239     if (irq >= 0) {
 240
 241         pic_intack(&s->pics[0], irq);
 242         if (time_drift_fix && irq == 0) {
 243             extern int64_t timer_acks, timer_ints_to_push;
 244             timer_acks++;
 245             if (timer_ints_to_push > 0) {
 246                 timer_ints_to_push--;
 247                 /* simulate an edge irq0, like the one generated by i8254 */
 248                 pic_set_irq1(&s->pics[0], 0, 0);
 249                 pic_set_irq1(&s->pics[0], 0, 1);
 250             }
 251         }
 252
 253         if (irq == 2) {
 254             irq2 = pic_get_irq(&s->pics[1]);
 255             if (irq2 >= 0) {
 256                 pic_intack(&s->pics[1], irq2);
 257             } else {
 258                 /* spurious IRQ on slave controller */
 259                 irq2 = 7;
 260             }
 261             intno = s->pics[1].irq_base + irq2;
 262             irq = irq2 + 8;
 263         } else {
 264             intno = s->pics[0].irq_base + irq;
 265         }
 266     } else {
 267         /* spurious IRQ on host controller */
 268         irq = 7;
 269         intno = s->pics[0].irq_base + irq;
 270     }
 271     pic_update_irq(s);
 272
 273 #ifdef DEBUG_IRQ_LATENCY
 274     printf("IRQ%d latency=%0.3fus\n",
 275            irq,
 276            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 277 #endif
 278 #if defined(DEBUG_PIC)
 279     printf("pic_interrupt: irq=%d\n", irq);
 280 #endif
 281     return intno;
 282 }
 283
 284 static void pic_reset(void *opaque)
 285 {
 286     PicState *s = opaque;
 287
 288     s->last_irr = 0;
 289     s->irr = 0;
 290     s->imr = 0;
 291     s->isr = 0;
 292     s->priority_add = 0;
 293     s->irq_base = 0;
 294     s->read_reg_select = 0;
 295     s->poll = 0;
 296     s->special_mask = 0;
 297     s->init_state = 0;
 298     s->auto_eoi = 0;
 299     s->rotate_on_auto_eoi = 0;
 300     s->special_fully_nested_mode = 0;
 301     s->init4 = 0;
 302     s->single_mode = 0;
 303     /* Note: ELCR is not reset */
 304 }
 305
 306 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 307 {
 308     PicState *s = opaque;
 309     int priority, cmd, irq;
 310
 311 #ifdef DEBUG_PIC
 312     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 313 #endif
 314     addr &= 1;
 315     if (addr == 0) {
 316         if (val & 0x10) {
 317             /* init */
 318             pic_reset(s);
 319             /* deassert a pending interrupt */
 320             qemu_irq_lower(s->pics_state->parent_irq);
 321             s->init_state = 1;
 322             s->init4 = val & 1;
 323             s->single_mode = val & 2;
 324             if (val & 0x08)
 325                 hw_error("level sensitive irq not supported");
 326         } else if (val & 0x08) {
 327             if (val & 0x04)
 328                 s->poll = 1;
 329             if (val & 0x02)
 330                 s->read_reg_select = val & 1;
 331             if (val & 0x40)
 332                 s->special_mask = (val >> 5) & 1;
 333         } else {
 334             cmd = val >> 5;
 335             switch(cmd) {
 336             case 0:
 337             case 4:
 338                 s->rotate_on_auto_eoi = cmd >> 2;
 339                 break;
 340             case 1: /* end of interrupt */
 341             case 5:
 342                 priority = get_priority(s, s->isr);
 343                 if (priority != 8) {
 344                     irq = (priority + s->priority_add) & 7;
 345                     s->isr &= ~(1 << irq);
 346                     if (cmd == 5)
 347                         s->priority_add = (irq + 1) & 7;
 348                     pic_update_irq(s->pics_state);
 349                 }
 350                 break;
 351             case 3:
 352                 irq = val & 7;
 353                 s->isr &= ~(1 << irq);
 354                 pic_update_irq(s->pics_state);
 355                 break;
 356             case 6:
 357                 s->priority_add = (val + 1) & 7;
 358                 pic_update_irq(s->pics_state);
 359                 break;
 360             case 7:
 361                 irq = val & 7;
 362                 s->isr &= ~(1 << irq);
 363                 s->priority_add = (irq + 1) & 7;
 364                 pic_update_irq(s->pics_state);
 365                 break;
 366             default:
 367                 /* no operation */
 368                 break;
 369             }
 370         }
 371     } else {
 372         switch(s->init_state) {
 373         case 0:
 374             /* normal mode */
 375             s->imr = val;
 376             pic_update_irq(s->pics_state);
 377             break;
 378         case 1:
 379             s->irq_base = val & 0xf8;
 380             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 381             break;
 382         case 2:
 383             if (s->init4) {
 384                 s->init_state = 3;
 385             } else {
 386                 s->init_state = 0;
 387             }
 388             break;
 389         case 3:
 390             s->special_fully_nested_mode = (val >> 4) & 1;
 391             s->auto_eoi = (val >> 1) & 1;
 392             s->init_state = 0;
 393             break;
 394         }
 395     }
 396 }
 397
 398 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 399 {
 400     int ret;
 401
 402     ret = pic_get_irq(s);
 403     if (ret >= 0) {
 404         if (addr1 >> 7) {
 405             s->pics_state->pics[0].isr &= ~(1 << 2);
 406             s->pics_state->pics[0].irr &= ~(1 << 2);
 407         }
 408         s->irr &= ~(1 << ret);
 409         s->isr &= ~(1 << ret);
 410         if (addr1 >> 7 || ret != 2)
 411             pic_update_irq(s->pics_state);
 412     } else {
 413         ret = 0x07;
 414         pic_update_irq(s->pics_state);
 415     }
 416
 417     return ret;
 418 }
 419
 420 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 421 {
 422     PicState *s = opaque;
 423     unsigned int addr;
 424     int ret;
 425
 426     addr = addr1;
 427     addr &= 1;
 428     if (s->poll) {
 429         ret = pic_poll_read(s, addr1);
 430         s->poll = 0;
 431     } else {
 432         if (addr == 0) {
 433             if (s->read_reg_select)
 434                 ret = s->isr;
 435             else
 436                 ret = s->irr;
 437         } else {
 438             ret = s->imr;
 439         }
 440     }
 441 #ifdef DEBUG_PIC
 442     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 443 #endif
 444     return ret;
 445 }
 446
 447 /* memory mapped interrupt status */
 448 /* XXX: may be the same than pic_read_irq() */
 449 uint32_t pic_intack_read(PicState2 *s)
 450 {
 451     int ret;
 452
 453     ret = pic_poll_read(&s->pics[0], 0x00);
 454     if (ret == 2)
 455         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 456     /* Prepare for ISR read */
 457     s->pics[0].read_reg_select = 1;
 458
 459     return ret;
 460 }
 461
 462 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 463 {
 464     PicState *s = opaque;
 465     s->elcr = val & s->elcr_mask;
 466 }
 467
 468 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 469 {
 470     PicState *s = opaque;
 471     return s->elcr;
 472 }
 473
 474 #ifdef USE_KVM
 475 #include "qemu-kvm.h"
 476 extern int kvm_allowed;
 477 extern kvm_context_t kvm_context;
 478
 479 static void kvm_kernel_pic_save_to_user(PicState *s)
 480 {
 481 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 482     struct kvm_irqchip chip;
 483     struct kvm_pic_state *kpic;
 484
 485     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 486                    KVM_IRQCHIP_PIC_MASTER :
 487                    KVM_IRQCHIP_PIC_SLAVE;
 488     kvm_get_irqchip(kvm_context, &chip);
 489     kpic = &chip.chip.pic;
 490
 491     s->last_irr = kpic->last_irr;
 492     s->irr = kpic->irr;
 493     s->imr = kpic->imr;
 494     s->isr = kpic->isr;
 495     s->priority_add = kpic->priority_add;
 496     s->irq_base = kpic->irq_base;
 497     s->read_reg_select = kpic->read_reg_select;
 498     s->poll = kpic->poll;
 499     s->special_mask = kpic->special_mask;
 500     s->init_state = kpic->init_state;
 501     s->auto_eoi = kpic->auto_eoi;
 502     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 503     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 504     s->init4 = kpic->init4;
 505     s->elcr = kpic->elcr;
 506     s->elcr_mask = kpic->elcr_mask;
 507 #endif
 508 }
 509
 510 static void kvm_kernel_pic_load_from_user(PicState *s)
 511 {
 512 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 513     struct kvm_irqchip chip;
 514     struct kvm_pic_state *kpic;
 515
 516     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 517                    KVM_IRQCHIP_PIC_MASTER :
 518                    KVM_IRQCHIP_PIC_SLAVE;
 519     kpic = &chip.chip.pic;
 520
 521     kpic->last_irr = s->last_irr;
 522     kpic->irr = s->irr;
 523     kpic->imr = s->imr;
 524     kpic->isr = s->isr;
 525     kpic->priority_add = s->priority_add;
 526     kpic->irq_base = s->irq_base;
 527     kpic->read_reg_select = s->read_reg_select;
 528     kpic->poll = s->poll;
 529     kpic->special_mask = s->special_mask;
 530     kpic->init_state = s->init_state;
 531     kpic->auto_eoi = s->auto_eoi;
 532     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 533     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 534     kpic->init4 = s->init4;
 535     kpic->elcr = s->elcr;
 536     kpic->elcr_mask = s->elcr_mask;
 537
 538     kvm_set_irqchip(kvm_context, &chip);
 539 #endif
 540 }
 541 #endif
 542
 543 static void pic_save(QEMUFile *f, void *opaque)
 544 {
 545     PicState *s = opaque;
 546
 547 #ifdef USE_KVM
 548     if (kvm_allowed && kvm_irqchip_in_kernel(kvm_context)) {
 549         kvm_kernel_pic_save_to_user(s);
 550     }
 551 #endif
 552
 553     qemu_put_8s(f, &s->last_irr);
 554     qemu_put_8s(f, &s->irr);
 555     qemu_put_8s(f, &s->imr);
 556     qemu_put_8s(f, &s->isr);
 557     qemu_put_8s(f, &s->priority_add);
 558     qemu_put_8s(f, &s->irq_base);
 559     qemu_put_8s(f, &s->read_reg_select);
 560     qemu_put_8s(f, &s->poll);
 561     qemu_put_8s(f, &s->special_mask);
 562     qemu_put_8s(f, &s->init_state);
 563     qemu_put_8s(f, &s->auto_eoi);
 564     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 565     qemu_put_8s(f, &s->special_fully_nested_mode);
 566     qemu_put_8s(f, &s->init4);
 567     qemu_put_8s(f, &s->single_mode);
 568     qemu_put_8s(f, &s->elcr);
 569 }
 570
 571 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 572 {
 573     PicState *s = opaque;
 574
 575     if (version_id != 1)
 576         return -EINVAL;
 577
 578     qemu_get_8s(f, &s->last_irr);
 579     qemu_get_8s(f, &s->irr);
 580     qemu_get_8s(f, &s->imr);
 581     qemu_get_8s(f, &s->isr);
 582     qemu_get_8s(f, &s->priority_add);
 583     qemu_get_8s(f, &s->irq_base);
 584     qemu_get_8s(f, &s->read_reg_select);
 585     qemu_get_8s(f, &s->poll);
 586     qemu_get_8s(f, &s->special_mask);
 587     qemu_get_8s(f, &s->init_state);
 588     qemu_get_8s(f, &s->auto_eoi);
 589     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 590     qemu_get_8s(f, &s->special_fully_nested_mode);
 591     qemu_get_8s(f, &s->init4);
 592     qemu_get_8s(f, &s->single_mode);
 593     qemu_get_8s(f, &s->elcr);
 594
 595 #ifdef USE_KVM
 596     if (kvm_allowed && kvm_irqchip_in_kernel(kvm_context)) {
 597         kvm_kernel_pic_load_from_user(s);
 598     }
 599 #endif
 600
 601     return 0;
 602 }
 603
 604 /* XXX: add generic master/slave system */
 605 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 606 {
 607     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 608     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 609     if (elcr_addr >= 0) {
 610         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 611         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 612     }
 613     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 614     qemu_register_reset(pic_reset, s);
 615 }
 616
 617 void pic_info(void)
 618 {
 619     int i;
 620     PicState *s;
 621
 622     if (!isa_pic)
 623         return;
 624
 625     for(i=0;i<2;i++) {
 626         s = &isa_pic->pics[i];
 627         term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 628                     i, s->irr, s->imr, s->isr, s->priority_add,
 629                     s->irq_base, s->read_reg_select, s->elcr,
 630                     s->special_fully_nested_mode);
 631     }
 632 }
 633
 634 void irq_info(void)
 635 {
 636 #ifndef DEBUG_IRQ_COUNT
 637     term_printf("irq statistic code not compiled.\n");
 638 #else
 639     int i;
 640     int64_t count;
 641
 642     term_printf("IRQ statistics:\n");
 643     for (i = 0; i < 16; i++) {
 644         count = irq_count[i];
 645         if (count > 0)
 646             term_printf("%2d: %" PRId64 "\n", i, count);
 647     }
 648 #endif
 649 }
 650
 651 qemu_irq *i8259_init(qemu_irq parent_irq)
 652 {
 653     PicState2 *s;
 654
 655     s = qemu_mallocz(sizeof(PicState2));
 656     if (!s)
 657         return NULL;
 658     pic_init1(0x20, 0x4d0, &s->pics[0]);
 659     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 660     s->pics[0].elcr_mask = 0xf8;
 661     s->pics[1].elcr_mask = 0xde;
 662     s->parent_irq = parent_irq;
 663     s->pics[0].pics_state = s;
 664     s->pics[1].pics_state = s;
 665     isa_pic = s;
 666     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 667 }
 668
 669 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
 670                           void *alt_irq_opaque)
 671 {
 672     s->alt_irq_func = alt_irq_func;
 673     s->alt_irq_opaque = alt_irq_opaque;
 674 }