qemu/hw/pl031.c

   1 /*
   2  * ARM AMBA PrimeCell PL031 RTC
   3  *
   4  * Copyright (c) 2007 CodeSourcery
   5  *
   6  * This file is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  */
  11
  12 #include "hw.h"
  13 #include "primecell.h"
  14 #include "qemu-timer.h"
  15 #include "sysemu.h"
  16
  17 //#define DEBUG_PL031
  18
  19 #ifdef DEBUG_PL031
  20 #define DPRINTF(fmt, args...) \
  21 do { printf("pl031: " fmt , ##args); } while (0)
  22 #else
  23 #define DPRINTF(fmt, args...) do {} while(0)
  24 #endif
  25
  26 #define RTC_DR      0x00    /* Data read register */
  27 #define RTC_MR      0x04    /* Match register */
  28 #define RTC_LR      0x08    /* Data load register */
  29 #define RTC_CR      0x0c    /* Control register */
  30 #define RTC_IMSC    0x10    /* Interrupt mask and set register */
  31 #define RTC_RIS     0x14    /* Raw interrupt status register */
  32 #define RTC_MIS     0x18    /* Masked interrupt status register */
  33 #define RTC_ICR     0x1c    /* Interrupt clear register */
  34
  35 typedef struct {
  36     QEMUTimer *timer;
  37     qemu_irq irq;
  38     uint32_t base;
  39
  40     uint64_t start_time;
  41     uint32_t tick_offset;
  42
  43     uint32_t mr;
  44     uint32_t lr;
  45     uint32_t cr;
  46     uint32_t im;
  47     uint32_t is;
  48 } pl031_state;
  49
  50 static const unsigned char pl031_id[] = {
  51     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
  52     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
  53 };
  54
  55 static void pl031_update(pl031_state *s)
  56 {
  57     qemu_set_irq(s->irq, s->is & s->im);
  58 }
  59
  60 static void pl031_interrupt(void * opaque)
  61 {
  62     pl031_state *s = (pl031_state *)opaque;
  63
  64     s->im = 1;
  65     DPRINTF("Alarm raised\n");
  66     pl031_update(s);
  67 }
  68
  69 static uint32_t pl031_get_count(pl031_state *s)
  70 {
  71     /* This assumes qemu_get_clock returns the time since the machine was
  72        created.  */
  73     return s->tick_offset + qemu_get_clock(vm_clock) / ticks_per_sec;
  74 }
  75
  76 static void pl031_set_alarm(pl031_state *s)
  77 {
  78     int64_t now;
  79     uint32_t ticks;
  80
  81     now = qemu_get_clock(vm_clock);
  82     ticks = s->tick_offset + now / ticks_per_sec;
  83
  84     /* The timer wraps around.  This subtraction also wraps in the same way,
  85        and gives correct results when alarm < now_ticks.  */
  86     ticks = s->mr - ticks;
  87     DPRINTF("Alarm set in %ud ticks\n", ticks);
  88     if (ticks == 0) {
  89         qemu_del_timer(s->timer);
  90         pl031_interrupt(s);
  91     } else {
  92         qemu_mod_timer(s->timer, now + (int64_t)ticks * ticks_per_sec);
  93     }
  94 }
  95
  96 static uint32_t pl031_read(void *opaque, target_phys_addr_t offset)
  97 {
  98     pl031_state *s = (pl031_state *)opaque;
  99
 100     offset -= s->base;
 101
 102     if (offset >= 0xfe0  &&  offset < 0x1000)
 103         return pl031_id[(offset - 0xfe0) >> 2];
 104
 105     switch (offset) {
 106     case RTC_DR:
 107         return pl031_get_count(s);
 108     case RTC_MR:
 109         return s->mr;
 110     case RTC_IMSC:
 111         return s->im;
 112     case RTC_RIS:
 113         return s->is;
 114     case RTC_LR:
 115         return s->lr;
 116     case RTC_CR:
 117         /* RTC is permanently enabled.  */
 118         return 1;
 119     case RTC_MIS:
 120         return s->is & s->im;
 121     case RTC_ICR:
 122         fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
 123                 (int)offset);
 124         break;
 125     default:
 126         cpu_abort(cpu_single_env, "pl031_read: Bad offset 0x%x\n",
 127                   (int)offset);
 128         break;
 129     }
 130
 131     return 0;
 132 }
 133
 134 static void pl031_write(void * opaque, target_phys_addr_t offset,
 135                         uint32_t value)
 136 {
 137     pl031_state *s = (pl031_state *)opaque;
 138
 139     offset -= s->base;
 140
 141     switch (offset) {
 142     case RTC_LR:
 143         s->tick_offset += value - pl031_get_count(s);
 144         pl031_set_alarm(s);
 145         break;
 146     case RTC_MR:
 147         s->mr = value;
 148         pl031_set_alarm(s);
 149         break;
 150     case RTC_IMSC:
 151         s->im = value & 1;
 152         DPRINTF("Interrupt mask %d\n", s->im);
 153         pl031_update(s);
 154         break;
 155     case RTC_ICR:
 156         /* The PL031 documentation (DDI0224B) states that the interupt is
 157            cleared when bit 0 of the written value is set.  However the
 158            arm926e documentation (DDI0287B) states that the interrupt is
 159            cleared when any value is written.  */
 160         DPRINTF("Interrupt cleared");
 161         s->is = 0;
 162         pl031_update(s);
 163         break;
 164     case RTC_CR:
 165         /* Written value is ignored.  */
 166         break;
 167
 168     case RTC_DR:
 169     case RTC_MIS:
 170     case RTC_RIS:
 171         fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n",
 172                 (int)offset);
 173         break;
 174
 175     default:
 176         cpu_abort(cpu_single_env, "pl031_write: Bad offset 0x%x\n",
 177                   (int)offset);
 178         break;
 179     }
 180 }
 181
 182 static CPUWriteMemoryFunc * pl031_writefn[] = {
 183     pl031_write,
 184     pl031_write,
 185     pl031_write
 186 };
 187
 188 static CPUReadMemoryFunc * pl031_readfn[] = {
 189     pl031_read,
 190     pl031_read,
 191     pl031_read
 192 };
 193
 194 void pl031_init(uint32_t base, qemu_irq irq)
 195 {
 196     int iomemtype;
 197     pl031_state *s;
 198     struct tm tm;
 199
 200     s = qemu_mallocz(sizeof(pl031_state));
 201     if (!s)
 202         cpu_abort(cpu_single_env, "pl031_init: Out of memory\n");
 203
 204     iomemtype = cpu_register_io_memory(0, pl031_readfn, pl031_writefn, s);
 205     if (iomemtype == -1)
 206         cpu_abort(cpu_single_env, "pl031_init: Can't register I/O memory\n");
 207
 208     cpu_register_physical_memory(base, 0x00001000, iomemtype);
 209
 210     s->base = base;
 211     s->irq  = irq;
 212     /* ??? We assume vm_clock is zero at this point.  */
 213     qemu_get_timedate(&tm, 0);
 214     s->tick_offset = mktime(&tm);
 215
 216     s->timer = qemu_new_timer(vm_clock, pl031_interrupt, s);
 217 }