fpga/sim.tcl

   1 #------------------------------------------------------------------------------
   2 # Run the simulation testbench in ModelSim: recompile both Verilog source
   3 # files, then start the simulation, add a lot of signals to the waveform
   4 # viewer, and run. I should (TODO) fix the absolute paths at some point.
   5 #
   6 # Jonathan Westhues, Mar 2006
   7 #------------------------------------------------------------------------------
   8
   9 vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga.v
  10 vlog -work work -O0 C:/depot/proximity/mark3/fpga/fpga_tb.v
  11
  12 vsim work.fpga_tb
  13
  14 add wave sim:/fpga_tb/adc_clk
  15 add wave sim:/fpga_tb/adc_d
  16 add wave sim:/fpga_tb/pwr_lo
  17 add wave sim:/fpga_tb/ssp_clk
  18 add wave sim:/fpga_tb/ssp_frame
  19 add wave sim:/fpga_tb/ssp_din
  20 add wave sim:/fpga_tb/ssp_dout
  21
  22 add wave sim:/fpga_tb/dut/clk_lo
  23 add wave sim:/fpga_tb/dut/pck_divider
  24 add wave sim:/fpga_tb/dut/carrier_divider_lo
  25 add wave sim:/fpga_tb/dut/conf_word
  26
  27 run 30000