fpga/hi_iso14443a.v

   1 //-----------------------------------------------------------------------------
   2 // ISO14443-A support for the Proxmark III
   3 // Gerhard de Koning Gans, April 2008
   4 //-----------------------------------------------------------------------------
   5
   6 module hi_iso14443a(
   7     ck_1356meg,
   8     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
   9     adc_d, adc_clk,
  10     ssp_frame, ssp_din, ssp_dout, ssp_clk,
  11     dbg,
  12     mod_type
  13 );
  14     input ck_1356meg;
  15     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
  16     input [7:0] adc_d;
  17     output adc_clk;
  18     input ssp_dout;
  19     output ssp_frame, ssp_din, ssp_clk;
  20     output dbg;
  21     input [3:0] mod_type;
  22
  23
  24 wire adc_clk = ck_1356meg;
  25
  26
  27
  28 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  29 // Reader -> PM3:
  30 // detecting and shaping the reader's signal. Reader will modulate the carrier by 100% (signal is either on or off). Use a
  31 // hysteresis (Schmitt Trigger) to avoid false triggers during slowly increasing or decreasing carrier amplitudes
  32 reg after_hysteresis;
  33 reg [11:0] has_been_low_for;
  34
  35 always @(negedge adc_clk)
  36 begin
  37         if(adc_d >= 16) after_hysteresis <= 1'b1;                       // U >= 1,14V   -> after_hysteresis = 1
  38     else if(adc_d < 8) after_hysteresis <= 1'b0;                // U <  1,04V   -> after_hysteresis = 0
  39         // Note: was >= 3,53V and <= 1,19V. The new trigger values allow more reliable detection of the first bit
  40         // (it might not reach 3,53V due to the high time constant of the high pass filter in the analogue RF part).
  41         // In addition, the new values are more in line with ISO14443-2: "The PICC shall detect the ”End of Pause” after the field exceeds
  42         // 5% of H_INITIAL and before it exceeds 60% of H_INITIAL." Depending on the signal strength, 60% might well be less than 3,53V.
  43
  44
  45         // detecting a loss of reader's field (adc_d < 192 for 4096 clock cycles). If this is the case,
  46         // set the detected reader signal (after_hysteresis) to '1' (unmodulated)
  47         if(adc_d >= 192)
  48     begin
  49         has_been_low_for <= 12'd0;
  50     end
  51     else
  52     begin
  53         if(has_been_low_for == 12'd4095)
  54         begin
  55             has_been_low_for <= 12'd0;
  56             after_hysteresis <= 1'b1;
  57         end
  58         else
  59                 begin
  60             has_been_low_for <= has_been_low_for + 1;
  61                 end
  62     end
  63
  64 end
  65
  66
  67
  68 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  69 // Reader -> PM3
  70 // detect when a reader is active (modulating). We assume that the reader is active, if we see the carrier off for at least 8
  71 // carrier cycles. We assume that the reader is inactive, if the carrier stayed high for at least 256 carrier cycles.
  72 reg deep_modulation;
  73 reg [2:0] deep_counter;
  74 reg [8:0] saw_deep_modulation;
  75
  76 always @(negedge adc_clk)
  77 begin
  78         if(~(| adc_d[7:0]))                                                                     // if adc_d == 0 (U <= 0,94V)
  79         begin
  80                 if(deep_counter == 3'd7)                                                // adc_d == 0 for 8 adc_clk ticks -> deep_modulation (by reader)
  81                 begin
  82                         deep_modulation <= 1'b1;
  83                         saw_deep_modulation <= 8'd0;
  84                 end
  85                 else
  86                         deep_counter <= deep_counter + 1;
  87         end
  88         else
  89         begin
  90                 deep_counter <= 3'd0;
  91                 if(saw_deep_modulation == 8'd255)                               // adc_d != 0 for 256 adc_clk ticks -> deep_modulation is over, probably waiting for tag's response
  92                         deep_modulation <= 1'b0;
  93                 else
  94                         saw_deep_modulation <= saw_deep_modulation + 1;
  95         end
  96 end
  97
  98
  99
 100 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 101 // Tag -> PM3
 102 // filter the input for a tag's signal. The filter box needs the 4 previous input values and is a gaussian derivative filter
 103 // for noise reduction and edge detection.
 104 // store 4 previous samples:
 105 reg [7:0] input_prev_4, input_prev_3, input_prev_2, input_prev_1;
 106
 107 always @(negedge adc_clk)
 108 begin
 109         input_prev_4 <= input_prev_3;
 110         input_prev_3 <= input_prev_2;
 111         input_prev_2 <= input_prev_1;
 112         input_prev_1 <= adc_d;
 113 end
 114
 115 // adc_d_filtered = 2*input_prev4 + 1*input_prev3 + 0*input_prev2 - 1*input_prev1 - 2*input
 116 //                                      = (2*input_prev4 + input_prev3) - (2*input + input_prev1)
 117 wire [8:0] input_prev_4_times_2 = input_prev_4 << 1;
 118 wire [8:0] adc_d_times_2                = adc_d << 1;
 119
 120 wire [9:0] tmp1 = input_prev_4_times_2 + input_prev_3;
 121 wire [9:0] tmp2 = adc_d_times_2 + input_prev_1;
 122
 123 // convert intermediate signals to signed and calculate the filter output
 124 wire signed [10:0] adc_d_filtered = {1'b0, tmp1} - {1'b0, tmp2};
 125
 126
 127
 128 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 129 // internal FPGA timing. Maximum required period is 128 carrier clock cycles for a full 8 Bit transfer to ARM. (i.e. we need a
 130 // 7 bit counter). Adjust its frequency to external reader's clock when simulating a tag or sniffing.
 131 reg pre_after_hysteresis;
 132 reg [3:0] reader_falling_edge_time;
 133 reg [6:0] negedge_cnt;
 134
 135 always @(negedge adc_clk)
 136 begin
 137         // detect a reader signal's falling edge and remember its timing:
 138         pre_after_hysteresis <= after_hysteresis;
 139         if (pre_after_hysteresis && ~after_hysteresis)
 140         begin
 141                 reader_falling_edge_time[3:0] <= negedge_cnt[3:0];
 142         end
 143
 144         // adjust internal timer counter if necessary:
 145         if (negedge_cnt[3:0] == 4'd13 && (mod_type == `FPGA_HF_ISO14443A_SNIFFER || mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN) && deep_modulation)
 146         begin
 147                 if (reader_falling_edge_time == 4'd1)                   // reader signal changes right after sampling. Better sample earlier next time.
 148                 begin
 149                         negedge_cnt <= negedge_cnt + 2;                         // time warp
 150                 end
 151                 else if (reader_falling_edge_time == 4'd0)              // reader signal changes right before sampling. Better sample later next time.
 152                 begin
 153                         negedge_cnt <= negedge_cnt;                                     // freeze time
 154                 end
 155                 else
 156                 begin
 157                         negedge_cnt <= negedge_cnt + 1;                         // Continue as usual
 158                 end
 159                 reader_falling_edge_time[3:0] <= 4'd8;                  // adjust only once per detected edge
 160         end
 161         else if (negedge_cnt == 7'd127)                                         // normal operation: count from 0 to 127
 162         begin
 163                 negedge_cnt <= 0;
 164         end
 165         else
 166         begin
 167                 negedge_cnt <= negedge_cnt + 1;
 168         end
 169 end
 170
 171
 172 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 173 // Tag -> PM3:
 174 // determine best possible time for starting/resetting the modulation detector.
 175 reg [3:0] mod_detect_reset_time;
 176
 177 always @(negedge adc_clk)
 178 begin
 179         if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)
 180         // (our) reader signal changes at negedge_cnt[3:0]=9, tag response expected to start n*16+4 ticks later, further delayed by
 181         // 3 ticks ADC conversion. The maximum filter output (edge detected) will be detected after subcarrier zero crossing (+7 ticks).
 182         // To allow some timing variances, we want to have the maximum filter outputs well within the detection window, i.e.
 183         // at mod_detect_reset_time+4 and mod_detect_reset_time+12  (-4 ticks).
 184         // 9 + 4 + 3 + 7 - 4  = 19.    19 mod 16 = 3
 185         begin
 186                 mod_detect_reset_time <= 4'd4;
 187         end
 188         else
 189         if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
 190         begin
 191                 // detect a rising edge of reader's signal and sync modulation detector to the tag's answer:
 192                 if (~pre_after_hysteresis && after_hysteresis && deep_modulation)
 193                 // reader signal rising edge detected at negedge_cnt[3:0]. This signal had been delayed
 194                 // 9 ticks by the RF part + 3 ticks by the A/D converter + 1 tick to assign to after_hysteresis.
 195                 // Then the same as above.
 196                 // - 9 - 3 - 1 + 4 + 3 + 7 - 4 = -3
 197                 begin
 198                         mod_detect_reset_time <= negedge_cnt[3:0] - 4'd3;
 199                 end
 200         end
 201 end
 202
 203
 204 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 205 // Tag -> PM3:
 206 // modulation detector. Looks for the steepest falling and rising edges within a 16 clock period. If there is both a significant
 207 // falling and rising edge (in any order), a modulation is detected.
 208 reg signed [10:0] rx_mod_falling_edge_max;
 209 reg signed [10:0] rx_mod_rising_edge_max;
 210 reg curbit;
 211
 212 `define EDGE_DETECT_THRESHOLD   5
 213
 214 always @(negedge adc_clk)
 215 begin
 216         if(negedge_cnt[3:0] == mod_detect_reset_time)
 217         begin
 218                 // detect modulation signal: if modulating, there must have been a falling AND a rising edge
 219                 if ((rx_mod_falling_edge_max > `EDGE_DETECT_THRESHOLD) && (rx_mod_rising_edge_max < -`EDGE_DETECT_THRESHOLD))
 220                                 curbit <= 1'b1; // modulation
 221                         else
 222                                 curbit <= 1'b0; // no modulation
 223                 // reset modulation detector
 224                 rx_mod_rising_edge_max <= 0;
 225                 rx_mod_falling_edge_max <= 0;
 226         end
 227         else                                                                                    // look for steepest edges (slopes)
 228         begin
 229                 if (adc_d_filtered > 0)
 230                 begin
 231                         if (adc_d_filtered > rx_mod_falling_edge_max)
 232                                 rx_mod_falling_edge_max <= adc_d_filtered;
 233                 end
 234                 else
 235                 begin
 236                         if (adc_d_filtered < rx_mod_rising_edge_max)
 237                                 rx_mod_rising_edge_max <= adc_d_filtered;
 238                 end
 239         end
 240
 241 end
 242
 243
 244
 245 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 246 // Tag+Reader -> PM3
 247 // sample 4 bits reader data and 4 bits tag data for sniffing
 248 reg [3:0] reader_data;
 249 reg [3:0] tag_data;
 250
 251 always @(negedge adc_clk)
 252 begin
 253     if(negedge_cnt[3:0] == 4'd0)
 254         begin
 255         reader_data[3:0] <= {reader_data[2:0], after_hysteresis};
 256                 tag_data[3:0] <= {tag_data[2:0], curbit};
 257         end
 258 end
 259
 260
 261
 262 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 263 // PM3 -> Reader:
 264 // a delay line to ensure that we send the (emulated) tag's answer at the correct time according to ISO14443-3
 265 reg [31:0] mod_sig_buf;
 266 reg [4:0] mod_sig_ptr;
 267 reg mod_sig;
 268
 269 always @(negedge adc_clk)
 270 begin
 271         if(negedge_cnt[3:0] == 4'd0)    // sample data at rising edge of ssp_clk - ssp_dout changes at the falling edge.
 272         begin
 273                 mod_sig_buf[31:2] <= mod_sig_buf[30:1];                         // shift
 274                 if (~ssp_dout && ~mod_sig_buf[1])
 275                         mod_sig_buf[1] <= 1'b0;                                                 // delete the correction bit (a single 1 preceded and succeeded by 0)
 276                 else
 277                         mod_sig_buf[1] <= mod_sig_buf[0];
 278                 mod_sig_buf[0] <= ssp_dout;                                                     // add new data to the delay line
 279
 280                 mod_sig = mod_sig_buf[mod_sig_ptr];                                     // the delayed signal.
 281         end
 282 end
 283
 284
 285
 286 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 287 // PM3 -> Reader, internal timing:
 288 // a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader's signal.
 289 // set fdt_elapsed when we no longer need to delay data. Set fdt_indicator when we can start sending data.
 290 // Note: the FPGA only takes care for the 1172 delay. To achieve an additional 1236-1172=64 ticks delay, the ARM must send
 291 // a correction bit (before the start bit). The correction bit will be coded as 00010000, i.e. it adds 4 bits to the
 292 // transmission stream, causing the required additional delay.
 293 reg [10:0] fdt_counter;
 294 reg fdt_indicator, fdt_elapsed;
 295 reg [3:0] mod_sig_flip;
 296 reg [3:0] sub_carrier_cnt;
 297
 298 // we want to achieve a delay of 1172. The RF part already has delayed the reader signals's rising edge
 299 // by 9 ticks, the ADC took 3 ticks and there is always a delay of 32 ticks by the mod_sig_buf. Therefore need to
 300 // count to 1172 - 9 - 3 - 32 = 1128
 301 `define FDT_COUNT 11'd1128
 302
 303 // The ARM must not send too early, otherwise the mod_sig_buf will overflow, therefore signal that we are ready
 304 // with fdt_indicator. The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks.
 305 // fdt_indicator is assigned to sendbit after at least 1 tick, the transfer to ARM needs minimum 8 ticks. Response from
 306 // ARM could appear at ssp_dout 8 ticks later.
 307 // 1128 - 464 - 1 - 8 - 8 = 647
 308 `define FDT_INDICATOR_COUNT 11'd647
 309 // Note: worst case, assignment to sendbit takes 15 ticks more, and transfer to ARM needs 7*16 = 112 ticks more.
 310 //       When the ARM's response then appears, the fdt_count is already 647 + 15 + 112 = 774, which still allows the ARM a possible
 311 //       response window of 1128 - 774 = 354 ticks.
 312
 313 // reset on a pause in listen mode. I.e. the counter starts when the pause is over:
 314 assign fdt_reset = ~after_hysteresis && mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN;
 315
 316 always @(negedge adc_clk)
 317 begin
 318         if (fdt_reset)
 319         begin
 320                 fdt_counter <= 11'd0;
 321                 fdt_elapsed <= 1'b0;
 322                 fdt_indicator <= 1'b0;
 323         end
 324         else
 325         begin
 326                 if(fdt_counter == `FDT_COUNT)
 327                 begin
 328                         if(~fdt_elapsed)                                                        // just reached fdt.
 329                         begin
 330                                 mod_sig_flip <= negedge_cnt[3:0];               // start modulation at this time
 331                                 sub_carrier_cnt <= 4'd0;                                // subcarrier phase in sync with start of modulation
 332                                 fdt_elapsed <= 1'b1;
 333                         end
 334                         else
 335                         begin
 336                                 sub_carrier_cnt <= sub_carrier_cnt + 1;
 337                         end
 338                 end
 339                 else
 340                 begin
 341                         fdt_counter <= fdt_counter + 1;
 342                 end
 343         end
 344
 345         if(fdt_counter == `FDT_INDICATOR_COUNT) fdt_indicator <= 1'b1;
 346 end
 347
 348
 349 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 350 // PM3 -> Reader or Tag
 351 // assign a modulation signal to the antenna. This signal is either a delayed signal (to achieve fdt when sending to a reader)
 352 // or undelayed when sending to a tag
 353 reg mod_sig_coil;
 354
 355 always @(negedge adc_clk)
 356 begin
 357         if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD)                   // need to take care of proper fdt timing
 358         begin
 359                 if(fdt_counter == `FDT_COUNT)
 360                 begin
 361                         if(fdt_elapsed)
 362                         begin
 363                                 if(negedge_cnt[3:0] == mod_sig_flip) mod_sig_coil <= mod_sig;
 364                         end
 365                         else
 366                         begin
 367                                 mod_sig_coil <= mod_sig;        // just reached fdt. Immediately assign signal to coil
 368                         end
 369                 end
 370         end
 371         else                                                                    // other modes: don't delay
 372         begin
 373                 mod_sig_coil <= ssp_dout;
 374         end
 375 end
 376
 377
 378
 379 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 380 // PM3 -> Reader
 381 // determine the required delay in the mod_sig_buf (set mod_sig_ptr).
 382 reg temp_buffer_reset;
 383
 384 always @(negedge adc_clk)
 385 begin
 386         if(fdt_reset)
 387         begin
 388                 mod_sig_ptr <= 5'd0;
 389                 temp_buffer_reset = 1'b0;
 390         end
 391         else
 392         begin
 393                 if(fdt_counter == `FDT_COUNT && ~fdt_elapsed)                                                   // if we just reached fdt
 394                         if(~(| mod_sig_ptr[4:0]))
 395                                 mod_sig_ptr <= 5'd8;                                                                                    // ... but didn't buffer a 1 yet, delay next 1 by n*128 ticks.
 396                         else
 397                                 temp_buffer_reset = 1'b1;                                                                               // else no need for further delays.
 398
 399                 if(negedge_cnt[3:0] == 4'd0)                                                                                    // at rising edge of ssp_clk - ssp_dout changes at the falling edge.
 400                 begin
 401                         if((ssp_dout || (| mod_sig_ptr[4:0])) && ~fdt_elapsed)                          // buffer a 1 (and all subsequent data) until fdt is reached.
 402                                 if (mod_sig_ptr == 5'd31)
 403                                         mod_sig_ptr <= 5'd0;                                                                            // buffer overflow - data loss.
 404                                 else
 405                                         mod_sig_ptr <= mod_sig_ptr + 1;                                                         // increase buffer (= increase delay by 16 adc_clk ticks). mod_sig_ptr always points ahead of first 1.
 406                         else if(fdt_elapsed && ~temp_buffer_reset)
 407                         begin
 408                                 // wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
 409                                 // at intervals of 8 * 16 = 128 adc_clk ticks (as defined in ISO14443-3)
 410                                 if(ssp_dout)
 411                                         temp_buffer_reset = 1'b1;
 412                                 if(mod_sig_ptr == 5'd1)
 413                                         mod_sig_ptr <= 5'd8;                                                                            // still nothing received, need to go for the next interval
 414                                 else
 415                                         mod_sig_ptr <= mod_sig_ptr - 1;                                                         // decrease buffer.
 416                         end
 417                 end
 418         end
 419 end
 420
 421
 422
 423 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 424 // FPGA -> ARM communication:
 425 // buffer 8 bits data to be sent to ARM. Shift them out bit by bit.
 426 reg [7:0] to_arm;
 427
 428 always @(negedge adc_clk)
 429 begin
 430         if (negedge_cnt[5:0] == 6'd63)                                                  // fill the buffer
 431         begin
 432                 if (mod_type == `FPGA_HF_ISO14443A_SNIFFER)
 433                 begin
 434                         if(deep_modulation)                                                     // a reader is sending (or there's no field at all)
 435                         begin
 436                                 to_arm <= {reader_data[3:0], 4'b0000};          // don't send tag data
 437                         end
 438                         else
 439                         begin
 440                                 to_arm <= {reader_data[3:0], tag_data[3:0]};
 441                         end
 442                 end
 443                 else
 444                 begin
 445                         to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]}; // feedback timing information
 446                 end
 447         end
 448
 449         if(negedge_cnt[2:0] == 3'b000 && mod_type == `FPGA_HF_ISO14443A_SNIFFER)        // shift at double speed
 450         begin
 451                 // Don't shift if we just loaded new data, obviously.
 452                 if(negedge_cnt[5:0] != 6'd0)
 453                 begin
 454                         to_arm[7:1] <= to_arm[6:0];
 455                 end
 456         end
 457
 458         if(negedge_cnt[3:0] == 4'b0000 && mod_type != `FPGA_HF_ISO14443A_SNIFFER)
 459         begin
 460                 // Don't shift if we just loaded new data, obviously.
 461                 if(negedge_cnt[6:0] != 7'd0)
 462                 begin
 463                         to_arm[7:1] <= to_arm[6:0];
 464                 end
 465         end
 466
 467 end
 468
 469
 470 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 471 // FPGA <-> ARM communication:
 472 // generate a ssp clock and ssp frame signal for the synchronous transfer from/to the ARM
 473 reg ssp_clk;
 474 reg ssp_frame;
 475
 476 always @(negedge adc_clk)
 477 begin
 478         if(mod_type == `FPGA_HF_ISO14443A_SNIFFER)
 479         // FPGA_HF_ISO14443A_SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
 480         begin
 481                 if(negedge_cnt[2:0] == 3'd0)
 482                         ssp_clk <= 1'b1;
 483                 if(negedge_cnt[2:0] == 3'd4)
 484                         ssp_clk <= 1'b0;
 485
 486                 if(negedge_cnt[5:0] == 6'd0)    // ssp_frame rising edge indicates start of frame
 487                         ssp_frame <= 1'b1;
 488                 if(negedge_cnt[5:0] == 6'd8)
 489                         ssp_frame <= 1'b0;
 490         end
 491         else
 492         // all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
 493         begin
 494                 if(negedge_cnt[3:0] == 4'd0)
 495                         ssp_clk <= 1'b1;
 496                 if(negedge_cnt[3:0] == 4'd8)
 497                         ssp_clk <= 1'b0;
 498
 499                 if(negedge_cnt[6:0] == 7'd7)    // ssp_frame rising edge indicates start of frame, sampled on falling edge of ssp_clk
 500                         ssp_frame <= 1'b1;
 501                 if(negedge_cnt[6:0] == 7'd23)
 502                         ssp_frame <= 1'b0;
 503         end
 504 end
 505
 506
 507
 508 ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
 509 // FPGA -> ARM communication:
 510 // select the data to be sent to ARM
 511 reg bit_to_arm;
 512 reg sendbit;
 513
 514 always @(negedge adc_clk)
 515 begin
 516         if(negedge_cnt[3:0] == 4'd0)
 517         begin
 518                 // What do we communicate to the ARM
 519                 if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_LISTEN)
 520                         sendbit = after_hysteresis;
 521                 else if(mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD)
 522                         /* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
 523                         else */
 524                         sendbit = fdt_indicator;
 525                 else if (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)
 526                         sendbit = curbit;
 527                 else
 528                         sendbit = 1'b0;
 529         end
 530
 531
 532         if(mod_type == `FPGA_HF_ISO14443A_SNIFFER)
 533                 // send sampled reader and tag data:
 534                 bit_to_arm = to_arm[7];
 535         else if (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
 536                 // send timing information:
 537                 bit_to_arm = to_arm[7];
 538         else
 539                 // send data or fdt_indicator
 540                 bit_to_arm = sendbit;
 541 end
 542
 543
 544
 545
 546 assign ssp_din = bit_to_arm;
 547
 548 // Subcarrier (adc_clk/16, for FPGA_HF_ISO14443A_TAGSIM_MOD only).
 549 wire sub_carrier;
 550 assign sub_carrier = ~sub_carrier_cnt[3];
 551
 552 // in FPGA_HF_ISO14443A_READER_MOD: drop carrier for mod_sig_coil==1 (pause); in FPGA_HF_ISO14443A_READER_LISTEN: carrier always on; in other modes: carrier always off
 553 assign pwr_hi = (ck_1356meg & (((mod_type == `FPGA_HF_ISO14443A_READER_MOD) & ~mod_sig_coil) || (mod_type == `FPGA_HF_ISO14443A_READER_LISTEN)));
 554
 555
 556 // Enable HF antenna drivers:
 557 assign pwr_oe1 = 1'b0;
 558 assign pwr_oe3 = 1'b0;
 559
 560 // FPGA_HF_ISO14443A_TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
 561 // for pwr_oe4 = 1 (tristate): antenna load = 10k || 33                 = 32,9 Ohms
 562 // for pwr_oe4 = 0 (active):   antenna load = 10k || 33 || 33   = 16,5 Ohms
 563 assign pwr_oe4 = mod_sig_coil & sub_carrier & (mod_type == `FPGA_HF_ISO14443A_TAGSIM_MOD);
 564
 565 // This is all LF, so doesn't matter.
 566 assign pwr_oe2 = 1'b0;
 567 assign pwr_lo = 1'b0;
 568
 569
 570 assign dbg = negedge_cnt[3];
 571
 572 endmodule