fpga/hi_sniffer.v

   1 module hi_sniffer(
   2     ck_1356meg,
   3     pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
   4     adc_d, adc_clk,
   5     ssp_frame, ssp_din, ssp_clk
   6 );
   7     input ck_1356meg;
   8     output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
   9     input [7:0] adc_d;
  10     output adc_clk;
  11     output ssp_frame, ssp_din, ssp_clk;
  12
  13 // We are only snooping, all off.
  14 assign pwr_hi  = 1'b0;
  15 assign pwr_lo  = 1'b0;
  16 assign pwr_oe1 = 1'b0;
  17 assign pwr_oe2 = 1'b0;
  18 assign pwr_oe3 = 1'b0;
  19 assign pwr_oe4 = 1'b0;
  20
  21 reg ssp_frame;
  22 reg [7:0] adc_d_out = 8'd0;
  23 reg [2:0] ssp_cnt = 3'd0;
  24
  25 assign adc_clk = ck_1356meg;
  26 assign ssp_clk = ~ck_1356meg;
  27
  28 always @(posedge ssp_clk)
  29 begin
  30     if(ssp_cnt[2:0] == 3'd7)
  31         ssp_cnt[2:0] <= 3'd0;
  32     else
  33         ssp_cnt <= ssp_cnt + 1;
  34
  35     if(ssp_cnt[2:0] == 3'b000) // set frame length
  36         begin
  37             adc_d_out[7:0] <= adc_d;
  38             ssp_frame <= 1'b1;
  39         end
  40     else
  41         begin
  42             adc_d_out[7:0] <= {1'b0, adc_d_out[7:1]};
  43             ssp_frame <= 1'b0;
  44         end
  45
  46 end
  47
  48 assign ssp_din = adc_d_out[0];
  49
  50 endmodule