gc/ogc/cache.h

   1 /*-------------------------------------------------------------
   2
   3
   4 cache.h -- Cache interface
   5
   6 Copyright (C) 2004
   7 Michael Wiedenbauer (shagkur)
   8 Dave Murphy (WinterMute)
   9
  10 This software is provided 'as-is', without any express or implied
  11 warranty.  In no event will the authors be held liable for any
  12 damages arising from the use of this software.
  13
  14 Permission is granted to anyone to use this software for any
  15 purpose, including commercial applications, and to alter it and
  16 redistribute it freely, subject to the following restrictions:
  17
  18 1.      The origin of this software must not be misrepresented; you
  19 must not claim that you wrote the original software. If you use
  20 this software in a product, an acknowledgment in the product
  21 documentation would be appreciated but is not required.
  22
  23 2.      Altered source versions must be plainly marked as such, and
  24 must not be misrepresented as being the original software.
  25
  26 3.      This notice may not be removed or altered from any source
  27 distribution.
  28
  29
  30 -------------------------------------------------------------*/
  31
  32
  33 #ifndef __CACHE_H__
  34 #define __CACHE_H__
  35
  36 /*! \file cache.h
  37 \brief Cache subsystem
  38
  39 */
  40
  41 #include <gctypes.h>
  42
  43 #define LC_BASEPREFIX           0xe000
  44 #define LC_BASE                         (LC_BASEPREFIX<<16)
  45
  46 #ifdef __cplusplus
  47    extern "C" {
  48 #endif /* __cplusplus */
  49
  50
  51 /*!
  52  * \fn void DCEnable()
  53  * \brief Enable L1 d-cache
  54  *
  55  * \return none
  56  */
  57 void DCEnable();
  58
  59
  60 /*!
  61  * \fn void DCDisable()
  62  * \brief Disable L1 d-cache
  63  *
  64  * \return none
  65  */
  66 void DCDisable();
  67
  68
  69 /*!
  70  * \fn void DCFreeze()
  71  * \brief Current contents of the L1 d-cache are locked down and will not be cast out.
  72  *
  73  *        Hits are still serviced, but misses go straight to L2 or 60x bus.  Most cache operations, such as DCFlushRange(), will still execute regardless of whether the cache is frozen.<br>
  74  *            <b><i>NOTE:</i></b> In PowerPC architecture jargon, this feature is referred to as "locking" the data cache.  We use the word "freeze" to distinguish it from the locked cache and DMA features.
  75  *
  76  * \return none
  77  */
  78 void DCFreeze();
  79
  80
  81 /*!
  82  * \fn void DCUnfreeze()
  83  * \brief Undoes actions of DCFreeze().
  84  *
  85  *        Old cache blocks will now be cast out on subsequent L1 misses.<br>
  86  *            <b><i>NOTE:</i></b> In PowerPC architecture jargon, this feature is referred to as "locking" the data cache.  We use the word "freeze" to distinguish it from the locked cache and DMA features.
  87  *
  88  * \return none
  89  */
  90 void DCUnfreeze();
  91
  92
  93 /*!
  94  * \fn void DCFlashInvalidate()
  95  * \brief Invalidate L1 d-cache.
  96  *
  97  *        An invalidate operation is issued that marks the state of each data cache block as invalid without writing back modified cache blocks to memory.<br>
  98  *        Cache access is blocked during this time.Bus accesses to the cache are signaled as a miss during invalidate-all operations.
  99  *
 100  * \return none
 101  */
 102 void DCFlashInvalidate();
 103
 104
 105 /*!
 106  * \fn void DCInvalidateRange(void *startaddress,u32 len)
 107  * \brief Invalidates a given range of the d-cache.
 108  *
 109  *        If any part of the range hits in the d-cache, the corresponding block will be invalidated.
 110  *
 111  * \param[in] startaddress pointer to the startaddress of the memory range to invalidate. <b><i>NOTE:</i></b> Has to be aligned on a 32byte boundery
 112  * \param[in] len length of the range to invalidate. <b><i>NOTE:</i></b> Should be a multiple of 32
 113  *
 114  * \return none
 115  */
 116 void DCInvalidateRange(void *startaddress,u32 len);
 117
 118
 119 /*!
 120  * \fn void DCFlushRange(void *startaddress,u32 len)
 121  * \brief Flushes a given range.
 122  *
 123  *        If any part of the range hits in the d-cache the corresponding block will be flushed to main memory and invalidated.<br>
 124  *        <b><i>NOTE:</i></b> This function invokes a "sync" after flushing the range. This means the function will stall until the CPU knows that the data has been writen to main memory
 125  *
 126  * \param[in] startaddress pointer to the startaddress of the memory range to flush. <b><i>NOTE:</i></b> Has to be aligned on a 32byte boundery
 127  * \param[in] len length of range to be flushed. <b><i>NOTE:</i></b> Should be a multiple of 32
 128  *
 129  *\return none
 130  */
 131 void DCFlushRange(void *startaddress,u32 len);
 132
 133 /*!
 134  * \fn void DCStoreRange(void *startaddress,u32 len)
 135  * \brief Ensures a range of memory is updated with any modified data in the cache.
 136  *
 137  *        <b><i>NOTE:</i></b> This function invokes a "sync" after storing the range. This means the function will stall until the CPU knows that the data has been writen to main memory
 138  *
 139  * \param[in] startaddress pointer to the startaddress of the memory range to store. <b><i>NOTE:</i></b> Has to be aligned on a 32byte boundery
 140  * \param[in] len length of the range to store. <b><i>NOTE:</i></b> Should be a multiple of 32
 141  *
 142  * \return none
 143  */
 144 void DCStoreRange(void *startaddress,u32 len);
 145
 146
 147 /*!
 148  * \fn void DCFlushRangeNoSync(void *startaddress,u32 len)
 149  * \brief Flushes a given range.
 150  *
 151  *        If any part of the range hits in the d-cache the corresponding block will be flushed to main memory and invalidated.<br>
 152  *        <b><i>NOTE:</i></b> This routine does not perform a "sync" to ensure that the range has been flushed to memory.  That is, the cache blocks are sent to the bus interface unit for storage to main memory, but by the time this function returns, you are not guaranteed that the blocks have been written to memory.
 153  *
 154  * \param[in] startaddress pointer to the startaddress of the memory range to flush. <b><i>NOTE:</i></b> Has to be aligned on a 32byte boundery
 155  * \param[in] len length of range to be flushed. <b><i>NOTE:</i></b> Should be a multiple of 32
 156  *
 157  * \return none
 158  */
 159 void DCFlushRangeNoSync(void *startaddress,u32 len);
 160
 161
 162 /*!
 163  * \fn void DCStoreRangeNoSync(void *startaddress,u32 len)
 164  * \brief Ensures a range of memory is updated with any modified data in the cache.
 165  *
 166  *        <b><i>NOTE:</i></b> This routine does not perform a "sync" to ensure that the range has been flushed to memory.  That is, the cache blocks are sent to the bus interface unit for storage to main memory, but by the time this function returns, you are not guaranteed that the blocks have been written to memory
 167  *
 168  * \param[in] startaddress pointer to the startaddress of the memory range to store. <b><i>NOTE:</i></b> Has to be aligned on a 32byte boundery
 169  * \param[in] len length of the range to store. <b><i>NOTE:</i></b> Should be a multiple of 32
 170  *
 171  * \return none
 172  */
 173 void DCStoreRangeNoSync(void *startaddress,u32 len);
 174
 175
 176 /*!
 177  * \fn void DCZeroRange(void *startaddress,u32 len)
 178  * \brief Loads a range of memory into cache and zeroes all the cache lines.
 179  *
 180  * \param[in] startaddress pointer to the startaddress of the memory range to load/zero. <b><i>NOTE:</i></b> Has to be aligned on a 32byte boundery
 181  * \param[in] len length of the range to load/zero. <b><i>NOTE:</i></b> Should be a multiple of 32
 182  *
 183  * \return none
 184  */
 185 void DCZeroRange(void *startaddress,u32 len);
 186
 187
 188 /*!
 189  * \fn void DCTouchRange(void *startaddress,u32 len)
 190  * \brief Loads a range of memory into cache.
 191  *
 192  * \param[in] startaddress pointer to the startaddress of the memory range to load. <b><i>NOTE:</i></b> Has to be aligned on a 32byte boundery
 193  * \param[in] len length of the range to load. <b><i>NOTE:</i></b> Should be a multiple of 32
 194  *
 195  * \return none
 196  */
 197 void DCTouchRange(void *startaddress,u32 len);
 198
 199
 200 /*!
 201  * \fn void ICSync()
 202  * \brief Performs an instruction cache synchronization.
 203  *
 204  *        This ensures that all instructions preceding this instruction have completed before this instruction completes.
 205  *
 206  * \return none
 207  */
 208 void ICSync();
 209
 210
 211 /*!
 212  * \fn void ICFlashInvalidate()
 213  * \brief Invalidate the L1 i-cache.
 214  *
 215  *        An invalidate operation is issued that marks the state of each instruction cache block as invalid without writing back modified cache blocks to memory.<br>
 216  *        Cache access is blocked during this time. Bus accesses to the cache are signaled as a miss during invalidate-all operations.
 217  *
 218  * \return none
 219  */
 220 void ICFlashInvalidate();
 221
 222
 223 /*!
 224  * \fn void ICEnable()
 225  * \brief Enable L1 i-cache
 226  *
 227  * \return none
 228  */
 229 void ICEnable();
 230
 231
 232 /*!
 233  * \fn void ICDisable()
 234  * \brief Disable L1 i-cache
 235  *
 236  * \return none
 237  */
 238 void ICDisable();
 239
 240
 241 /*!
 242  * \fn void ICFreeze()
 243  * \brief Current contents of the L1 i-cache are locked down and will not be cast out.
 244  *
 245  *        Hits are still serviced, but misses go straight to L2 or 60x bus.<br>
 246  *            <b><i>NOTE:</i></b> In PowerPC architecture jargon, this feature is referred to as "locking" the data cache.  We use the word "freeze" to distinguish it from the locked cache and DMA features.
 247  *
 248  * \return none
 249  */
 250 void ICFreeze();
 251
 252
 253 /*!
 254  * \fn void ICUnfreeze()
 255  * \brief Undoes actions of ICFreeze().
 256  *
 257  *        Old cache blocks will now be cast out on subsequent L1 misses.<br>
 258  *            <b><i>NOTE:</i></b> In PowerPC architecture jargon, this feature is referred to as "locking" the data cache.  We use the word "freeze" to distinguish it from the locked cache and DMA features.
 259  *
 260  * \return none
 261  */
 262 void ICUnfreeze();
 263
 264
 265 /*!
 266  * \fn void ICBlockInvalidate(void *startaddress)
 267  * \brief Invalidates a block in the i-cache.
 268  *
 269  *        If the block hits in the i-cache, the corresponding block will be invalidated.
 270  *
 271  * \param[in] startaddress pointer to the startaddress of the memory block to invalidate. <b><i>NOTE:</i></b> Has to be aligned on a 32byte boundery
 272  *
 273  *\return none
 274  */
 275 void ICBlockInvalidate(void *startaddress);
 276
 277
 278 /*!
 279  * \fn void ICInvalidateRange(void *startaddress,u32 len)
 280  * \brief Invalidate a range in the L1 i-cache.
 281  *
 282  *        If any part of the range hits in the i-cache, the corresponding block will be invalidated.
 283  *
 284  * \param[in] startaddress pointer to the startaddress of the memory range to invalidate. <b><i>NOTE:</i></b> Has to be aligned on a 32byte boundery
 285  * \param[in] len length of the range to invalidate. <b><i>NOTE:</i></b> Should be a multiple of 32
 286  *
 287  * \return none
 288  */
 289 void ICInvalidateRange(void *startaddress,u32 len);
 290
 291 void LCEnable();
 292 void LCDisable();
 293 void LCLoadBlocks(void *,void *,u32);
 294 void LCStoreBlocks(void *,void *,u32);
 295 u32 LCLoadData(void *,void *,u32);
 296 u32 LCStoreData(void *,void *,u32);
 297 u32 LCQueueLength();
 298 u32 LCQueueWait(u32);
 299 void LCFlushQueue();
 300 void LCAlloc(void *,u32);
 301 void LCAllocNoInvalidate(void *,u32);
 302 void LCAllocOneTag(BOOL,void *);
 303 void LCAllocTags(BOOL,void *,u32);
 304
 305 #define LCGetBase()             ((void*)LC_BASE)
 306 #ifdef __cplusplus
 307    }
 308 #endif /* __cplusplus */
 309
 310 #endif