flight/pios/stm32f0x/pios_tim.c

   1 #include "pios.h"
   2
   3 #ifdef PIOS_INCLUDE_TIM
   4
   5 #include "pios_tim_priv.h"
   6
   7 enum pios_tim_dev_magic {
   8     PIOS_TIM_DEV_MAGIC = 0x87654098,
   9 };
  10
  11 struct pios_tim_dev {
  12     enum pios_tim_dev_magic magic;
  13
  14     const struct pios_tim_channel   *channels;
  15     uint8_t num_channels;
  16
  17     const struct pios_tim_callbacks *callbacks;
  18     uint32_t context;
  19 };
  20
  21 #if 0
  22 static bool PIOS_TIM_validate(struct pios_tim_dev *tim_dev)
  23 {
  24     return tim_dev->magic == PIOS_TIM_DEV_MAGIC;
  25 }
  26 #endif
  27
  28 #if defined(PIOS_INCLUDE_FREERTOS) && 0
  29 static struct pios_tim_dev *PIOS_TIM_alloc(void)
  30 {
  31     struct pios_tim_dev *tim_dev;
  32
  33     tim_dev = (struct pios_tim_dev *)malloc(sizeof(*tim_dev));
  34     if (!tim_dev) {
  35         return NULL;
  36     }
  37
  38     tim_dev->magic = PIOS_TIM_DEV_MAGIC;
  39     return tim_dev;
  40 }
  41 #else
  42 static struct pios_tim_dev pios_tim_devs[PIOS_TIM_MAX_DEVS];
  43 static uint8_t pios_tim_num_devs;
  44 static struct pios_tim_dev *PIOS_TIM_alloc(void)
  45 {
  46     struct pios_tim_dev *tim_dev;
  47
  48     if (pios_tim_num_devs >= PIOS_TIM_MAX_DEVS) {
  49         return NULL;
  50     }
  51
  52     tim_dev = &pios_tim_devs[pios_tim_num_devs++];
  53     tim_dev->magic = PIOS_TIM_DEV_MAGIC;
  54
  55     return tim_dev;
  56 }
  57 #endif /* if defined(PIOS_INCLUDE_FREERTOS) && 0 */
  58
  59
  60 int32_t PIOS_TIM_InitClock(const struct pios_tim_clock_cfg *cfg)
  61 {
  62     PIOS_DEBUG_Assert(cfg);
  63
  64     /* Enable appropriate clock to timer module */
  65     switch ((uint32_t)cfg->timer) {
  66     case (uint32_t)TIM1:
  67         RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
  68         break;
  69     case (uint32_t)TIM2:
  70         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
  71         break;
  72     case (uint32_t)TIM3:
  73         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
  74         break;
  75     case (uint32_t)TIM4:
  76         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
  77         break;
  78 #ifdef STM32F10X_HD
  79     case (uint32_t)TIM5:
  80         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
  81         break;
  82     case (uint32_t)TIM6:
  83         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
  84         break;
  85     case (uint32_t)TIM7:
  86         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, ENABLE);
  87         break;
  88     case (uint32_t)TIM8:
  89         RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);
  90         break;
  91 #endif
  92     }
  93
  94     /* Configure the dividers for this timer */
  95     TIM_TimeBaseInit(cfg->timer, cfg->time_base_init);
  96
  97     /* Configure internal timer clocks */
  98     TIM_InternalClockConfig(cfg->timer);
  99
 100     /* Enable timers */
 101     TIM_Cmd(cfg->timer, ENABLE);
 102
 103     /* Enable Interrupts */
 104     NVIC_Init(&cfg->irq.init);
 105
 106     return 0;
 107 }
 108
 109 int32_t PIOS_TIM_InitChannels(uint32_t *tim_id, const struct pios_tim_channel *channels, uint8_t num_channels, const struct pios_tim_callbacks *callbacks, uint32_t context)
 110 {
 111     PIOS_Assert(channels);
 112     PIOS_Assert(num_channels);
 113
 114     struct pios_tim_dev *tim_dev;
 115     tim_dev = (struct pios_tim_dev *)PIOS_TIM_alloc();
 116     if (!tim_dev) {
 117         goto out_fail;
 118     }
 119
 120     /* Bind the configuration to the device instance */
 121     tim_dev->channels     = channels;
 122     tim_dev->num_channels = num_channels;
 123     tim_dev->callbacks    = callbacks;
 124     tim_dev->context = context;
 125
 126     /* Configure the pins */
 127     for (uint8_t i = 0; i < num_channels; i++) {
 128         const struct pios_tim_channel *chan = &(channels[i]);
 129
 130         /* Enable the peripheral clock for the GPIO */
 131         switch ((uint32_t)chan->pin.gpio) {
 132         case (uint32_t)GPIOA:
 133             RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
 134             break;
 135         case (uint32_t)GPIOB:
 136             RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
 137             break;
 138         case (uint32_t)GPIOC:
 139             RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
 140             break;
 141         default:
 142             PIOS_Assert(0);
 143             break;
 144         }
 145         GPIO_Init(chan->pin.gpio, &chan->pin.init);
 146
 147         if (chan->remap) {
 148             GPIO_PinRemapConfig(chan->remap, ENABLE);
 149         }
 150     }
 151
 152     *tim_id = (uint32_t)tim_dev;
 153
 154     return 0;
 155
 156 out_fail:
 157     return -1;
 158 }
 159
 160 static void PIOS_TIM_generic_irq_handler(TIM_TypeDef *timer)
 161 {
 162     /* Iterate over all registered clients of the TIM layer to find channels on this timer */
 163     for (uint8_t i = 0; i < pios_tim_num_devs; i++) {
 164         const struct pios_tim_dev *tim_dev = &pios_tim_devs[i];
 165
 166         if (!tim_dev->channels || tim_dev->num_channels == 0) {
 167             /* No channels to process on this client */
 168             continue;
 169         }
 170
 171         /* Check for an overflow event on this timer */
 172         bool overflow_event;
 173         uint16_t overflow_count;
 174         if (TIM_GetITStatus(timer, TIM_IT_Update) == SET) {
 175             TIM_ClearITPendingBit(timer, TIM_IT_Update);
 176             overflow_count = timer->ARR;
 177             overflow_event = true;
 178         } else {
 179             overflow_count = 0;
 180             overflow_event = false;
 181         }
 182
 183         for (uint8_t j = 0; j < tim_dev->num_channels; j++) {
 184             const struct pios_tim_channel *chan = &tim_dev->channels[j];
 185
 186             if (chan->timer != timer) {
 187                 /* channel is not on this timer */
 188                 continue;
 189             }
 190
 191             /* Figure out which interrupt bit we should be looking at */
 192             uint16_t timer_it;
 193             switch (chan->timer_chan) {
 194             case TIM_Channel_1:
 195                 timer_it = TIM_IT_CC1;
 196                 break;
 197             case TIM_Channel_2:
 198                 timer_it = TIM_IT_CC2;
 199                 break;
 200             case TIM_Channel_3:
 201                 timer_it = TIM_IT_CC3;
 202                 break;
 203             case TIM_Channel_4:
 204                 timer_it = TIM_IT_CC4;
 205                 break;
 206             default:
 207                 PIOS_Assert(0);
 208                 break;
 209             }
 210
 211             bool edge_event;
 212             uint16_t edge_count;
 213             if (TIM_GetITStatus(chan->timer, timer_it) == SET) {
 214                 TIM_ClearITPendingBit(chan->timer, timer_it);
 215
 216                 /* Read the current counter */
 217                 switch (chan->timer_chan) {
 218                 case TIM_Channel_1:
 219                     edge_count = TIM_GetCapture1(chan->timer);
 220                     break;
 221                 case TIM_Channel_2:
 222                     edge_count = TIM_GetCapture2(chan->timer);
 223                     break;
 224                 case TIM_Channel_3:
 225                     edge_count = TIM_GetCapture3(chan->timer);
 226                     break;
 227                 case TIM_Channel_4:
 228                     edge_count = TIM_GetCapture4(chan->timer);
 229                     break;
 230                 default:
 231                     PIOS_Assert(0);
 232                     break;
 233                 }
 234                 edge_event = true;
 235             } else {
 236                 edge_event = false;
 237                 edge_count = 0;
 238             }
 239
 240             if (!tim_dev->callbacks) {
 241                 /* No callbacks registered, we're done with this channel */
 242                 continue;
 243             }
 244
 245             /* Generate the appropriate callbacks */
 246             if (overflow_event & edge_event) {
 247                 /*
 248                  * When both edge and overflow happen in the same interrupt, we
 249                  * need a heuristic to determine the order of the edge and overflow
 250                  * events so that the callbacks happen in the right order.  If we
 251                  * get the order wrong, our pulse width calculations could be off by up
 252                  * to ARR ticks.  That could be bad.
 253                  *
 254                  * Heuristic: If the edge_count is < 16 ticks above zero then we assume the
 255                  *            edge happened just after the overflow.
 256                  */
 257
 258                 if (edge_count < 16) {
 259                     /* Call the overflow callback first */
 260                     if (tim_dev->callbacks->overflow) {
 261                         (*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
 262                                                         tim_dev->context,
 263                                                         j,
 264                                                         overflow_count);
 265                     }
 266                     /* Call the edge callback second */
 267                     if (tim_dev->callbacks->edge) {
 268                         (*tim_dev->callbacks->edge)((uint32_t)tim_dev,
 269                                                     tim_dev->context,
 270                                                     j,
 271                                                     edge_count);
 272                     }
 273                 } else {
 274                     /* Call the edge callback first */
 275                     if (tim_dev->callbacks->edge) {
 276                         (*tim_dev->callbacks->edge)((uint32_t)tim_dev,
 277                                                     tim_dev->context,
 278                                                     j,
 279                                                     edge_count);
 280                     }
 281                     /* Call the overflow callback second */
 282                     if (tim_dev->callbacks->overflow) {
 283                         (*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
 284                                                         tim_dev->context,
 285                                                         j,
 286                                                         overflow_count);
 287                     }
 288                 }
 289             } else if (overflow_event && tim_dev->callbacks->overflow) {
 290                 (*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
 291                                                 tim_dev->context,
 292                                                 j,
 293                                                 overflow_count);
 294             } else if (edge_event && tim_dev->callbacks->edge) {
 295                 (*tim_dev->callbacks->edge)((uint32_t)tim_dev,
 296                                             tim_dev->context,
 297                                             j,
 298                                             edge_count);
 299             }
 300         }
 301     }
 302 }
 303 #if 0
 304 uint16_t val = 0;
 305 for (uint8_t i = 0; i < pios_pwm_cfg.num_channels; i++) {
 306     struct pios_pwm_channel channel = pios_pwm_cfg.channels[i];
 307     if ((channel.timer == timer) && (TIM_GetITStatus(channel.timer, channel.ccr) == SET)) {
 308         TIM_ClearITPendingBit(channel.timer, channel.ccr);
 309
 310         switch (channel.channel) {
 311         case TIM_Channel_1:
 312             val = TIM_GetCapture1(channel.timer);
 313             break;
 314         case TIM_Channel_2:
 315             val = TIM_GetCapture2(channel.timer);
 316             break;
 317         case TIM_Channel_3:
 318             val = TIM_GetCapture3(channel.timer);
 319             break;
 320         case TIM_Channel_4:
 321             val = TIM_GetCapture4(channel.timer);
 322             break;
 323         }
 324
 325         if (CaptureState[i] == 0) {
 326             RiseValue[i] = val;
 327         } else {
 328             FallValue[i] = val;
 329         }
 330
 331         // flip state machine and capture value here
 332         /* Simple rise or fall state machine */
 333         TIM_ICInitTypeDef TIM_ICInitStructure = pios_pwm_cfg.tim_ic_init;
 334         if (CaptureState[i] == 0) {
 335             /* Switch states */
 336             CaptureState[i] = 1;
 337
 338             /* Switch polarity of input capture */
 339             TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Falling;
 340             TIM_ICInitStructure.TIM_Channel    = channel.channel;
 341             TIM_ICInit(channel.timer, &TIM_ICInitStructure);
 342         } else {
 343             /* Capture computation */
 344             if (FallValue[i] > RiseValue[i]) {
 345                 CaptureValue[i] = (FallValue[i] - RiseValue[i]);
 346             } else {
 347                 CaptureValue[i] = ((channel.timer->ARR - RiseValue[i]) + FallValue[i]);
 348             }
 349
 350             /* Switch states */
 351             CaptureState[i] = 0;
 352
 353             /* Increase supervisor counter */
 354             CapCounter[i]++;
 355
 356             /* Switch polarity of input capture */
 357             TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Rising;
 358             TIM_ICInitStructure.TIM_Channel    = channel.channel;
 359             TIM_ICInit(channel.timer, &TIM_ICInitStructure);
 360         }
 361     }
 362 }
 363 #endif /* if 0 */
 364
 365 /* Bind Interrupt Handlers
 366  *
 367  * Map all valid TIM IRQs to the common interrupt handler
 368  * and give it enough context to properly demux the various timers
 369  */
 370 void TIM1_UP_IRQHandler(void) __attribute__((alias("PIOS_TIM_1_UP_irq_handler")));
 371 static void PIOS_TIM_1_UP_irq_handler(void)
 372 {
 373     PIOS_TIM_generic_irq_handler(TIM1);
 374 }
 375
 376 void TIM1_CC_IRQHandler(void) __attribute__((alias("PIOS_TIM_1_CC_irq_handler")));
 377 static void PIOS_TIM_1_CC_irq_handler(void)
 378 {
 379     PIOS_TIM_generic_irq_handler(TIM1);
 380 }
 381
 382 void TIM2_IRQHandler(void) __attribute__((alias("PIOS_TIM_2_irq_handler")));
 383 static void PIOS_TIM_2_irq_handler(void)
 384 {
 385     PIOS_TIM_generic_irq_handler(TIM2);
 386 }
 387
 388 void TIM3_IRQHandler(void) __attribute__((alias("PIOS_TIM_3_irq_handler")));
 389 static void PIOS_TIM_3_irq_handler(void)
 390 {
 391     PIOS_TIM_generic_irq_handler(TIM3);
 392 }
 393
 394 void TIM4_IRQHandler(void) __attribute__((alias("PIOS_TIM_4_irq_handler")));
 395 static void PIOS_TIM_4_irq_handler(void)
 396 {
 397     PIOS_TIM_generic_irq_handler(TIM4);
 398 }
 399
 400 void TIM5_IRQHandler(void) __attribute__((alias("PIOS_TIM_5_irq_handler")));
 401 static void PIOS_TIM_5_irq_handler(void)
 402 {
 403     PIOS_TIM_generic_irq_handler(TIM5);
 404 }
 405
 406 void TIM6_IRQHandler(void) __attribute__((alias("PIOS_TIM_6_irq_handler")));
 407 static void PIOS_TIM_6_irq_handler(void)
 408 {
 409     PIOS_TIM_generic_irq_handler(TIM6);
 410 }
 411
 412 void TIM7_IRQHandler(void) __attribute__((alias("PIOS_TIM_7_irq_handler")));
 413 static void PIOS_TIM_7_irq_handler(void)
 414 {
 415     PIOS_TIM_generic_irq_handler(TIM7);
 416 }
 417
 418 void TIM8_UP_IRQHandler(void) __attribute__((alias("PIOS_TIM_8_UP_irq_handler")));
 419 static void PIOS_TIM_8_UP_irq_handler(void)
 420 {
 421     PIOS_TIM_generic_irq_handler(TIM8);
 422 }
 423
 424 void TIM8_CC_IRQHandler(void) __attribute__((alias("PIOS_TIM_8_CC_irq_handler")));
 425 static void PIOS_TIM_8_CC_irq_handler(void)
 426 {
 427     PIOS_TIM_generic_irq_handler(TIM8);
 428 }
 429
 430 #endif /* PIOS_INCLUDE_TIM */