flight/pios/stm32f10x/libraries/STM32_USB-FS-Device_Driver/inc/usb_regs.h

   1 /******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
   2 * File Name          : usb_regs.h
   3 * Author             : MCD Application Team
   4 * Version            : V3.2.1
   5 * Date               : 07/05/2010
   6 * Description        : Interface prototype functions to USB cell registers
   7 ********************************************************************************
   8 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  12 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  14 *******************************************************************************/
  15
  16 /* Define to prevent recursive inclusion -------------------------------------*/
  17 #ifndef __USB_REGS_H
  18 #define __USB_REGS_H
  19
  20 #ifndef STM32F10X_CL
  21
  22 /* Includes ------------------------------------------------------------------*/
  23 /* Exported types ------------------------------------------------------------*/
  24 typedef enum _EP_DBUF_DIR
  25 {
  26   /* double buffered endpoint direction */
  27   EP_DBUF_ERR,
  28   EP_DBUF_OUT,
  29   EP_DBUF_IN
  30 }EP_DBUF_DIR;
  31
  32 /* endpoint buffer number */
  33 enum EP_BUF_NUM
  34 {
  35   EP_NOBUF,
  36   EP_BUF0,
  37   EP_BUF1
  38 };
  39
  40 /* Exported constants --------------------------------------------------------*/
  41 #define RegBase  (0x40005C00L)  /* USB_IP Peripheral Registers base address */
  42 #define PMAAddr  (0x40006000L)  /* USB_IP Packet Memory Area base address   */
  43
  44 /******************************************************************************/
  45 /*                         General registers                                  */
  46 /******************************************************************************/
  47
  48 /* Control register */
  49 #define CNTR    ((__IO unsigned *)(RegBase + 0x40))
  50 /* Interrupt status register */
  51 #define ISTR    ((__IO unsigned *)(RegBase + 0x44))
  52 /* Frame number register */
  53 #define FNR     ((__IO unsigned *)(RegBase + 0x48))
  54 /* Device address register */
  55 #define DADDR   ((__IO unsigned *)(RegBase + 0x4C))
  56 /* Buffer Table address register */
  57 #define BTABLE  ((__IO unsigned *)(RegBase + 0x50))
  58 /******************************************************************************/
  59 /*                         Endpoint registers                                 */
  60 /******************************************************************************/
  61 #define EP0REG  ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */
  62
  63 /* Endpoint Addresses (w/direction) */
  64 #define EP0_OUT     ((uint8_t)0x00)
  65 #define EP0_IN      ((uint8_t)0x80)
  66 #define EP1_OUT     ((uint8_t)0x01)
  67 #define EP1_IN      ((uint8_t)0x81)
  68 #define EP2_OUT     ((uint8_t)0x02)
  69 #define EP2_IN      ((uint8_t)0x82)
  70 #define EP3_OUT     ((uint8_t)0x03)
  71 #define EP3_IN      ((uint8_t)0x83)
  72 #define EP4_OUT     ((uint8_t)0x04)
  73 #define EP4_IN      ((uint8_t)0x84)
  74 #define EP5_OUT     ((uint8_t)0x05)
  75 #define EP5_IN      ((uint8_t)0x85)
  76 #define EP6_OUT     ((uint8_t)0x06)
  77 #define EP6_IN      ((uint8_t)0x86)
  78 #define EP7_OUT     ((uint8_t)0x07)
  79 #define EP7_IN      ((uint8_t)0x87)
  80
  81 /* endpoints enumeration */
  82 #define ENDP0       ((uint8_t)0)
  83 #define ENDP1       ((uint8_t)1)
  84 #define ENDP2       ((uint8_t)2)
  85 #define ENDP3       ((uint8_t)3)
  86 #define ENDP4       ((uint8_t)4)
  87 #define ENDP5       ((uint8_t)5)
  88 #define ENDP6       ((uint8_t)6)
  89 #define ENDP7       ((uint8_t)7)
  90
  91 /******************************************************************************/
  92 /*                       ISTR interrupt events                                */
  93 /******************************************************************************/
  94 #define ISTR_CTR    (0x8000) /* Correct TRansfer (clear-only bit) */
  95 #define ISTR_DOVR   (0x4000) /* DMA OVeR/underrun (clear-only bit) */
  96 #define ISTR_ERR    (0x2000) /* ERRor (clear-only bit) */
  97 #define ISTR_WKUP   (0x1000) /* WaKe UP (clear-only bit) */
  98 #define ISTR_SUSP   (0x0800) /* SUSPend (clear-only bit) */
  99 #define ISTR_RESET  (0x0400) /* RESET (clear-only bit) */
 100 #define ISTR_SOF    (0x0200) /* Start Of Frame (clear-only bit) */
 101 #define ISTR_ESOF   (0x0100) /* Expected Start Of Frame (clear-only bit) */
 102
 103
 104 #define ISTR_DIR    (0x0010)  /* DIRection of transaction (read-only bit)  */
 105 #define ISTR_EP_ID  (0x000F)  /* EndPoint IDentifier (read-only bit)  */
 106
 107 #define CLR_CTR    (~ISTR_CTR)   /* clear Correct TRansfer bit */
 108 #define CLR_DOVR   (~ISTR_DOVR)  /* clear DMA OVeR/underrun bit*/
 109 #define CLR_ERR    (~ISTR_ERR)   /* clear ERRor bit */
 110 #define CLR_WKUP   (~ISTR_WKUP)  /* clear WaKe UP bit     */
 111 #define CLR_SUSP   (~ISTR_SUSP)  /* clear SUSPend bit     */
 112 #define CLR_RESET  (~ISTR_RESET) /* clear RESET bit      */
 113 #define CLR_SOF    (~ISTR_SOF)   /* clear Start Of Frame bit   */
 114 #define CLR_ESOF   (~ISTR_ESOF)  /* clear Expected Start Of Frame bit */
 115
 116 /******************************************************************************/
 117 /*             CNTR control register bits definitions                         */
 118 /******************************************************************************/
 119 #define CNTR_CTRM   (0x8000) /* Correct TRansfer Mask */
 120 #define CNTR_DOVRM  (0x4000) /* DMA OVeR/underrun Mask */
 121 #define CNTR_ERRM   (0x2000) /* ERRor Mask */
 122 #define CNTR_WKUPM  (0x1000) /* WaKe UP Mask */
 123 #define CNTR_SUSPM  (0x0800) /* SUSPend Mask */
 124 #define CNTR_RESETM (0x0400) /* RESET Mask   */
 125 #define CNTR_SOFM   (0x0200) /* Start Of Frame Mask */
 126 #define CNTR_ESOFM  (0x0100) /* Expected Start Of Frame Mask */
 127
 128
 129 #define CNTR_RESUME (0x0010) /* RESUME request */
 130 #define CNTR_FSUSP  (0x0008) /* Force SUSPend */
 131 #define CNTR_LPMODE (0x0004) /* Low-power MODE */
 132 #define CNTR_PDWN   (0x0002) /* Power DoWN */
 133 #define CNTR_FRES   (0x0001) /* Force USB RESet */
 134
 135 /******************************************************************************/
 136 /*                FNR Frame Number Register bit definitions                   */
 137 /******************************************************************************/
 138 #define FNR_RXDP (0x8000) /* status of D+ data line */
 139 #define FNR_RXDM (0x4000) /* status of D- data line */
 140 #define FNR_LCK  (0x2000) /* LoCKed */
 141 #define FNR_LSOF (0x1800) /* Lost SOF */
 142 #define FNR_FN  (0x07FF) /* Frame Number */
 143 /******************************************************************************/
 144 /*               DADDR Device ADDRess bit definitions                         */
 145 /******************************************************************************/
 146 #define DADDR_EF (0x80)
 147 #define DADDR_ADD (0x7F)
 148 /******************************************************************************/
 149 /*                            Endpoint register                               */
 150 /******************************************************************************/
 151 /* bit positions */
 152 #define EP_CTR_RX      (0x8000) /* EndPoint Correct TRansfer RX */
 153 #define EP_DTOG_RX     (0x4000) /* EndPoint Data TOGGLE RX */
 154 #define EPRX_STAT      (0x3000) /* EndPoint RX STATus bit field */
 155 #define EP_SETUP       (0x0800) /* EndPoint SETUP */
 156 #define EP_T_FIELD     (0x0600) /* EndPoint TYPE */
 157 #define EP_KIND        (0x0100) /* EndPoint KIND */
 158 #define EP_CTR_TX      (0x0080) /* EndPoint Correct TRansfer TX */
 159 #define EP_DTOG_TX     (0x0040) /* EndPoint Data TOGGLE TX */
 160 #define EPTX_STAT      (0x0030) /* EndPoint TX STATus bit field */
 161 #define EPADDR_FIELD   (0x000F) /* EndPoint ADDRess FIELD */
 162
 163 /* EndPoint REGister MASK (no toggle fields) */
 164 #define EPREG_MASK     (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD)
 165
 166 /* EP_TYPE[1:0] EndPoint TYPE */
 167 #define EP_TYPE_MASK   (0x0600) /* EndPoint TYPE Mask */
 168 #define EP_BULK        (0x0000) /* EndPoint BULK */
 169 #define EP_CONTROL     (0x0200) /* EndPoint CONTROL */
 170 #define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
 171 #define EP_INTERRUPT   (0x0600) /* EndPoint INTERRUPT */
 172 #define EP_T_MASK      (~EP_T_FIELD & EPREG_MASK)
 173
 174
 175 /* EP_KIND EndPoint KIND */
 176 #define EPKIND_MASK    (~EP_KIND & EPREG_MASK)
 177
 178 /* STAT_TX[1:0] STATus for TX transfer */
 179 #define EP_TX_DIS      (0x0000) /* EndPoint TX DISabled */
 180 #define EP_TX_STALL    (0x0010) /* EndPoint TX STALLed */
 181 #define EP_TX_NAK      (0x0020) /* EndPoint TX NAKed */
 182 #define EP_TX_VALID    (0x0030) /* EndPoint TX VALID */
 183 #define EPTX_DTOG1     (0x0010) /* EndPoint TX Data TOGgle bit1 */
 184 #define EPTX_DTOG2     (0x0020) /* EndPoint TX Data TOGgle bit2 */
 185 #define EPTX_DTOGMASK  (EPTX_STAT|EPREG_MASK)
 186
 187 /* STAT_RX[1:0] STATus for RX transfer */
 188 #define EP_RX_DIS      (0x0000) /* EndPoint RX DISabled */
 189 #define EP_RX_STALL    (0x1000) /* EndPoint RX STALLed */
 190 #define EP_RX_NAK      (0x2000) /* EndPoint RX NAKed */
 191 #define EP_RX_VALID    (0x3000) /* EndPoint RX VALID */
 192 #define EPRX_DTOG1     (0x1000) /* EndPoint RX Data TOGgle bit1 */
 193 #define EPRX_DTOG2     (0x2000) /* EndPoint RX Data TOGgle bit1 */
 194 #define EPRX_DTOGMASK  (EPRX_STAT|EPREG_MASK)
 195 /* Exported macro ------------------------------------------------------------*/
 196 /* SetCNTR */
 197 #define _SetCNTR(wRegValue)  (*CNTR   = (uint16_t)wRegValue)
 198
 199 /* SetISTR */
 200 #define _SetISTR(wRegValue)  (*ISTR   = (uint16_t)wRegValue)
 201
 202 /* SetDADDR */
 203 #define _SetDADDR(wRegValue) (*DADDR  = (uint16_t)wRegValue)
 204
 205 /* SetBTABLE */
 206 #define _SetBTABLE(wRegValue)(*BTABLE = (uint16_t)(wRegValue & 0xFFF8))
 207
 208 /* GetCNTR */
 209 #define _GetCNTR()   ((uint16_t) *CNTR)
 210
 211 /* GetISTR */
 212 #define _GetISTR()   ((uint16_t) *ISTR)
 213
 214 /* GetFNR */
 215 #define _GetFNR()    ((uint16_t) *FNR)
 216
 217 /* GetDADDR */
 218 #define _GetDADDR()  ((uint16_t) *DADDR)
 219
 220 /* GetBTABLE */
 221 #define _GetBTABLE() ((uint16_t) *BTABLE)
 222
 223 /* SetENDPOINT */
 224 #define _SetENDPOINT(bEpNum,wRegValue)  (*(EP0REG + bEpNum)= \
 225     (uint16_t)wRegValue)
 226
 227 /* GetENDPOINT */
 228 #define _GetENDPOINT(bEpNum)        ((uint16_t)(*(EP0REG + bEpNum)))
 229
 230 /*******************************************************************************
 231 * Macro Name     : SetEPType
 232 * Description    : sets the type in the endpoint register(bits EP_TYPE[1:0])
 233 * Input          : bEpNum: Endpoint Number.
 234 *                  wType
 235 * Output         : None.
 236 * Return         : None.
 237 *******************************************************************************/
 238 #define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\
 239                                   ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType )))
 240
 241 /*******************************************************************************
 242 * Macro Name     : GetEPType
 243 * Description    : gets the type in the endpoint register(bits EP_TYPE[1:0])
 244 * Input          : bEpNum: Endpoint Number.
 245 * Output         : None.
 246 * Return         : Endpoint Type
 247 *******************************************************************************/
 248 #define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
 249
 250 /*******************************************************************************
 251 * Macro Name     : SetEPTxStatus
 252 * Description    : sets the status for tx transfer (bits STAT_TX[1:0]).
 253 * Input          : bEpNum: Endpoint Number.
 254 *                  wState: new state
 255 * Output         : None.
 256 * Return         : None.
 257 *******************************************************************************/
 258 #define _SetEPTxStatus(bEpNum,wState) {\
 259     register uint16_t _wRegVal;       \
 260     _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\
 261     /* toggle first bit ? */     \
 262     if((EPTX_DTOG1 & wState)!= 0)      \
 263       _wRegVal ^= EPTX_DTOG1;        \
 264     /* toggle second bit ?  */         \
 265     if((EPTX_DTOG2 & wState)!= 0)      \
 266       _wRegVal ^= EPTX_DTOG2;        \
 267     _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX));    \
 268   } /* _SetEPTxStatus */
 269
 270 /*******************************************************************************
 271 * Macro Name     : SetEPRxStatus
 272 * Description    : sets the status for rx transfer (bits STAT_TX[1:0])
 273 * Input          : bEpNum: Endpoint Number.
 274 *                  wState: new state.
 275 * Output         : None.
 276 * Return         : None.
 277 *******************************************************************************/
 278 #define _SetEPRxStatus(bEpNum,wState) {\
 279     register uint16_t _wRegVal;   \
 280     \
 281     _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\
 282     /* toggle first bit ? */  \
 283     if((EPRX_DTOG1 & wState)!= 0) \
 284       _wRegVal ^= EPRX_DTOG1;  \
 285     /* toggle second bit ? */  \
 286     if((EPRX_DTOG2 & wState)!= 0) \
 287       _wRegVal ^= EPRX_DTOG2;  \
 288     _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \
 289   } /* _SetEPRxStatus */
 290
 291 /*******************************************************************************
 292 * Macro Name     : SetEPRxTxStatus
 293 * Description    : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
 294 * Input          : bEpNum: Endpoint Number.
 295 *                  wStaterx: new state.
 296 *                  wStatetx: new state.
 297 * Output         : None.
 298 * Return         : None.
 299 *******************************************************************************/
 300 #define _SetEPRxTxStatus(bEpNum,wStaterx,wStatetx) {\
 301     register uint32_t _wRegVal;   \
 302     \
 303     _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DTOGMASK |EPTX_STAT) ;\
 304     /* toggle first bit ? */  \
 305     if((EPRX_DTOG1 & wStaterx)!= 0) \
 306       _wRegVal ^= EPRX_DTOG1;  \
 307     /* toggle second bit ? */  \
 308     if((EPRX_DTOG2 & wStaterx)!= 0) \
 309       _wRegVal ^= EPRX_DTOG2;  \
 310     /* toggle first bit ? */     \
 311     if((EPTX_DTOG1 & wStatetx)!= 0)      \
 312       _wRegVal ^= EPTX_DTOG1;        \
 313     /* toggle second bit ?  */         \
 314     if((EPTX_DTOG2 & wStatetx)!= 0)      \
 315       _wRegVal ^= EPTX_DTOG2;        \
 316     _SetENDPOINT(bEpNum, _wRegVal | EP_CTR_RX|EP_CTR_TX);    \
 317   } /* _SetEPRxTxStatus */
 318 /*******************************************************************************
 319 * Macro Name     : GetEPTxStatus / GetEPRxStatus
 320 * Description    : gets the status for tx/rx transfer (bits STAT_TX[1:0]
 321 *                  /STAT_RX[1:0])
 322 * Input          : bEpNum: Endpoint Number.
 323 * Output         : None.
 324 * Return         : status .
 325 *******************************************************************************/
 326 #define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STAT)
 327
 328 #define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STAT)
 329
 330 /*******************************************************************************
 331 * Macro Name     : SetEPTxValid / SetEPRxValid
 332 * Description    : sets directly the VALID tx/rx-status into the enpoint register
 333 * Input          : bEpNum: Endpoint Number.
 334 * Output         : None.
 335 * Return         : None.
 336 *******************************************************************************/
 337 #define _SetEPTxValid(bEpNum)     (_SetEPTxStatus(bEpNum, EP_TX_VALID))
 338
 339 #define _SetEPRxValid(bEpNum)     (_SetEPRxStatus(bEpNum, EP_RX_VALID))
 340
 341 /*******************************************************************************
 342 * Macro Name     : GetTxStallStatus / GetRxStallStatus.
 343 * Description    : checks stall condition in an endpoint.
 344 * Input          : bEpNum: Endpoint Number.
 345 * Output         : None.
 346 * Return         : TRUE = endpoint in stall condition.
 347 *******************************************************************************/
 348 #define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \
 349                                    == EP_TX_STALL)
 350 #define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \
 351                                    == EP_RX_STALL)
 352
 353 /*******************************************************************************
 354 * Macro Name     : SetEP_KIND / ClearEP_KIND.
 355 * Description    : set & clear EP_KIND bit.
 356 * Input          : bEpNum: Endpoint Number.
 357 * Output         : None.
 358 * Return         : None.
 359 *******************************************************************************/
 360 #define _SetEP_KIND(bEpNum)    (_SetENDPOINT(bEpNum, \
 361                                 (EP_CTR_RX|EP_CTR_TX|((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
 362 #define _ClearEP_KIND(bEpNum)  (_SetENDPOINT(bEpNum, \
 363                                 (EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPKIND_MASK))))
 364
 365 /*******************************************************************************
 366 * Macro Name     : Set_Status_Out / Clear_Status_Out.
 367 * Description    : Sets/clears directly STATUS_OUT bit in the endpoint register.
 368 * Input          : bEpNum: Endpoint Number.
 369 * Output         : None.
 370 * Return         : None.
 371 *******************************************************************************/
 372 #define _Set_Status_Out(bEpNum)    _SetEP_KIND(bEpNum)
 373 #define _Clear_Status_Out(bEpNum)  _ClearEP_KIND(bEpNum)
 374
 375 /*******************************************************************************
 376 * Macro Name     : SetEPDoubleBuff / ClearEPDoubleBuff.
 377 * Description    : Sets/clears directly EP_KIND bit in the endpoint register.
 378 * Input          : bEpNum: Endpoint Number.
 379 * Output         : None.
 380 * Return         : None.
 381 *******************************************************************************/
 382 #define _SetEPDoubleBuff(bEpNum)   _SetEP_KIND(bEpNum)
 383 #define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
 384
 385 /*******************************************************************************
 386 * Macro Name     : ClearEP_CTR_RX / ClearEP_CTR_TX.
 387 * Description    : Clears bit CTR_RX / CTR_TX in the endpoint register.
 388 * Input          : bEpNum: Endpoint Number.
 389 * Output         : None.
 390 * Return         : None.
 391 *******************************************************************************/
 392 #define _ClearEP_CTR_RX(bEpNum)   (_SetENDPOINT(bEpNum,\
 393                                    _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
 394 #define _ClearEP_CTR_TX(bEpNum)   (_SetENDPOINT(bEpNum,\
 395                                    _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
 396
 397 /*******************************************************************************
 398 * Macro Name     : ToggleDTOG_RX / ToggleDTOG_TX .
 399 * Description    : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
 400 * Input          : bEpNum: Endpoint Number.
 401 * Output         : None.
 402 * Return         : None.
 403 *******************************************************************************/
 404 #define _ToggleDTOG_RX(bEpNum)    (_SetENDPOINT(bEpNum, \
 405                                    EP_CTR_RX|EP_CTR_TX|EP_DTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
 406 #define _ToggleDTOG_TX(bEpNum)    (_SetENDPOINT(bEpNum, \
 407                                    EP_CTR_RX|EP_CTR_TX|EP_DTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
 408
 409 /*******************************************************************************
 410 * Macro Name     : ClearDTOG_RX / ClearDTOG_TX.
 411 * Description    : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
 412 * Input          : bEpNum: Endpoint Number.
 413 * Output         : None.
 414 * Return         : None.
 415 *******************************************************************************/
 416 #define _ClearDTOG_RX(bEpNum)  if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\
 417     _ToggleDTOG_RX(bEpNum)
 418 #define _ClearDTOG_TX(bEpNum)  if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\
 419     _ToggleDTOG_TX(bEpNum)
 420 /*******************************************************************************
 421 * Macro Name     : SetEPAddress.
 422 * Description    : Sets address in an endpoint register.
 423 * Input          : bEpNum: Endpoint Number.
 424 *                  bAddr: Address.
 425 * Output         : None.
 426 * Return         : None.
 427 *******************************************************************************/
 428 #define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\
 429     EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
 430
 431 /*******************************************************************************
 432 * Macro Name     : GetEPAddress.
 433 * Description    : Gets address in an endpoint register.
 434 * Input          : bEpNum: Endpoint Number.
 435 * Output         : None.
 436 * Return         : None.
 437 *******************************************************************************/
 438 #define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
 439
 440 #define _pEPTxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8  )*2 + PMAAddr))
 441 #define _pEPTxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr))
 442 #define _pEPRxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr))
 443 #define _pEPRxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr))
 444
 445 /*******************************************************************************
 446 * Macro Name     : SetEPTxAddr / SetEPRxAddr.
 447 * Description    : sets address of the tx/rx buffer.
 448 * Input          : bEpNum: Endpoint Number.
 449 *                  wAddr: address to be set (must be word aligned).
 450 * Output         : None.
 451 * Return         : None.
 452 *******************************************************************************/
 453 #define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
 454 #define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
 455
 456 /*******************************************************************************
 457 * Macro Name     : GetEPTxAddr / GetEPRxAddr.
 458 * Description    : Gets address of the tx/rx buffer.
 459 * Input          : bEpNum: Endpoint Number.
 460 * Output         : None.
 461 * Return         : address of the buffer.
 462 *******************************************************************************/
 463 #define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
 464 #define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
 465
 466 /*******************************************************************************
 467 * Macro Name     : SetEPCountRxReg.
 468 * Description    : Sets counter of rx buffer with no. of blocks.
 469 * Input          : pdwReg: pointer to counter.
 470 *                  wCount: Counter.
 471 * Output         : None.
 472 * Return         : None.
 473 *******************************************************************************/
 474 #define _BlocksOf32(dwReg,wCount,wNBlocks) {\
 475     wNBlocks = wCount >> 5;\
 476     if((wCount & 0x1f) == 0)\
 477       wNBlocks--;\
 478     *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000);\
 479   }/* _BlocksOf32 */
 480
 481 #define _BlocksOf2(dwReg,wCount,wNBlocks) {\
 482     wNBlocks = wCount >> 1;\
 483     if((wCount & 0x1) != 0)\
 484       wNBlocks++;\
 485     *pdwReg = (uint32_t)(wNBlocks << 10);\
 486   }/* _BlocksOf2 */
 487
 488 #define _SetEPCountRxReg(dwReg,wCount)  {\
 489     uint16_t wNBlocks;\
 490     if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\
 491     else {_BlocksOf2(dwReg,wCount,wNBlocks);}\
 492   }/* _SetEPCountRxReg */
 493
 494
 495
 496 #define _SetEPRxDblBuf0Count(bEpNum,wCount) {\
 497     uint32_t *pdwReg = _pEPTxCount(bEpNum); \
 498     _SetEPCountRxReg(pdwReg, wCount);\
 499   }
 500 /*******************************************************************************
 501 * Macro Name     : SetEPTxCount / SetEPRxCount.
 502 * Description    : sets counter for the tx/rx buffer.
 503 * Input          : bEpNum: endpoint number.
 504 *                  wCount: Counter value.
 505 * Output         : None.
 506 * Return         : None.
 507 *******************************************************************************/
 508 #define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount)
 509 #define _SetEPRxCount(bEpNum,wCount) {\
 510     uint32_t *pdwReg = _pEPRxCount(bEpNum); \
 511     _SetEPCountRxReg(pdwReg, wCount);\
 512   }
 513 /*******************************************************************************
 514 * Macro Name     : GetEPTxCount / GetEPRxCount.
 515 * Description    : gets counter of the tx buffer.
 516 * Input          : bEpNum: endpoint number.
 517 * Output         : None.
 518 * Return         : Counter value.
 519 *******************************************************************************/
 520 #define _GetEPTxCount(bEpNum)((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
 521 #define _GetEPRxCount(bEpNum)((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
 522
 523 /*******************************************************************************
 524 * Macro Name     : SetEPDblBuf0Addr / SetEPDblBuf1Addr.
 525 * Description    : Sets buffer 0/1 address in a double buffer endpoint.
 526 * Input          : bEpNum: endpoint number.
 527 *                : wBuf0Addr: buffer 0 address.
 528 * Output         : None.
 529 * Return         : None.
 530 *******************************************************************************/
 531 #define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);}
 532 #define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);}
 533
 534 /*******************************************************************************
 535 * Macro Name     : SetEPDblBuffAddr.
 536 * Description    : Sets addresses in a double buffer endpoint.
 537 * Input          : bEpNum: endpoint number.
 538 *                : wBuf0Addr: buffer 0 address.
 539 *                : wBuf1Addr = buffer 1 address.
 540 * Output         : None.
 541 * Return         : None.
 542 *******************************************************************************/
 543 #define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \
 544     _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\
 545     _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\
 546   } /* _SetEPDblBuffAddr */
 547
 548 /*******************************************************************************
 549 * Macro Name     : GetEPDblBuf0Addr / GetEPDblBuf1Addr.
 550 * Description    : Gets buffer 0/1 address of a double buffer endpoint.
 551 * Input          : bEpNum: endpoint number.
 552 * Output         : None.
 553 * Return         : None.
 554 *******************************************************************************/
 555 #define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
 556 #define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
 557
 558 /*******************************************************************************
 559 * Macro Name     : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count.
 560 * Description    : Gets buffer 0/1 address of a double buffer endpoint.
 561 * Input          : bEpNum: endpoint number.
 562 *                : bDir: endpoint dir  EP_DBUF_OUT = OUT
 563 *                                      EP_DBUF_IN  = IN
 564 *                : wCount: Counter value
 565 * Output         : None.
 566 * Return         : None.
 567 *******************************************************************************/
 568 #define _SetEPDblBuf0Count(bEpNum, bDir, wCount)  { \
 569     if(bDir == EP_DBUF_OUT)\
 570       /* OUT endpoint */ \
 571     {_SetEPRxDblBuf0Count(bEpNum,wCount);} \
 572     else if(bDir == EP_DBUF_IN)\
 573       /* IN endpoint */ \
 574       *_pEPTxCount(bEpNum) = (uint32_t)wCount;  \
 575   } /* SetEPDblBuf0Count*/
 576
 577 #define _SetEPDblBuf1Count(bEpNum, bDir, wCount)  { \
 578     if(bDir == EP_DBUF_OUT)\
 579       /* OUT endpoint */ \
 580     {_SetEPRxCount(bEpNum,wCount);}\
 581     else if(bDir == EP_DBUF_IN)\
 582       /* IN endpoint */\
 583       *_pEPRxCount(bEpNum) = (uint32_t)wCount; \
 584   } /* SetEPDblBuf1Count */
 585
 586 #define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\
 587     _SetEPDblBuf0Count(bEpNum, bDir, wCount); \
 588     _SetEPDblBuf1Count(bEpNum, bDir, wCount); \
 589   } /* _SetEPDblBuffCount  */
 590
 591 /*******************************************************************************
 592 * Macro Name     : GetEPDblBuf0Count / GetEPDblBuf1Count.
 593 * Description    : Gets buffer 0/1 rx/tx counter for double buffering.
 594 * Input          : bEpNum: endpoint number.
 595 * Output         : None.
 596 * Return         : None.
 597 *******************************************************************************/
 598 #define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
 599 #define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
 600
 601
 602 /* External variables --------------------------------------------------------*/
 603 extern __IO uint16_t wIstr;  /* ISTR register last read value */
 604
 605 /* Exported functions ------------------------------------------------------- */
 606 void SetCNTR(uint16_t /*wRegValue*/);
 607 void SetISTR(uint16_t /*wRegValue*/);
 608 void SetDADDR(uint16_t /*wRegValue*/);
 609 void SetBTABLE(uint16_t /*wRegValue*/);
 610 void SetBTABLE(uint16_t /*wRegValue*/);
 611 uint16_t GetCNTR(void);
 612 uint16_t GetISTR(void);
 613 uint16_t GetFNR(void);
 614 uint16_t GetDADDR(void);
 615 uint16_t GetBTABLE(void);
 616 void SetENDPOINT(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
 617 uint16_t GetENDPOINT(uint8_t /*bEpNum*/);
 618 void SetEPType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
 619 uint16_t GetEPType(uint8_t /*bEpNum*/);
 620 void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
 621 void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
 622 void SetDouBleBuffEPStall(uint8_t /*bEpNum*/, uint8_t bDir);
 623 uint16_t GetEPTxStatus(uint8_t /*bEpNum*/);
 624 uint16_t GetEPRxStatus(uint8_t /*bEpNum*/);
 625 void SetEPTxValid(uint8_t /*bEpNum*/);
 626 void SetEPRxValid(uint8_t /*bEpNum*/);
 627 uint16_t GetTxStallStatus(uint8_t /*bEpNum*/);
 628 uint16_t GetRxStallStatus(uint8_t /*bEpNum*/);
 629 void SetEP_KIND(uint8_t /*bEpNum*/);
 630 void ClearEP_KIND(uint8_t /*bEpNum*/);
 631 void Set_Status_Out(uint8_t /*bEpNum*/);
 632 void Clear_Status_Out(uint8_t /*bEpNum*/);
 633 void SetEPDoubleBuff(uint8_t /*bEpNum*/);
 634 void ClearEPDoubleBuff(uint8_t /*bEpNum*/);
 635 void ClearEP_CTR_RX(uint8_t /*bEpNum*/);
 636 void ClearEP_CTR_TX(uint8_t /*bEpNum*/);
 637 void ToggleDTOG_RX(uint8_t /*bEpNum*/);
 638 void ToggleDTOG_TX(uint8_t /*bEpNum*/);
 639 void ClearDTOG_RX(uint8_t /*bEpNum*/);
 640 void ClearDTOG_TX(uint8_t /*bEpNum*/);
 641 void SetEPAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
 642 uint8_t GetEPAddress(uint8_t /*bEpNum*/);
 643 void SetEPTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
 644 void SetEPRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
 645 uint16_t GetEPTxAddr(uint8_t /*bEpNum*/);
 646 uint16_t GetEPRxAddr(uint8_t /*bEpNum*/);
 647 void SetEPCountRxReg(uint32_t * /*pdwReg*/, uint16_t /*wCount*/);
 648 void SetEPTxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
 649 void SetEPRxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
 650 uint16_t GetEPTxCount(uint8_t /*bEpNum*/);
 651 uint16_t GetEPRxCount(uint8_t /*bEpNum*/);
 652 void SetEPDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
 653 void SetEPDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
 654 void SetEPDblBuffAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
 655 uint16_t GetEPDblBuf0Addr(uint8_t /*bEpNum*/);
 656 uint16_t GetEPDblBuf1Addr(uint8_t /*bEpNum*/);
 657 void SetEPDblBuffCount(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
 658 void SetEPDblBuf0Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
 659 void SetEPDblBuf1Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
 660 uint16_t GetEPDblBuf0Count(uint8_t /*bEpNum*/);
 661 uint16_t GetEPDblBuf1Count(uint8_t /*bEpNum*/);
 662 EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
 663 void FreeUserBuffer(uint8_t bEpNum/*bEpNum*/, uint8_t bDir);
 664 uint16_t ToWord(uint8_t, uint8_t);
 665 uint16_t ByteSwap(uint16_t);
 666
 667 #endif /* STM32F10X_CL */
 668
 669 #endif /* __USB_REGS_H */
 670
 671 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/