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[librepilot.git] / flight / pios / stm32f10x / pios_bkp.c
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1 /**
2 ******************************************************************************
3 * @addtogroup PIOS PIOS Core hardware abstraction layer
4 * @{
5 * @addtogroup PIOS_BKP Backup SRAM functions
6 * @brief Hardware abstraction layer for backup sram
7 * @{
9 * @file pios_bkp.c
10 * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2013.
11 * @brief IAP functions
12 * @see The GNU Public License (GPL) Version 3
14 *****************************************************************************/
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 3 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 * for more details.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 #include <pios.h>
32 #include <pios_bkp.h>
33 #include <stm32f10x.h>
34 #include <stm32f10x_bkp.h>
35 #include <stm32f10x_pwr.h>
37 /****************************************************************************************
38 * Header files
39 ****************************************************************************************/
41 /*****************************************************************************************
42 * Public Definitions/Macros
43 ****************************************************************************************/
45 /****************************************************************************************
46 * Public Functions
47 ****************************************************************************************/
48 const uint32_t pios_bkp_registers_map[] = {
49 BKP_DR1,
50 BKP_DR2,
51 BKP_DR3,
52 BKP_DR4,
53 BKP_DR5,
54 BKP_DR6,
55 BKP_DR7,
56 BKP_DR8,
57 BKP_DR9,
58 BKP_DR10,
59 BKP_DR11,
60 BKP_DR12,
61 BKP_DR13,
62 BKP_DR14,
63 BKP_DR15,
64 BKP_DR16,
65 BKP_DR17,
66 BKP_DR18,
67 BKP_DR19,
69 #if FALSE /* Not enabled as stm32f4 needs some modifications to
70 * accomodate more than 20 registers (like storing 2 uint16_t
71 * regs in one uint32_t bkp location)
73 BKP_DR20,
74 BKP_DR21,
75 BKP_DR22,
76 BKP_DR23,
77 BKP_DR24,
78 BKP_DR25,
79 BKP_DR26,
80 BKP_DR27,
81 BKP_DR28,
82 BKP_DR29,
83 BKP_DR30,
84 BKP_DR32,
85 BKP_DR33,
86 BKP_DR34,
87 BKP_DR35,
88 BKP_DR36,
89 BKP_DR37,
90 BKP_DR38,
91 BKP_DR39,
92 BKP_DR40,
93 BKP_DR41,
94 BKP_DR42,
95 #endif /* if FALSE */
97 #define PIOS_BKP_REGISTERS_COUNT NELEMENTS(pios_bkp_registers_map)
99 void PIOS_BKP_Init(void)
101 /* Enable CRC clock */
102 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE);
104 /* Enable PWR and BKP clock */
105 RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE);
107 /* Clear Tamper pin Event(TE) pending flag */
108 BKP_ClearFlag();
111 uint16_t PIOS_BKP_ReadRegister(uint32_t regnumber)
113 if (PIOS_BKP_REGISTERS_COUNT < regnumber) {
114 PIOS_Assert(0);
115 } else {
116 return (uint16_t)BKP_ReadBackupRegister(pios_bkp_registers_map[regnumber]);
120 void PIOS_BKP_WriteRegister(uint32_t regnumber, uint16_t data)
122 if (PIOS_BKP_REGISTERS_COUNT < regnumber) {
123 PIOS_Assert(0);
124 } else {
125 BKP_WriteBackupRegister(pios_bkp_registers_map[regnumber], (uint32_t)data);
129 void PIOS_BKP_EnableWrite(void)
131 /* Enable write access to Backup domain */
132 PWR_BackupAccessCmd(ENABLE);
135 void PIOS_BKP_DisableWrite(void)
137 /* Enable write access to Backup domain */
138 PWR_BackupAccessCmd(DISABLE);
142 /****************************************************************************************
143 * Public Data
144 ****************************************************************************************/