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1 /******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
2 * File Name : usb_conf.h
3 * Author : MCD Application Team
4 * Version : V3.2.1
5 * Date : 07/05/2010
6 * Description : Custom HID demo configuration file
7 ********************************************************************************
8 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
12 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
14 *******************************************************************************/
16 /* Define to prevent recursive inclusion -------------------------------------*/
17 #ifndef __USB_CONF_H
18 #define __USB_CONF_H
20 /* Includes ------------------------------------------------------------------*/
21 /* Exported types ------------------------------------------------------------*/
22 /* Exported constants --------------------------------------------------------*/
23 /* Exported macro ------------------------------------------------------------*/
24 /* Exported functions ------------------------------------------------------- */
25 /* External variables --------------------------------------------------------*/
27 #ifndef STM32F10X_CL
28 /*-------------------------------------------------------------*/
29 /* -------------- Buffer Description Table -----------------*/
30 /*-------------------------------------------------------------*/
31 /* buffer table base address */
32 /* buffer table base address */
33 #define BTABLE_ADDRESS (0x00)
35 /* EP0 */
36 /* rx/tx buffer base address */
37 #define ENDP0_RXADDR (0x20)
38 #define ENDP0_TXADDR (0x40)
40 /* EP1 */
41 /* rx/tx buffer base address */
42 #define ENDP1_TXADDR (0x60)
43 #define ENDP1_RXADDR (0x80)
45 /* EP2 */
46 /* rx/tx buffer base address */
47 #define ENDP2_TXADDR (0x100)
48 #define ENDP2_RXADDR (0x140)
50 /* EP3 */
51 /* rx/tx buffer base address */
52 #define ENDP3_TXADDR (0x180)
53 #define ENDP3_RXADDR (0x1C0)
55 /*-------------------------------------------------------------*/
56 /* ------------------- ISTR events -------------------------*/
57 /*-------------------------------------------------------------*/
58 /* IMR_MSK */
59 /* mask defining which events has to be handled */
60 /* by the device application software */
61 #define IMR_MSK \
62 (CNTR_CTRM | CNTR_WKUPM | CNTR_SUSPM | CNTR_ERRM | CNTR_SOFM \
63 | CNTR_ESOFM | CNTR_RESETM)
65 /* Provide a callback function for SOF so we can do early USB detection */
66 #define SOF_CALLBACK
68 /* Provide a callback function for SUSPend so we can notice a cable removal event */
69 #define SUSP_CALLBACK
73 #ifdef STM32F10X_CL
75 /*******************************************************************************
76 * FIFO Size Configuration
77 *
78 * (i) Dedicated data FIFO SPRAM of 1.25 Kbytes = 1280 bytes = 320 32-bits words
79 * available for the endpoints IN and OUT.
80 * Device mode features:
81 * -1 bidirectional CTRL EP 0
82 * -3 IN EPs to support any kind of Bulk, Interrupt or Isochronous transfer
83 * -3 OUT EPs to support any kind of Bulk, Interrupt or Isochronous transfer
84 *
85 * ii) Receive data FIFO size = RAM for setup packets +
86 * OUT endpoint control information +
87 * data OUT packets + miscellaneous
88 * Space = ONE 32-bits words
89 * --> RAM for setup packets = 4 * n + 6 space
90 * (n is the nbr of CTRL EPs the device core supports)
91 * --> OUT EP CTRL info = 1 space
92 * (one space for status information written to the FIFO along with each
93 * received packet)
94 * --> data OUT packets = (Largest Packet Size / 4) + 1 spaces
95 * (MINIMUM to receive packets)
96 * --> OR data OUT packets = at least 2*(Largest Packet Size / 4) + 1 spaces
97 * (if high-bandwidth EP is enabled or multiple isochronous EPs)
98 * --> miscellaneous = 1 space per OUT EP
99 * (one space for transfer complete status information also pushed to the
100 * FIFO with each endpoint's last packet)
101 *
102 * (iii)MINIMUM RAM space required for each IN EP Tx FIFO = MAX packet size for
103 * that particular IN EP. More space allocated in the IN EP Tx FIFO results
104 * in a better performance on the USB and can hide latencies on the AHB.
105 *
106 * (iv) TXn min size = 16 words. (n : Transmit FIFO index)
107 * (v) When a TxFIFO is not used, the Configuration should be as follows:
108 * case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes)
109 * --> Txm can use the space allocated for Txn.
110 * case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes)
111 * --> Txn should be configured with the minimum space of 16 words
112 * (vi) The FIFO is used optimally when used TxFIFOs are allocated in the top
113 * of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones.
114 *******************************************************************************/
116 #define RX_FIFO_SIZE 128
117 #define TX0_FIFO_SIZE 64
118 #define TX1_FIFO_SIZE 64
119 #define TX2_FIFO_SIZE 16
120 #define TX3_FIFO_SIZE 16
122 /* OTGD-FS-DEVICE IP interrupts Enable definitions */
123 /* Uncomment the define to enable the selected interrupt */
124 // #define INTR_MODEMISMATCH
125 #define INTR_SOFINTR
127 // #define INTR_NPTXFEMPTY
128 // #define INTR_GINNAKEFF
129 // #define INTR_GOUTNAKEFF
130 // #define INTR_ERLYSUSPEND
134 // #define INTR_ISOOUTDROP
135 // #define INTR_EOPFRAME
136 // #define INTR_EPMISMATCH
139 // #define INTR_INCOMPLISOIN
140 // #define INTR_INCOMPLISOOUT
143 /* OTGD-FS-DEVICE IP interrupts subroutines */
144 /* Comment the define to enable the selected interrupt subroutine and replace it
145 by user code */
146 #define INTR_MODEMISMATCH_Callback NOP_Process
147 #define INTR_SOFINTR_Callback NOP_Process
148 #define INTR_RXSTSQLVL_Callback NOP_Process
149 #define INTR_NPTXFEMPTY_Callback NOP_Process
150 #define INTR_NPTXFEMPTY_Callback NOP_Process
151 #define INTR_GINNAKEFF_Callback NOP_Process
152 #define INTR_GOUTNAKEFF_Callback NOP_Process
153 #define INTR_ERLYSUSPEND_Callback NOP_Process
154 #define INTR_USBSUSPEND_Callback NOP_Process
155 #define INTR_USBRESET_Callback NOP_Process
156 #define INTR_ENUMDONE_Callback NOP_Process
157 #define INTR_ISOOUTDROP_Callback NOP_Process
158 #define INTR_EOPFRAME_Callback NOP_Process
159 #define INTR_EPMISMATCH_Callback NOP_Process
160 #define INTR_INEPINTR_Callback NOP_Process
161 #define INTR_OUTEPINTR_Callback NOP_Process
162 #define INTR_INCOMPLISOIN_Callback NOP_Process
163 #define INTR_INCOMPLISOOUT_Callback NOP_Process
164 #define INTR_WKUPINTR_Callback NOP_Process
166 /* Isochronous data update */
167 #define INTR_RXSTSQLVL_ISODU_Callback NOP_Process
169 /* Isochronous transfer parameters */
170 /* Size of a single Isochronous buffer (size of a single transfer) */
171 #define ISOC_BUFFER_SZE 1
172 /* Number of sub-buffers (number of single buffers/transfers), should be even */
173 #define NUM_SUB_BUFFERS 2
177 /* CTR service routines */
178 /* associated to defined endpoints */
179 #define EP1_IN_Callback NOP_Process
180 #define EP2_IN_Callback NOP_Process
181 #define EP3_IN_Callback NOP_Process
182 #define EP4_IN_Callback NOP_Process
183 #define EP5_IN_Callback NOP_Process
184 #define EP6_IN_Callback NOP_Process
185 #define EP7_IN_Callback NOP_Process
187 #define EP1_OUT_Callback NOP_Process
188 #define EP2_OUT_Callback NOP_Process
189 #define EP3_OUT_Callback NOP_Process
190 #define EP4_OUT_Callback NOP_Process
191 #define EP5_OUT_Callback NOP_Process
192 #define EP6_OUT_Callback NOP_Process
193 #define EP7_OUT_Callback NOP_Process
197 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/