flight/pios/stm32f30x/system.c

   1 /**
   2  ******************************************************************************
   3  * @file    system_stm32f30x.c
   4  * @author  MCD Application Team
   5  * @version V1.0.0
   6  * @date    04-September-2012
   7  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   8  *          This file contains the system clock configuration for STM32F30x devices,
   9  *          and is generated by the clock configuration tool
  10  *          stm32f30x_Clock_Configuration_V1.0.0.xls
  11  *
  12  * 1.  This file provides two functions and one global variable to be called from
  13  *     user application:
  14  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  15  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
  16  *                      depending on the configuration made in the clock xls tool.
  17  *                      This function is called at startup just after reset and
  18  *                      before branch to main program. This call is made inside
  19  *                      the "startup_stm32f30x.s" file.
  20  *
  21  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  22  *                                  by the user application to setup the SysTick
  23  *                                  timer or configure other parameters.
  24  *
  25  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  26  *                                 be called whenever the core clock is changed
  27  *                                 during program execution.
  28  *
  29  * 2. After each device reset the HSI (8 MHz) is used as system clock source.
  30  *    Then SystemInit() function is called, in "startup_stm32f30x.s" file, to
  31  *    configure the system clock before to branch to main program.
  32  *
  33  * 3. If the system clock source selected by user fails to startup, the SystemInit()
  34  *    function will do nothing and HSI still used as system clock source. User can
  35  *    add some code to deal with this issue inside the SetSysClock() function.
  36  *
  37  * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
  38  *    in "stm32f30x.h" file. When HSE is used as system clock source, directly or
  39  *    through PLL, and you are using different crystal you have to adapt the HSE
  40  *    value to your own configuration.
  41  *
  42  * 5. This file configures the system clock as follows:
  43  *=============================================================================
  44  *                         Supported STM32F30x device
  45  *-----------------------------------------------------------------------------
  46  *        System Clock source                    | PLL (HSE)
  47  *-----------------------------------------------------------------------------
  48  *        SYSCLK(Hz)                             | 72000000
  49  *-----------------------------------------------------------------------------
  50  *        HCLK(Hz)                               | 72000000
  51  *-----------------------------------------------------------------------------
  52  *        AHB Prescaler                          | 1
  53  *-----------------------------------------------------------------------------
  54  *        APB2 Prescaler                         | 1
  55  *-----------------------------------------------------------------------------
  56  *        APB1 Prescaler                         | 2
  57  *-----------------------------------------------------------------------------
  58  *        HSE Frequency(Hz)                      | 8000000
  59  *----------------------------------------------------------------------------
  60  *        PLLMUL                                 | 9
  61  *-----------------------------------------------------------------------------
  62  *        PREDIV                                 | 1
  63  *-----------------------------------------------------------------------------
  64  *        USB Clock                              | DISABLE
  65  *-----------------------------------------------------------------------------
  66  *        Flash Latency(WS)                      | 2
  67  *-----------------------------------------------------------------------------
  68  *        Prefetch Buffer                        | ON
  69  *-----------------------------------------------------------------------------
  70  *=============================================================================
  71  ******************************************************************************
  72  * @attention
  73  *
  74  * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
  75  *
  76  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  77  * You may not use this file except in compliance with the License.
  78  * You may obtain a copy of the License at:
  79  *
  80  *        http://www.st.com/software_license_agreement_liberty_v2
  81  *
  82  * Unless required by applicable law or agreed to in writing, software
  83  * distributed under the License is distributed on an "AS IS" BASIS,
  84  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  85  * See the License for the specific language governing permissions and
  86  * limitations under the License.
  87  *
  88  ******************************************************************************
  89  */
  90 /** @addtogroup CMSIS
  91  * @{
  92  */
  93
  94 /** @addtogroup stm32f30x_system
  95  * @{
  96  */
  97
  98 /** @addtogroup STM32F30x_System_Private_Includes
  99  * @{
 100  */
 101
 102 #include "stm32f30x.h"
 103
 104 /**
 105  * @}
 106  */
 107
 108 /** @addtogroup STM32F30x_System_Private_TypesDefinitions
 109  * @{
 110  */
 111
 112 /**
 113  * @}
 114  */
 115
 116 /** @addtogroup STM32F30x_System_Private_Defines
 117  * @{
 118  */
 119 /*!< Uncomment the following line if you need to relocate your vector Table in
 120      Internal SRAM. */
 121 /* #define VECT_TAB_SRAM */
 122 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
 123                                  This value must be a multiple of 0x200. */
 124 /**
 125  * @}
 126  */
 127
 128 /** @addtogroup STM32F30x_System_Private_Macros
 129  * @{
 130  */
 131
 132 /**
 133  * @}
 134  */
 135
 136 /** @addtogroup STM32F30x_System_Private_Variables
 137  * @{
 138  */
 139
 140 uint32_t SystemCoreClock = 72000000;
 141
 142 __I uint8_t AHBPrescTable[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9 };
 143
 144 /**
 145  * @}
 146  */
 147
 148 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
 149  * @{
 150  */
 151
 152 static void SetSysClock(void);
 153
 154 /**
 155  * @}
 156  */
 157
 158 /** @addtogroup STM32F30x_System_Private_Functions
 159  * @{
 160  */
 161
 162 /**
 163  * @brief  Setup the microcontroller system
 164  *         Initialize the Embedded Flash Interface, the PLL and update the
 165  *         SystemFrequency variable.
 166  * @param  None
 167  * @retval None
 168  */
 169 void SystemInit(void)
 170 {
 171     /* FPU settings ------------------------------------------------------------*/
 172   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 173     SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10 and CP11 Full Access */
 174   #endif
 175
 176     /* Reset the RCC clock configuration to the default reset state ------------*/
 177     /* Set HSION bit */
 178     RCC->CR    |= (uint32_t)0x00000001;
 179
 180     /* Reset CFGR register */
 181     RCC->CFGR  &= 0xF87FC00C;
 182
 183     /* Reset HSEON, CSSON and PLLON bits */
 184     RCC->CR    &= (uint32_t)0xFEF6FFFF;
 185
 186     /* Reset HSEBYP bit */
 187     RCC->CR    &= (uint32_t)0xFFFBFFFF;
 188
 189     /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
 190     RCC->CFGR  &= (uint32_t)0xFF80FFFF;
 191
 192     /* Reset PREDIV1[3:0] bits */
 193     RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
 194
 195     /* Reset USARTSW[1:0], I2CSW and TIMs bits */
 196     RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
 197
 198     /* Disable all interrupts */
 199     RCC->CIR    = 0x00000000;
 200
 201     /* Configure the System clock source, PLL Multiplier and Divider factors,
 202        AHB/APBx prescalers and Flash settings ----------------------------------*/
 203     SetSysClock();
 204
 205 #ifdef VECT_TAB_SRAM
 206     SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 207 #else
 208     SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 209 #endif
 210 }
 211
 212 /**
 213  * @brief  Update SystemCoreClock variable according to Clock Register Values.
 214  *         The SystemCoreClock variable contains the core clock (HCLK), it can
 215  *         be used by the user application to setup the SysTick timer or configure
 216  *         other parameters.
 217  *
 218  * @note   Each time the core clock (HCLK) changes, this function must be called
 219  *         to update SystemCoreClock variable value. Otherwise, any configuration
 220  *         based on this variable will be incorrect.
 221  *
 222  * @note   - The system frequency computed by this function is not the real
 223  *           frequency in the chip. It is calculated based on the predefined
 224  *           constant and the selected clock source:
 225  *
 226  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 227  *
 228  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 229  *
 230  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 231  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 232  *
 233  *         (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
 234  *             8 MHz) but the real value may vary depending on the variations
 235  *             in voltage and temperature.
 236  *
 237  *         (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
 238  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
 239  *              frequency of the crystal used. Otherwise, this function may
 240  *              have wrong result.
 241  *
 242  *         - The result of this function could be not correct when using fractional
 243  *           value for HSE crystal.
 244  *
 245  * @param  None
 246  * @retval None
 247  */
 248 void SystemCoreClockUpdate(void)
 249 {
 250     uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
 251
 252     /* Get SYSCLK source -------------------------------------------------------*/
 253     tmp = RCC->CFGR & RCC_CFGR_SWS;
 254
 255     switch (tmp) {
 256     case 0x00: /* HSI used as system clock */
 257         SystemCoreClock = HSI_VALUE;
 258         break;
 259     case 0x04: /* HSE used as system clock */
 260         SystemCoreClock = HSE_VALUE;
 261         break;
 262     case 0x08: /* PLL used as system clock */
 263         /* Get PLL clock source and multiplication factor ----------------------*/
 264         pllmull   = RCC->CFGR & RCC_CFGR_PLLMULL;
 265         pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
 266         pllmull   = (pllmull >> 18) + 2;
 267
 268         if (pllsource == 0x00) {
 269             /* HSI oscillator clock divided by 2 selected as PLL clock entry */
 270             SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
 271         } else {
 272             prediv1factor   = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
 273             /* HSE oscillator clock selected as PREDIV1 clock entry */
 274             SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
 275         }
 276         break;
 277     default: /* HSI used as system clock */
 278         SystemCoreClock = HSI_VALUE;
 279         break;
 280     }
 281     /* Compute HCLK clock frequency ----------------*/
 282     /* Get HCLK prescaler */
 283     tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 284     /* HCLK clock frequency */
 285     SystemCoreClock >>= tmp;
 286 }
 287
 288 /**
 289  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 290  *               AHB/APBx prescalers and Flash settings
 291  * @note   This function should be called only once the RCC clock configuration
 292  *         is reset to the default reset state (done in SystemInit() function).
 293  * @param  None
 294  * @retval None
 295  */
 296 static void SetSysClock(void)
 297 {
 298     __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 299
 300 /******************************************************************************/
 301 /*            PLL (clocked by HSE) used as System clock source                */
 302 /******************************************************************************/
 303
 304     /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------*/
 305     /* Enable HSE */
 306 #ifdef PIOS_RCC_HSE_BYPASS
 307     RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
 308 #else
 309     RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 310 #endif /* PIOS_HSE_BYPASS */
 311
 312     /* Wait till HSE is ready and if Time out is reached exit */
 313     do {
 314         HSEStatus = RCC->CR & RCC_CR_HSERDY;
 315         StartUpCounter++;
 316     } while ((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 317
 318     if ((RCC->CR & RCC_CR_HSERDY) != RESET) {
 319         HSEStatus = (uint32_t)0x01;
 320     } else {
 321         HSEStatus = (uint32_t)0x00;
 322     }
 323
 324     if (HSEStatus == (uint32_t)0x01) {
 325         /* Enable Prefetch Buffer and set Flash Latency */
 326         FLASH->ACR = FLASH_ACR_PRFTBE | (uint32_t)FLASH_ACR_LATENCY_1;
 327
 328         /* HCLK = SYSCLK / 1 */
 329         RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
 330
 331         /* PCLK2 = HCLK / 1 */
 332         RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
 333
 334         /* PCLK1 = HCLK / 2 */
 335         RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
 336
 337         /* PLL configuration */
 338         RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
 339         RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL9);
 340
 341         /* Enable PLL */
 342         RCC->CR   |= RCC_CR_PLLON;
 343
 344         /* Wait till PLL is ready */
 345         while ((RCC->CR & RCC_CR_PLLRDY) == 0) {}
 346
 347         /* Select PLL as system clock source */
 348         RCC->CFGR &= (uint32_t)((uint32_t) ~(RCC_CFGR_SW));
 349         RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
 350
 351         /* Wait till PLL is used as system clock source */
 352         while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) {}
 353     } else { /* If HSE fails to start-up, the application will have wrong clock
 354                   configuration. User can add here some code to deal with this error */
 355     }
 356 }
 357
 358 /**
 359  * @}
 360  */
 361
 362 /**
 363  * @}
 364  */
 365
 366 /**
 367  * @}
 368  */
 369
 370 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/