2 ******************************************************************************
3 * @addtogroup PIOS PIOS Core hardware abstraction layer
5 * @addtogroup PIOS_BKP Backup SRAM functions
6 * @brief Hardware abstraction layer for backup sram
10 * @author The OpenPilot Team, http://www.openpilot.org Copyright (C) 2013.
11 * @brief IAP functions
12 * @see The GNU Public License (GPL) Version 3
14 *****************************************************************************/
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 3 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
23 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
33 #include <stm32f4xx_rtc.h>
35 /****************************************************************************************
37 ****************************************************************************************/
39 /*****************************************************************************************
40 * Public Definitions/Macros
41 ****************************************************************************************/
43 /****************************************************************************************
45 ****************************************************************************************/
46 const uint32_t pios_bkp_registers_map
[] = {
68 #define PIOS_BKP_REGISTERS_COUNT NELEMENTS(pios_bkp_registers_map)
70 void PIOS_BKP_Init(void)
72 /* Enable CRC clock */
73 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_CRC
| RCC_AHB1Periph_BKPSRAM
, ENABLE
);
75 /* Enable PWR and BKP clock */
76 RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR
, ENABLE
);
78 /* Clear Tamper pin Event(TE) pending flag */
79 RTC_ClearFlag(RTC_FLAG_TAMP1F
);
82 uint16_t PIOS_BKP_ReadRegister(uint32_t regnumber
)
84 if (PIOS_BKP_REGISTERS_COUNT
< regnumber
) {
87 return (uint16_t)RTC_ReadBackupRegister(pios_bkp_registers_map
[regnumber
]);
91 void PIOS_BKP_WriteRegister(uint32_t regnumber
, uint16_t data
)
93 if (PIOS_BKP_REGISTERS_COUNT
< regnumber
) {
96 RTC_WriteBackupRegister(pios_bkp_registers_map
[regnumber
], (uint32_t)data
);
100 void PIOS_BKP_EnableWrite(void)
102 /* Enable write access to Backup domain */
103 PWR_BackupAccessCmd(ENABLE
);
106 void PIOS_BKP_DisableWrite(void)
108 /* Enable write access to Backup domain */
109 PWR_BackupAccessCmd(DISABLE
);
113 /****************************************************************************************
115 ****************************************************************************************/