flight/pios/stm32f4xx/pios_tim.c

   1 /**
   2  ******************************************************************************
   3  * @addtogroup PIOS PIOS Core hardware abstraction layer
   4  * @{
   5  * @addtogroup PIOS_TIM Timer Functions
   6  * @brief PIOS Timer control code
   7  * @{
   8  *
   9  * @file       pios_tim.c
  10  * @author     The OpenPilot Team, http://www.openpilot.org Copyright (C) 2012.
  11  * @brief      Sets up timers and ways to register callbacks on them
  12  * @see        The GNU Public License (GPL) Version 3
  13  *
  14  *****************************************************************************/
  15 /*
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 3 of the License, or
  19  * (at your option) any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful, but
  22  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  23  * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  24  * for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License along
  27  * with this program; if not, write to the Free Software Foundation, Inc.,
  28  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  29  */
  30
  31
  32 #include "pios.h"
  33
  34 #ifdef PIOS_INCLUDE_TIM
  35
  36 #include "pios_tim_priv.h"
  37
  38 enum pios_tim_dev_magic {
  39     PIOS_TIM_DEV_MAGIC = 0x87654098,
  40 };
  41
  42 struct pios_tim_dev {
  43     enum pios_tim_dev_magic magic;
  44
  45     const struct pios_tim_channel   *channels;
  46     uint8_t num_channels;
  47
  48     const struct pios_tim_callbacks *callbacks;
  49     uint32_t context;
  50 };
  51 #define PIOS_TIM_ALL_FLAGS TIM_IT_CC1 | TIM_IT_CC2 | TIM_IT_CC3 | TIM_IT_CC4 | TIM_IT_Trigger | TIM_IT_Update
  52
  53 static struct pios_tim_dev pios_tim_devs[PIOS_TIM_MAX_DEVS];
  54 static uint8_t pios_tim_num_devs;
  55 static struct pios_tim_dev *PIOS_TIM_alloc(void)
  56 {
  57     struct pios_tim_dev *tim_dev;
  58
  59     if (pios_tim_num_devs >= PIOS_TIM_MAX_DEVS) {
  60         return NULL;
  61     }
  62
  63     tim_dev = &pios_tim_devs[pios_tim_num_devs++];
  64     tim_dev->magic = PIOS_TIM_DEV_MAGIC;
  65
  66     return tim_dev;
  67 }
  68
  69
  70 int32_t PIOS_TIM_InitClock(const struct pios_tim_clock_cfg *cfg)
  71 {
  72     PIOS_DEBUG_Assert(cfg);
  73
  74     /* Enable appropriate clock to timer module */
  75     switch ((uint32_t)cfg->timer) {
  76     case (uint32_t)TIM1:
  77         RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM1, ENABLE);
  78         break;
  79     case (uint32_t)TIM2:
  80         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);
  81         break;
  82     case (uint32_t)TIM3:
  83         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
  84         break;
  85     case (uint32_t)TIM4:
  86         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
  87         break;
  88     case (uint32_t)TIM5:
  89         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE);
  90         break;
  91     case (uint32_t)TIM6:
  92         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM6, ENABLE);
  93         break;
  94     case (uint32_t)TIM7:
  95         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM7, ENABLE);
  96         break;
  97     case (uint32_t)TIM8:
  98         RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM8, ENABLE);
  99         break;
 100     case (uint32_t)TIM9:
 101         RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE);
 102         break;
 103     case (uint32_t)TIM10:
 104         RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM10, ENABLE);
 105         break;
 106     case (uint32_t)TIM11:
 107         RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM11, ENABLE);
 108         break;
 109     case (uint32_t)TIM12:
 110         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM12, ENABLE);
 111         break;
 112     case (uint32_t)TIM13:
 113         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM13, ENABLE);
 114         break;
 115     case (uint32_t)TIM14:
 116         RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM14, ENABLE);
 117         break;
 118     }
 119
 120     /* Configure the dividers for this timer */
 121     TIM_TimeBaseInit(cfg->timer, cfg->time_base_init);
 122
 123     /* Configure internal timer clocks */
 124     TIM_InternalClockConfig(cfg->timer);
 125
 126     /* Enable timers */
 127     TIM_Cmd(cfg->timer, ENABLE);
 128
 129     /* Enable Interrupts */
 130     NVIC_Init(&cfg->irq.init);
 131
 132
 133     // Advanced timers TIM1 & TIM8 need special handling:
 134     // There are up to 4 separate interrupts handlers for each advanced timer, but
 135     // pios_tim_clock_cfg has provision for only one irq init, so we take care here
 136     // to enable additional irq channels that we intend to use.
 137
 138
 139     if (cfg->timer == TIM1) {
 140         NVIC_InitTypeDef init = cfg->irq.init;
 141         init.NVIC_IRQChannel = TIM1_UP_TIM10_IRQn;
 142         NVIC_Init(&init);
 143 #if !defined(STM32F401xx) && !defined(STM32F411xE)
 144     } else if (cfg->timer == TIM8) {
 145         NVIC_InitTypeDef init = cfg->irq.init;
 146         init.NVIC_IRQChannel = TIM8_UP_TIM13_IRQn;
 147         NVIC_Init(&init);
 148 #endif
 149     }
 150
 151     return 0;
 152 }
 153
 154 int32_t PIOS_TIM_InitChannels(uint32_t *tim_id, const struct pios_tim_channel *channels, uint8_t num_channels, const struct pios_tim_callbacks *callbacks, uint32_t context)
 155 {
 156     PIOS_Assert(channels);
 157     PIOS_Assert(num_channels);
 158
 159     struct pios_tim_dev *tim_dev;
 160     tim_dev = (struct pios_tim_dev *)PIOS_TIM_alloc();
 161     if (!tim_dev) {
 162         goto out_fail;
 163     }
 164
 165     /* Bind the configuration to the device instance */
 166     tim_dev->channels     = channels;
 167     tim_dev->num_channels = num_channels;
 168     tim_dev->callbacks    = callbacks;
 169     tim_dev->context = context;
 170
 171     /* Configure the pins */
 172     for (uint8_t i = 0; i < num_channels; i++) {
 173         const struct pios_tim_channel *chan = &(channels[i]);
 174
 175         /* Enable the peripheral clock for the GPIO */
 176 /*              switch ((uint32_t)chan->pin.gpio) {
 177                 case (uint32_t) GPIOA:
 178                         RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
 179                         break;
 180                 case (uint32_t) GPIOB:
 181                         RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
 182                         break;
 183                 case (uint32_t) GPIOC:
 184                         RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
 185                         break;
 186                 default:
 187                         PIOS_Assert(0);
 188                         break;
 189                 }
 190  */                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                       // commented out for now as f4 starts all clocks
 191         GPIO_Init(chan->pin.gpio, &chan->pin.init);
 192
 193         PIOS_DEBUG_Assert(chan->remap);
 194
 195         // Second parameter should technically be PinSource but they are numerically the same
 196         GPIO_PinAFConfig(chan->pin.gpio, chan->pin.pin_source, chan->remap);
 197     }
 198
 199     *tim_id = (uint32_t)tim_dev;
 200
 201     return 0;
 202
 203 out_fail:
 204     return -1;
 205 }
 206
 207 static void PIOS_TIM_generic_irq_handler(TIM_TypeDef *timer)
 208 {
 209     /* Iterate over all registered clients of the TIM layer to find channels on this timer */
 210     for (uint8_t i = 0; i < pios_tim_num_devs; i++) {
 211         const struct pios_tim_dev *tim_dev = &pios_tim_devs[i];
 212
 213         if (!tim_dev->channels || tim_dev->num_channels == 0) {
 214             /* No channels to process on this client */
 215             continue;
 216         }
 217
 218         /* Check for an overflow event on this timer */
 219         bool overflow_event;
 220         uint16_t overflow_count;
 221         if (TIM_GetITStatus(timer, TIM_IT_Update) == SET) {
 222             TIM_ClearITPendingBit(timer, TIM_IT_Update);
 223             overflow_count = timer->ARR;
 224             overflow_event = true;
 225         } else {
 226             overflow_count = 0;
 227             overflow_event = false;
 228         }
 229
 230         for (uint8_t j = 0; j < tim_dev->num_channels; j++) {
 231             const struct pios_tim_channel *chan = &tim_dev->channels[j];
 232
 233             if (chan->timer != timer) {
 234                 /* channel is not on this timer */
 235                 continue;
 236             }
 237
 238             /* Figure out which interrupt bit we should be looking at */
 239             uint16_t timer_it;
 240             switch (chan->timer_chan) {
 241             case TIM_Channel_1:
 242                 timer_it = TIM_IT_CC1;
 243                 break;
 244             case TIM_Channel_2:
 245                 timer_it = TIM_IT_CC2;
 246                 break;
 247             case TIM_Channel_3:
 248                 timer_it = TIM_IT_CC3;
 249                 break;
 250             case TIM_Channel_4:
 251                 timer_it = TIM_IT_CC4;
 252                 break;
 253             default:
 254                 PIOS_Assert(0);
 255                 break;
 256             }
 257
 258             bool edge_event;
 259             uint16_t edge_count;
 260             if (TIM_GetITStatus(chan->timer, timer_it) == SET) {
 261                 TIM_ClearITPendingBit(chan->timer, timer_it);
 262
 263                 /* Read the current counter */
 264                 switch (chan->timer_chan) {
 265                 case TIM_Channel_1:
 266                     edge_count = TIM_GetCapture1(chan->timer);
 267                     break;
 268                 case TIM_Channel_2:
 269                     edge_count = TIM_GetCapture2(chan->timer);
 270                     break;
 271                 case TIM_Channel_3:
 272                     edge_count = TIM_GetCapture3(chan->timer);
 273                     break;
 274                 case TIM_Channel_4:
 275                     edge_count = TIM_GetCapture4(chan->timer);
 276                     break;
 277                 default:
 278                     PIOS_Assert(0);
 279                     break;
 280                 }
 281                 edge_event = true;
 282             } else {
 283                 edge_event = false;
 284                 edge_count = 0;
 285             }
 286
 287             if (!tim_dev->callbacks) {
 288                 /* No callbacks registered, we're done with this channel */
 289                 continue;
 290             }
 291
 292             /* Generate the appropriate callbacks */
 293             if (overflow_event & edge_event) {
 294                 /*
 295                  * When both edge and overflow happen in the same interrupt, we
 296                  * need a heuristic to determine the order of the edge and overflow
 297                  * events so that the callbacks happen in the right order.  If we
 298                  * get the order wrong, our pulse width calculations could be off by up
 299                  * to ARR ticks.  That could be bad.
 300                  *
 301                  * Heuristic: If the edge_count is < 16 ticks above zero then we assume the
 302                  *            edge happened just after the overflow.
 303                  */
 304
 305                 if (edge_count < 16) {
 306                     /* Call the overflow callback first */
 307                     if (tim_dev->callbacks->overflow) {
 308                         (*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
 309                                                         tim_dev->context,
 310                                                         j,
 311                                                         overflow_count);
 312                     }
 313                     /* Call the edge callback second */
 314                     if (tim_dev->callbacks->edge) {
 315                         (*tim_dev->callbacks->edge)((uint32_t)tim_dev,
 316                                                     tim_dev->context,
 317                                                     j,
 318                                                     edge_count);
 319                     }
 320                 } else {
 321                     /* Call the edge callback first */
 322                     if (tim_dev->callbacks->edge) {
 323                         (*tim_dev->callbacks->edge)((uint32_t)tim_dev,
 324                                                     tim_dev->context,
 325                                                     j,
 326                                                     edge_count);
 327                     }
 328                     /* Call the overflow callback second */
 329                     if (tim_dev->callbacks->overflow) {
 330                         (*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
 331                                                         tim_dev->context,
 332                                                         j,
 333                                                         overflow_count);
 334                     }
 335                 }
 336             } else if (overflow_event && tim_dev->callbacks->overflow) {
 337                 (*tim_dev->callbacks->overflow)((uint32_t)tim_dev,
 338                                                 tim_dev->context,
 339                                                 j,
 340                                                 overflow_count);
 341             } else if (edge_event && tim_dev->callbacks->edge) {
 342                 (*tim_dev->callbacks->edge)((uint32_t)tim_dev,
 343                                             tim_dev->context,
 344                                             j,
 345                                             edge_count);
 346             }
 347         }
 348     }
 349 }
 350
 351 /* Bind Interrupt Handlers
 352  *
 353  * Map all valid TIM IRQs to the common interrupt handler
 354  * and give it enough context to properly demux the various timers
 355  */
 356 void TIM1_CC_IRQHandler(void) __attribute__((alias("PIOS_TIM_1_CC_irq_handler")));
 357 static void PIOS_TIM_1_CC_irq_handler(void)
 358 {
 359     PIOS_TIM_generic_irq_handler(TIM1);
 360 }
 361
 362 void TIM2_IRQHandler(void) __attribute__((alias("PIOS_TIM_2_irq_handler")));
 363 static void PIOS_TIM_2_irq_handler(void)
 364 {
 365     PIOS_TIM_generic_irq_handler(TIM2);
 366 }
 367
 368 void TIM3_IRQHandler(void) __attribute__((alias("PIOS_TIM_3_irq_handler")));
 369 static void PIOS_TIM_3_irq_handler(void)
 370 {
 371     PIOS_TIM_generic_irq_handler(TIM3);
 372 }
 373
 374 void TIM4_IRQHandler(void) __attribute__((alias("PIOS_TIM_4_irq_handler")));
 375 static void PIOS_TIM_4_irq_handler(void)
 376 {
 377     PIOS_TIM_generic_irq_handler(TIM4);
 378 }
 379
 380 void TIM5_IRQHandler(void) __attribute__((alias("PIOS_TIM_5_irq_handler")));
 381 static void PIOS_TIM_5_irq_handler(void)
 382 {
 383     PIOS_TIM_generic_irq_handler(TIM5);
 384 }
 385
 386 void TIM6_IRQHandler(void) __attribute__((alias("PIOS_TIM_6_irq_handler")));
 387 static void PIOS_TIM_6_irq_handler(void)
 388 {
 389     PIOS_TIM_generic_irq_handler(TIM6);
 390 }
 391
 392 void TIM7_IRQHandler(void) __attribute__((alias("PIOS_TIM_7_irq_handler")));
 393 static void PIOS_TIM_7_irq_handler(void)
 394 {
 395     PIOS_TIM_generic_irq_handler(TIM7);
 396 }
 397
 398 void TIM8_CC_IRQHandler(void) __attribute__((alias("PIOS_TIM_8_CC_irq_handler")));
 399 static void PIOS_TIM_8_CC_irq_handler(void)
 400 {
 401     PIOS_TIM_generic_irq_handler(TIM8);
 402 }
 403
 404 // The rest of TIM1 interrupts are overlapped
 405 void TIM1_BRK_TIM9_IRQHandler(void) __attribute__((alias("PIOS_TIM_9_CC_irq_handler")));
 406 static void PIOS_TIM_9_CC_irq_handler(void)
 407 {
 408     if (TIM_GetITStatus(TIM1, TIM_IT_Break)) {
 409         PIOS_TIM_generic_irq_handler(TIM1);
 410     } else if (TIM_GetITStatus(TIM9, PIOS_TIM_ALL_FLAGS)) {
 411         PIOS_TIM_generic_irq_handler(TIM9);
 412     }
 413 }
 414
 415 void TIM1_UP_TIM10_IRQHandler(void) __attribute__((alias("PIOS_TIM_10_CC_irq_handler")));
 416 static void PIOS_TIM_10_CC_irq_handler(void)
 417 {
 418     if (TIM_GetITStatus(TIM1, TIM_IT_Update)) {
 419         PIOS_TIM_generic_irq_handler(TIM1);
 420     } else if (TIM_GetITStatus(TIM10, PIOS_TIM_ALL_FLAGS)) {
 421         PIOS_TIM_generic_irq_handler(TIM10);
 422     }
 423 }
 424
 425 void TIM1_TRG_COM_TIM11_IRQHandler(void) __attribute__((alias("PIOS_TIM_11_CC_irq_handler")));
 426 static void PIOS_TIM_11_CC_irq_handler(void)
 427 {
 428     if (TIM_GetITStatus(TIM1, TIM_IT_COM | TIM_IT_Trigger)) {
 429         PIOS_TIM_generic_irq_handler(TIM1);
 430     } else if (TIM_GetITStatus(TIM11, PIOS_TIM_ALL_FLAGS)) {
 431         PIOS_TIM_generic_irq_handler(TIM11);
 432     }
 433 }
 434
 435 void TIM8_BRK_TIM12_IRQHandler(void) __attribute__((alias("PIOS_TIM_12_irq_handler")));
 436 static void PIOS_TIM_12_irq_handler(void)
 437 {
 438     if (TIM_GetITStatus(TIM8, TIM_IT_Break)) {
 439         PIOS_TIM_generic_irq_handler(TIM8);
 440     } else if (TIM_GetITStatus(TIM12, PIOS_TIM_ALL_FLAGS)) {
 441         PIOS_TIM_generic_irq_handler(TIM12);
 442     }
 443 }
 444
 445 void TIM8_UP_TIM13_IRQHandler(void) __attribute__((alias("PIOS_TIM8_UP_TIM13_IRQHandler")));
 446 static void PIOS_TIM8_UP_TIM13_IRQHandler(void)
 447 {
 448     if (TIM_GetITStatus(TIM8, TIM_IT_Update)) {
 449         PIOS_TIM_generic_irq_handler(TIM8);
 450     } else if (TIM_GetITStatus(TIM13, PIOS_TIM_ALL_FLAGS)) {
 451         PIOS_TIM_generic_irq_handler(TIM13);
 452     }
 453 }
 454
 455 void TIM8_TRG_COM_TIM14_IRQHandler(void) __attribute__((alias("PIOS_TIM8_TRG_COM_TIM14_IRQHandler")));
 456 static void PIOS_TIM8_TRG_COM_TIM14_IRQHandler(void)
 457 {
 458     if (TIM_GetITStatus(TIM8, TIM_IT_COM | TIM_IT_Trigger)) {
 459         PIOS_TIM_generic_irq_handler(TIM8);
 460     } else if (TIM_GetITStatus(TIM14, PIOS_TIM_ALL_FLAGS)) {
 461         PIOS_TIM_generic_irq_handler(TIM14);
 462     }
 463 }
 464
 465 #endif /* PIOS_INCLUDE_TIM */
 466
 467 /**
 468  * @}
 469  * @}
 470  */