flight/pios/inc/pios_rfm22b_regs.h

   1 /**
   2  ******************************************************************************
   3  * @addtogroup PIOS PIOS Core hardware abstraction layer
   4  * @{
   5  * @addtogroup   PIOS_RFM22B Radio Functions
   6  * @brief PIOS interface for RFM22B Radio
   7  * @{
   8  *
   9  * @file       pios_rfm22b_regs.h
  10  * @author     The OpenPilot Team, http://www.openpilot.org Copyright (C) 2012.
  11  * @author     Tau Labs, http://taulabs.org, Copyright (C) 2014
  12  * @author     LibrePilot, http://librepilot.org, Copyright (C) 2016
  13  * @brief      RFM22B private definitions.
  14  * @see        The GNU Public License (GPL) Version 3
  15  *
  16  *****************************************************************************/
  17 /*
  18  * This program is free software; you can redistribute it and/or modify
  19  * it under the terms of the GNU General Public License as published by
  20  * the Free Software Foundation; either version 3 of the License, or
  21  * (at your option) any later version.
  22  *
  23  * This program is distributed in the hope that it will be useful, but
  24  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  25  * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  26  * for more details.
  27  *
  28  * You should have received a copy of the GNU General Public License along
  29  * with this program; if not, write to the Free Software Foundation, Inc.,
  30  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  31  */
  32
  33 #ifndef PIOS_RFM22B_REGS_H
  34 #define PIOS_RFM22B_REGS_H
  35
  36 // ************************************
  37
  38 #define RFM22_DEVICE_VERSION_V2                   0x02
  39 #define RFM22_DEVICE_VERSION_A0                   0x04
  40 #define RFM22_DEVICE_VERSION_B1                   0x06
  41
  42 // ************************************
  43
  44 #define BIT0                                      (1u << 0)
  45 #define BIT1                                      (1u << 1)
  46 #define BIT2                                      (1u << 2)
  47 #define BIT3                                      (1u << 3)
  48 #define BIT4                                      (1u << 4)
  49 #define BIT5                                      (1u << 5)
  50 #define BIT6                                      (1u << 6)
  51 #define BIT7                                      (1u << 7)
  52
  53 // ************************************
  54
  55 #define RFM22_DEVICE_TYPE                         0x00  // R
  56 #define RFM22_DT_MASK                             0x1F
  57
  58 #define RFM22_DEVICE_VERSION                      0x01  // R
  59 #define RFM22_DV_MASK                             0x1F
  60
  61 #define RFM22_device_status                       0x02  // R
  62 #define RFM22_ds_cps_mask                         0x03  // Chip Power State mask
  63 #define RFM22_ds_cps_idle                         0x00  // IDLE Chip Power State
  64 #define RFM22_ds_cps_rx                           0x01  // RX Chip Power State
  65 #define RFM22_ds_cps_tx                           0x02  // TX Chip Power State
  66 // #define RFM22_ds_lockdet                                             0x04            //
  67 // #define RFM22_ds_freqerr                                             0x08            //
  68 #define RFM22_ds_headerr                          0x10  // Header Error Status. Indicates if the received packet has a header check error
  69 #define RFM22_ds_rxffem                           0x20  // RX FIFO Empty Status
  70 #define RFM22_ds_ffunfl                           0x40  // RX/TX FIFO Underflow Status
  71 #define RFM22_ds_ffovfl                           0x80  // RX/TX FIFO Overflow Status
  72
  73 #define RFM22_interrupt_status1                   0x03  // R
  74 #define RFM22_is1_icrerror                        BIT0  // CRC Error. When set to 1 the cyclic redundancy check is failed.
  75 #define RFM22_is1_ipkvalid                        BIT1  // Valid Packet Received.When set to 1 a valid packet has been received.
  76 #define RFM22_is1_ipksent                         BIT2  // Packet Sent Interrupt. When set to1 a valid packet has been transmitted.
  77 #define RFM22_is1_iext                            BIT3  // External Interrupt. When set to 1 an interrupt occurred on one of the GPIO�s if it is programmed so. The status can be checked in register 0Eh. See GPIOx Configuration section for the details.
  78 #define RFM22_is1_irxffafull                      BIT4  // RX FIFO Almost Full.When set to 1 the RX FIFO has met its almost full threshold and needs to be read by the microcontroller.
  79 #define RFM22_is1_ixtffaem                        BIT5  // TX FIFO Almost Empty. When set to 1 the TX FIFO is almost empty and needs to be filled.
  80 #define RFM22_is1_itxffafull                      BIT6  // TX FIFO Almost Full. When set to 1 the TX FIFO has met its almost full threshold and needs to be transmitted.
  81 #define RFM22_is1_ifferr                          BIT7  // FIFO Underflow/Overflow Error. When set to 1 the TX or RX FIFO has overflowed or underflowed.
  82
  83 #define RFM22_interrupt_status2                   0x04  // R
  84 #define RFM22_is2_ipor                            BIT0  // Power-on-Reset (POR). When the chip detects a Power on Reset above the desired setting this bit will be set to 1.
  85 #define RFM22_is2_ichiprdy                        BIT1  // Chip Ready (XTAL). When a chip ready event has been detected this bit will be set to 1.
  86 #define RFM22_is2_ilbd                            BIT2  // Low Battery Detect. When a low battery event is been detected this bit will be set to 1. This interrupt event is saved even if it is not enabled by the mask register bit and causes an interrupt after it is enabled.
  87 #define RFM22_is2_iwut                            BIT3  // Wake-Up-Timer. On the expiration of programmed wake-up timer this bit will be set to 1.
  88 #define RFM22_is2_irssi                           BIT4  // RSSI. When RSSI level exceeds the programmed threshold this bit will be set to 1.
  89 #define RFM22_is2_ipreainval                      BIT5  // Invalid Preamble Detected. When the preamble is not found within a period of time set by the invalid preamble detection threshold in Register 54h, this bit will be set to 1.
  90 #define RFM22_is2_ipreaval                        BIT6  // Valid Preamble Detected. When a preamble is detected this bit will be set to 1.
  91 #define RFM22_is2_iswdet                          BIT7  // Sync Word Detected. When a sync word is detected this bit will be set to 1.
  92
  93 #define RFM22_interrupt_enable1                   0x05  // R/W
  94 #define RFM22_ie1_encrcerror                      BIT0  // Enable CRC Error. When set to 1 the CRC Error interrupt will be enabled.
  95 #define RFM22_ie1_enpkvalid                       BIT1  // Enable Valid Packet Received. When ipkvalid = 1 the Valid Packet Received Interrupt will be enabled.
  96 #define RFM22_ie1_enpksent                        BIT2  // Enable Packet Sent. When ipksent =1 the Packet Sense Interrupt will be enabled.
  97 #define RFM22_ie1_enext                           BIT3  // Enable External Interrupt. When set to 1 the External Interrupt will be enabled.
  98 #define RFM22_ie1_enrxffafull                     BIT4  // Enable RX FIFO Almost Full. When set to 1 the RX FIFO Almost Full interrupt will be enabled.
  99 #define RFM22_ie1_entxffaem                       BIT5  // Enable TX FIFO Almost Empty. When set to 1 the TX FIFO Almost Empty interrupt will be enabled.
 100 #define RFM22_ie1_entxffafull                     BIT6  // Enable TX FIFO Almost Full. When set to 1 the TX FIFO Almost Full interrupt will be enabled.
 101 #define RFM22_ie1_enfferr                         BIT7  // Enable FIFO Underflow/Overflow. When set to 1 the FIFO Underflow/Overflow interrupt will be enabled.
 102
 103 #define RFM22_interrupt_enable2                   0x06  // R/W
 104 #define RFM22_ie2_enpor                           BIT0  // Enable POR. When set to 1 the POR interrupt will be enabled.
 105 #define RFM22_ie2_enchiprdy                       BIT1  // Enable Chip Ready (XTAL). When set to 1 the Chip Ready interrupt will be enabled.
 106 #define RFM22_ie2_enlbd                           BIT2  // Enable Low Battery Detect. When set to 1 the Low Battery Detect interrupt will be enabled.
 107 #define RFM22_ie2_enwut                           BIT3  // Enable Wake-Up Timer. When set to 1 the Wake-Up Timer interrupt will be enabled.
 108 #define RFM22_ie2_enrssi                          BIT4  // Enable RSSI. When set to 1 the RSSI Interrupt will be enabled.
 109 #define RFM22_ie2_enpreainval                     BIT5  // Enable Invalid Preamble Detected. When mpreadet =1 the Invalid Preamble Detected Interrupt will be enabled.
 110 #define RFM22_ie2_enpreaval                       BIT6  // Enable Valid Preamble Detected. When mpreadet =1 the Valid Preamble Detected Interrupt will be enabled.
 111 #define RFM22_ie2_enswdet                         BIT7  // Enable Sync Word Detected. When mpreadet =1 the Preamble Detected Interrupt will be enabled.
 112
 113 #define RFM22_op_and_func_ctrl1                   0x07  // R/W
 114 #define RFM22_opfc1_xton                          0x01  // READY Mode (Xtal is ON).
 115 #define RFM22_opfc1_pllon                         0x02  // TUNE Mode (PLL is ON). When pllon = 1 the PLL will remain enabled in Idle State. This will for faster turn-around time at the cost of increased current consumption in Idle State.
 116 #define RFM22_opfc1_rxon                          0x04  // RX on in Manual Receiver Mode. Automatically cleared if Multiple Packets config. is disabled and a valid packet received.
 117 #define RFM22_opfc1_txon                          0x08  // TX on in Manual Transmit Mode. Automatically cleared in FIFO mode once the packet is sent. Transmission can be aborted during packet transmission, however, when no data has been sent yet, transmission can only be aborted after the device is programmed to �unmodulated carrier� ("Register 71h. Modulation Mode Control 2").
 118 #define RFM22_opfc1_x32ksel                       0x10  // 32,768 kHz Crystal Oscillator Select.   0: RC oscillator    1: 32 kHz crystal
 119 #define RFM22_opfc1_enwt                          0x20  // Enable Wake-Up-Timer. Enabled when enwt = 1. If the Wake-up-Timer function is enabled it will operate in any mode and notify the microcontroller through the GPIO interrupt when the timer expires.
 120 #define RFM22_opfc1_enlbd                         0x40  // Enable Low Battery Detect. When this bit is set to 1 the Low Battery Detector circuit and threshold comparison will be enabled.
 121 #define RFM22_opfc1_swres                         0x80  // Software Register Reset Bit. This bit may be used to reset all registers simultaneously to a DEFAULT state, without the need for sequentially writing to each individual register. The RESET is accomplished by setting swres = 1. This bit will be automatically cleared.
 122
 123 #define RFM22_op_and_func_ctrl2                   0x08  // R/W
 124 #define RFM22_opfc2_ffclrtx                       0x01  // TX FIFO Reset/Clear. This has to be a two writes operation: Setting ffclrtx =1 followed by ffclrtx = 0 will clear the contents of the TX FIFO.
 125 #define RFM22_opfc2_ffclrrx                       0x02  // RX FIFO Reset/Clear. This has to be a two writes operation: Setting ffclrrx =1 followed by ffclrrx = 0 will clear the contents of the RX FIFO.
 126 #define RFM22_opfc2_enldm                         0x04  // Enable Low Duty Cycle Mode. If this bit is set to 1 then the chip turns on the RX regularly. The frequency should be set in the Wake-Up Timer Period register, while the minimum ON time should be set in the Low-Duty Cycle Mode Duration register. The FIFO mode should be enabled also.
 127 #define RFM22_opfc2_autotx                        0x08  // Automatic Transmission. When autotx = 1 the transceiver will enter automatically TX State when the FIFO is almost full. When the FIFO is empty it will automatically return to the Idle State.
 128 #define RFM22_opfc2_rxmpk                         0x10  // RX Multi Packet. When the chip is selected to use FIFO Mode (dtmod[1:0]) and RX Packet Handling (enpacrx) then it will fill up the FIFO with multiple valid packets if this bit is set, otherwise the transceiver will automatically leave the RX State after the first valid packet has been received.
 129 #define RFM22_opfc2_antdiv_mask                   0xE0  // Enable Antenna Diversity. The GPIO must be configured for Antenna Diversity for the algorithm to work properly.
 130
 131 #define RFM22_xtal_osc_load_cap                   0x09  // R/W
 132 #define RFM22_xolc_xlc_mask                       0x7F  // Tuning Capacitance for the 30 MHz XTAL.
 133 #define RFM22_xolc_xtalshft                       0x80  // Additional capacitance to course shift the frequency if xlc[6:0] is not sufficient. Not binary with xlc[6:0].
 134
 135 #define RFM22_cpu_output_clk                      0x0A  // R/W
 136 #define RFM22_coc_30MHz                           0x00
 137 #define RFM22_coc_15MHz                           0x01
 138 #define RFM22_coc_10MHz                           0x02
 139 #define RFM22_coc_4MHz                            0x03
 140 #define RFM22_coc_3MHz                            0x04
 141 #define RFM22_coc_2MHz                            0x05
 142 #define RFM22_coc_1MHz                            0x06
 143 #define RFM22_coc_32768Hz                         0x07
 144 #define RFM22_coc_enlfc                           0x08
 145 #define RFM22_coc_0cycle                          0x00
 146 #define RFM22_coc_128cycles                       0x10
 147 #define RFM22_coc_256cycles                       0x20
 148 #define RFM22_coc_512cycles                       0x30
 149
 150 #define RFM22_gpio0_config                        0x0B  // R/W
 151 #define RFM22_gpio0_config_por                    0x00  // Power-On-Reset (output)
 152 #define RFM22_gpio0_config_wut                    0x01  // Wake-Up Timer: 1 when WUT has expired (output)
 153 #define RFM22_gpio0_config_lbd                    0x02  // Low Battery Detect: 1 when battery is below threshold setting (output)
 154 #define RFM22_gpio0_config_ddi                    0x03  // Direct Digital Input
 155 #define RFM22_gpio0_config_eife                   0x04  // External Interrupt, falling edge (input)
 156 #define RFM22_gpio0_config_eire                   0x05  // External Interrupt, rising edge (input)
 157 #define RFM22_gpio0_config_eisc                   0x06  // External Interrupt, state change (input)
 158 #define RFM22_gpio0_config_ai                     0x07  // ADC Analog Input
 159 #define RFM22_gpio0_config_atni                   0x08  // Reserved (Analog Test N Input)
 160 #define RFM22_gpio0_config_atpi                   0x09  // Reserved (Analog Test P Input)
 161 #define RFM22_gpio0_config_ddo                    0x0A  // Direct Digital Output
 162 #define RFM22_gpio0_config_dto                    0x0B  // Reserved (Digital Test Output)
 163 #define RFM22_gpio0_config_atno                   0x0C  // Reserved (Analog Test N Output)
 164 #define RFM22_gpio0_config_atpo                   0x0D  // Reserved (Analog Test P Output)
 165 #define RFM22_gpio0_config_rv                     0xOE  // Reference Voltage (output)
 166 #define RFM22_gpio0_config_dclk                   0x0F  // TX/RX Data CLK output to be used in conjunction with TX/RX Data pin (output)
 167 #define RFM22_gpio0_config_txd                    0x10  // TX Data input for direct modulation (input)
 168 #define RFM22_gpio0_config_err                    0x11  // External Retransmission Request (input)
 169 #define RFM22_gpio0_config_txstate                0x12  // TX State (output)
 170 #define RFM22_gpio0_config_txfifoaf               0x13  // TX FIFO Almost Full (output)
 171 #define RFM22_gpio0_config_rxd                    0x14  // RX Data (output)
 172 #define RFM22_gpio0_config_rxstate                0x15  // RX State (output)
 173 #define RFM22_gpio0_config_rxfifoaf               0x16  // RX FIFO Almost Full (output)
 174 #define RFM22_gpio0_config_antswt1                0x17  // Antenna 1 Switch used for antenna diversity (output)
 175 #define RFM22_gpio0_config_antswt2                0x18  // Antenna 2 Switch used for antenna diversity (output)
 176 #define RFM22_gpio0_config_vpd                    0x19  // Valid Preamble Detected (output)
 177 #define RFM22_gpio0_config_ipd                    0x1A  // Invalid Preamble Detected (output)
 178 #define RFM22_gpio0_config_swd                    0x1B  // Sync Word Detected (output)
 179 #define RFM22_gpio0_config_cca                    0x1C  // Clear Channel Assessment (output)
 180 #define RFM22_gpio0_config_vdd                    0x1D  // VDD
 181 #define RFM22_gpio0_config_pup                    0x20
 182 #define RFM22_gpio0_config_drv0                   0x00  // output drive level
 183 #define RFM22_gpio0_config_drv1                   0x40  // output drive level
 184 #define RFM22_gpio0_config_drv2                   0x80  // output drive level
 185 #define RFM22_gpio0_config_drv3                   0xC0  // output drive level
 186
 187 #define RFM22_gpio1_config                        0x0C  // R/W
 188 #define RFM22_gpio1_config_ipor                   0x00  // Inverted Power-On-Reset (output)
 189 #define RFM22_gpio1_config_wut                    0x01  // Wake-Up Timer: 1 when WUT has expired (output)
 190 #define RFM22_gpio1_config_lbd                    0x02  // Low Battery Detect: 1 when battery is below threshold setting (output)
 191 #define RFM22_gpio1_config_ddi                    0x03  // Direct Digital Input
 192 #define RFM22_gpio1_config_eife                   0x04  // External Interrupt, falling edge (input)
 193 #define RFM22_gpio1_config_eire                   0x05  // External Interrupt, rising edge (input)
 194 #define RFM22_gpio1_config_eisc                   0x06  // External Interrupt, state change (input)
 195 #define RFM22_gpio1_config_ai                     0x07  // ADC Analog Input
 196 #define RFM22_gpio1_config_atni                   0x08  // Reserved (Analog Test N Input)
 197 #define RFM22_gpio1_config_atpi                   0x09  // Reserved (Analog Test P Input)
 198 #define RFM22_gpio1_config_ddo                    0x0A  // Direct Digital Output
 199 #define RFM22_gpio1_config_dto                    0x0B  // Reserved (Digital Test Output)
 200 #define RFM22_gpio1_config_atno                   0x0C  // Reserved (Analog Test N Output)
 201 #define RFM22_gpio1_config_atpo                   0x0D  // Reserved (Analog Test P Output)
 202 #define RFM22_gpio1_config_rv                     0xOE  // Reference Voltage (output)
 203 #define RFM22_gpio1_config_dclk                   0x0F  // TX/RX Data CLK output to be used in conjunction with TX/RX Data pin (output)
 204 #define RFM22_gpio1_config_txd                    0x10  // TX Data input for direct modulation (input)
 205 #define RFM22_gpio1_config_err                    0x11  // External Retransmission Request (input)
 206 #define RFM22_gpio1_config_txstate                0x12  // TX State (output)
 207 #define RFM22_gpio1_config_txfifoaf               0x13  // TX FIFO Almost Full (output)
 208 #define RFM22_gpio1_config_rxd                    0x14  // RX Data (output)
 209 #define RFM22_gpio1_config_rxstate                0x15  // RX State (output)
 210 #define RFM22_gpio1_config_rxfifoaf               0x16  // RX FIFO Almost Full (output)
 211 #define RFM22_gpio1_config_antswt1                0x17  // Antenna 1 Switch used for antenna diversity (output)
 212 #define RFM22_gpio1_config_antswt2                0x18  // Antenna 2 Switch used for antenna diversity (output)
 213 #define RFM22_gpio1_config_vpd                    0x19  // Valid Preamble Detected (output)
 214 #define RFM22_gpio1_config_ipd                    0x1A  // Invalid Preamble Detected (output)
 215 #define RFM22_gpio1_config_swd                    0x1B  // Sync Word Detected (output)
 216 #define RFM22_gpio1_config_cca                    0x1C  // Clear Channel Assessment (output)
 217 #define RFM22_gpio1_config_vdd                    0x1D  // VDD
 218 #define RFM22_gpio1_config_pup                    0x20
 219 #define RFM22_gpio1_config_drv0                   0x00  // output drive level
 220 #define RFM22_gpio1_config_drv1                   0x40  // output drive level
 221 #define RFM22_gpio1_config_drv2                   0x80  // output drive level
 222 #define RFM22_gpio1_config_drv3                   0xC0  // output drive level
 223
 224 #define RFM22_gpio2_config                        0x0D  // R/W
 225 #define RFM22_gpio2_config_mc                     0x00  // Microcontroller Clock (output)
 226 #define RFM22_gpio2_config_wut                    0x01  // Wake-Up Timer: 1 when WUT has expired (output)
 227 #define RFM22_gpio2_config_lbd                    0x02  // Low Battery Detect: 1 when battery is below threshold setting (output)
 228 #define RFM22_gpio2_config_ddi                    0x03  // Direct Digital Input
 229 #define RFM22_gpio2_config_eife                   0x04  // External Interrupt, falling edge (input)
 230 #define RFM22_gpio2_config_eire                   0x05  // External Interrupt, rising edge (input)
 231 #define RFM22_gpio2_config_eisc                   0x06  // External Interrupt, state change (input)
 232 #define RFM22_gpio2_config_ai                     0x07  // ADC Analog Input
 233 #define RFM22_gpio2_config_atni                   0x08  // Reserved (Analog Test N Input)
 234 #define RFM22_gpio2_config_atpi                   0x09  // Reserved (Analog Test P Input)
 235 #define RFM22_gpio2_config_ddo                    0x0A  // Direct Digital Output
 236 #define RFM22_gpio2_config_dto                    0x0B  // Reserved (Digital Test Output)
 237 #define RFM22_gpio2_config_atno                   0x0C  // Reserved (Analog Test N Output)
 238 #define RFM22_gpio2_config_atpo                   0x0D  // Reserved (Analog Test P Output)
 239 #define RFM22_gpio2_config_rv                     0xOE  // Reference Voltage (output)
 240 #define RFM22_gpio2_config_dclk                   0x0F  // TX/RX Data CLK output to be used in conjunction with TX/RX Data pin (output)
 241 #define RFM22_gpio2_config_txd                    0x10  // TX Data input for direct modulation (input)
 242 #define RFM22_gpio2_config_err                    0x11  // External Retransmission Request (input)
 243 #define RFM22_gpio2_config_txstate                0x12  // TX State (output)
 244 #define RFM22_gpio2_config_txfifoaf               0x13  // TX FIFO Almost Full (output)
 245 #define RFM22_gpio2_config_rxd                    0x14  // RX Data (output)
 246 #define RFM22_gpio2_config_rxstate                0x15  // RX State (output)
 247 #define RFM22_gpio2_config_rxfifoaf               0x16  // RX FIFO Almost Full (output)
 248 #define RFM22_gpio2_config_antswt1                0x17  // Antenna 1 Switch used for antenna diversity (output)
 249 #define RFM22_gpio2_config_antswt2                0x18  // Antenna 2 Switch used for antenna diversity (output)
 250 #define RFM22_gpio2_config_vpd                    0x19  // Valid Preamble Detected (output)
 251 #define RFM22_gpio2_config_ipd                    0x1A  // Invalid Preamble Detected (output)
 252 #define RFM22_gpio2_config_swd                    0x1B  // Sync Word Detected (output)
 253 #define RFM22_gpio2_config_cca                    0x1C  // Clear Channel Assessment (output)
 254 #define RFM22_gpio2_config_vdd                    0x1D  // VDD
 255 #define RFM22_gpio2_config_pup                    0x20
 256 #define RFM22_gpio2_config_drv0                   0x00  // output drive level
 257 #define RFM22_gpio2_config_drv1                   0x40  // output drive level
 258 #define RFM22_gpio2_config_drv2                   0x80  // output drive level
 259 #define RFM22_gpio2_config_drv3                   0xC0  // output drive level
 260
 261 #define RFM22_io_port_config                      0x0E  // R/W
 262 #define RFM22_io_port_extitst2                    0x40  // External Interrupt Status. If the GPIO2 is programmed to be external interrupt sources then the status can be read here.
 263 #define RFM22_io_port_extitst1                    0x20  // External Interrupt Status. If the GPIO1 is programmed to be external interrupt sources then the status can be read here.
 264 #define RFM22_io_port_extitst0                    0x10  // External Interrupt Status. If the GPIO0 is programmed to be external interrupt sources then the status can be read here.
 265 #define RFM22_io_port_itsdo                       0x08  // Interrupt Request Output on the SDO Pin. nIRQ output is present on the SDO pin if this bit is set and the nSEL input is inactive (high).
 266 #define RFM22_io_port_dio2                        0x04  // Direct I/O for GPIO2. If the GPIO2 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO2 is configured to be a direct input then the value of the pin can be read here.
 267 #define RFM22_io_port_dio1                        0x02  // Direct I/O for GPIO1. If the GPIO1 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO1 is configured to be a direct input then the value of the pin can be read here.
 268 #define RFM22_io_port_dio0                        0x01  // Direct I/O for GPIO0. If the GPIO0 is configured to be a direct output then the value on the GPIO pin can be set here. If the GPIO0 is configured to be a direct input then the value of the pin can be read here.
 269 #define RFM22_io_port_default                     0x00  // GPIO pins are default
 270
 271 #define RFM22_adc_config                          0x0F  // R/W
 272 #define RFM22_ac_adcgain0                         0x00
 273 #define RFM22_ac_adcgain1                         0x01
 274 #define RFM22_ac_adcgain2                         0x02
 275 #define RFM22_ac_adcgain3                         0x03
 276 #define RFM22_ac_adcref_bg                        0x00
 277 #define RFM22_ac_adcref_vdd3                      0x08
 278 #define RFM22_ac_adcref_vdd2                      0x0C
 279 #define RFM22_ac_adcsel_temp_sensor               0x00
 280 #define RFM22_ac_adcsel_gpio0                     0x10
 281 #define RFM22_ac_adcsel_gpio1                     0x20
 282 #define RFM22_ac_adcsel_gpio2                     0x30
 283 #define RFM22_ac_adcsel_gpio01                    0x40
 284 #define RFM22_ac_adcsel_gpio12                    0x50
 285 #define RFM22_ac_adcsel_gpio02                    0x60
 286 #define RFM22_ac_adcsel_gpio_gnd                  0x70
 287 #define RFM22_ac_adcstartbusy                     0x80
 288
 289 #define RFM22_adc_sensor_amp_offset               0x10  // R/W
 290 #define RFM22_asao_adcoffs_mask                   0x0F  // ADC Sensor Amplifier Offset. The offset can be calculated as Offset = adcoffs[2:0] x VDD/1000; MSB = adcoffs[3] = Sign bit.
 291
 292 #define RFM22_adc_value                           0x11  // R .. Internal 8 bit ADC Output Value.
 293
 294 #define RFM22_temp_sensor_calib                   0x12  // R/W
 295 #define RFM22_tsc_tstrim_mask                     0x0F  // Temperature Sensor Trim Value.
 296 #define RFM22_tsc_entstrim                        0x10  // Temperature Sensor Trim Enable.
 297 #define RFM22_tsc_entsoffs                        0x20  // Temperature Sensor Offset to Convert from K to C.
 298 #define RFM22_tsc_tsrange0                        0x00  // Temperature Sensor Range Selection. -40C to +64C 0.5C resolution
 299 #define RFM22_tsc_tsrange1                        0x40  // -40 to +85C with 1.0C resolution
 300 #define RFM22_tsc_tsrange2                        0x80  // 0C to 85C with 0.5C resolution
 301 #define RFM22_tsc_tsrange3                        0xC0  // -40F to 216F with 1.0F resolution
 302
 303 #define RFM22_temp_value_offset                   0x13  // R/W
 304
 305 #define RFM22_wakeup_timer_period1                0x14  // R/W
 306 #define RFM22_wakeup_timer_period2                0x15  // R/W
 307 #define RFM22_wakeup_timer_period3                0x16  // R/W
 308
 309 #define RFM22_wakeup_timer_value1                 0x17  // R
 310 #define RFM22_wakeup_timer_value2                 0x18  // R
 311
 312 #define RFM22_low_dutycycle_mode_duration         0x19  // R/W
 313 #define RFM22_low_battery_detector_threshold      0x1A  // R/W
 314
 315 #define RFM22_battery_volateg_level               0x1B  // R
 316
 317 #define RFM22_if_filter_bandwidth                 0x1C  // R/W
 318 #define RFM22_iffbw_filset_mask                   0x0F
 319 #define RFM22_iffbw_ndec_exp_mask                 0x70
 320 #define RFM22_iffbw_dwn3_bypass                   0x80
 321
 322 #define RFM22_afc_loop_gearshift_override         0x1D  // R/W
 323 #define RFM22_afc_lp_gs_ovrd_afcgearl_mask        0x07  // AFC Low Gear Setting.
 324 #define RFM22_afc_lp_gs_ovrd_afcgearh_mask        0x38  // AFC High Gear Setting.
 325 #define RFM22_afc_lp_gs_ovrd_enafc                0x40  // AFC Enable.
 326 #define RFM22_afc_lp_gs_ovrd_afcbd                0x80  // If set, the tolerated AFC frequency error will be halved.
 327
 328 #define RFM22_afc_timing_control                  0x1E  // R/W
 329
 330 #define RFM22_clk_recovery_gearshift_override     0x1F  // R/W
 331 #define RFM22_clk_recovery_oversampling_ratio     0x20  // R/W
 332 #define RFM22_clk_recovery_offset2                0x21  // R/W
 333 #define RFM22_clk_recovery_offset1                0x22  // R/W
 334 #define RFM22_clk_recovery_offset0                0x23  // R/W
 335 #define RFM22_clk_recovery_timing_loop_gain1      0x24  // R/W
 336 #define RFM22_clk_recovery_timing_loop_gain0      0x25  // R/W
 337
 338 #define RFM22_rssi                                0x26  // R
 339 #define RFM22_rssi_threshold_clear_chan_indicator 0x27 // R/W
 340
 341 #define RFM22_antenna_diversity_register1         0x28  // R
 342 #define RFM22_antenna_diversity_register2         0x29  // R
 343
 344 #define RFM22_afc_limiter                         0x2A  // R/W .. AFC_pull_in_range = �AFCLimiter[7:0] x (hbsel+1) x 625 Hz
 345
 346 #define RFM22_afc_correction_read                 0x2B  // R
 347
 348 #define RFM22_ook_counter_value1                  0x2C  // R/W
 349 #define RFM22_ook_counter_value2                  0x2D  // R/W
 350
 351 #define RFM22_slicer_peak_hold                    0x2E  // R/W
 352
 353 #define RFM22_data_access_control                 0x30  // R/W
 354 #define RFM22_dac_crc_ccitt                       0x00  //
 355 #define RFM22_dac_crc_crc16                       0x01  //
 356 #define RFM22_dac_crc_iec16                       0x02  //
 357 #define RFM22_dac_crc_biacheva                    0x03  //
 358 #define RFM22_dac_encrc                           0x04  // CRC Enable. Cyclic Redundancy Check generation is enabled if this bit is set.
 359 #define RFM22_dac_enpactx                         0x08  // Enable Packet TX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled. Setting enpactx = 1 will enable automatic packet handling in the TX path. Register 30�4D allow for various configurations of the packet structure. Setting enpactx = 0 will not do any packet handling in the TX path. It will only transmit what is loaded to the FIFO.
 360 #define RFM22_dac_skip2ph                         0x10  // Skip 2nd Phase of Preamble Detection. If set, we skip the second phase of the preamble detection (under certain conditions) if antenna diversity is enabled.
 361 #define RFM22_dac_crcdonly                        0x20  // CRC Data Only Enable. When this bit is set to 1 the CRC is calculated on and checked against the packet data fields only.
 362 #define RFM22_dac_lsbfrst                         0x40  // LSB First Enable. The LSB of the data will be transmitted/received first if this bit is set.
 363 #define RFM22_dac_enpacrx                         0x80  // Enable Packet RX Handling. If FIFO Mode (dtmod = 10) is being used automatic packet handling may be enabled. Setting enpacrx = 1 will enable automatic packet handling in the RX path. Register 30�4D allow for various configurations of the packet structure. Setting enpacrx = 0 will not do any packet handling in the RX path. It will only receive everything after the sync word and fill up the RX FIFO.
 364
 365 #define RFM22_ezmac_status                        0x31  // R
 366 #define RFM22_ezmac_status_pksent                 0x01  // Packet Sent. A 1 a packet has been sent by the radio. (Same bit as in register 03, but reading it does not reset the IRQ)
 367 #define RFM22_ezmac_status_pktx                   0x02  // Packet Transmitting. When 1 the radio is currently transmitting a packet.
 368 #define RFM22_ezmac_status_crcerror               0x04  // CRC Error. When 1 a Cyclic Redundancy Check error has been detected. (Same bit as in register 03, but reading it does not reset the IRQ)
 369 #define RFM22_ezmac_status_pkvalid                0x08  // Valid Packet Received. When a 1 a valid packet has been received by the receiver. (Same bit as in register 03, but reading it does not reset the IRQ)
 370 #define RFM22_ezmac_status_pkrx                   0x10  // Packet Receiving. When 1 the radio is currently receiving a valid packet.
 371 #define RFM22_ezmac_status_pksrch                 0x20  // Packet Searching. When 1 the radio is searching for a valid packet.
 372 #define RFM22_ezmac_status_rxcrc1                 0x40  // If high, it indicates the last CRC received is all one�s. May indicated Transmitter underflow in case of CRC error.
 373
 374 #define RFM22_header_control1                     0x32  // R/W
 375 #define RFM22_header_cntl1_bcen_none              0x00  // No broadcast address enable.
 376 #define RFM22_header_cntl1_bcen_0                 0x10  // Broadcast address enable for header byte 0.
 377 #define RFM22_header_cntl1_bcen_1                 0x20  // Broadcast address enable for header byte 1.
 378 #define RFM22_header_cntl1_bcen_2                 0x40  // Broadcast address enable for header byte 2.
 379 #define RFM22_header_cntl1_bcen_3                 0x80  // Broadcast address enable for header byte 3.
 380 #define RFM22_header_cntl1_hdch_none              0x00  // No Received Header check
 381 #define RFM22_header_cntl1_hdch_0                 0x01  // Received Header check for byte 0.
 382 #define RFM22_header_cntl1_hdch_1                 0x02  // Received Header check for byte 1.
 383 #define RFM22_header_cntl1_hdch_2                 0x04  // Received Header check for byte 2.
 384 #define RFM22_header_cntl1_hdch_3                 0x08  // Received Header check for byte 3.
 385
 386 #define RFM22_header_control2                     0x33  // R/W
 387 #define RFM22_header_cntl2_prealen                0x01  // MSB of Preamble Length. See register Preamble Length.
 388 #define RFM22_header_cntl2_synclen_3              0x00  // Synchronization Word 3
 389 #define RFM22_header_cntl2_synclen_32             0x02  // Synchronization Word 3 followed by 2
 390 #define RFM22_header_cntl2_synclen_321            0x04  // Synchronization Word 3 followed by 2 followed by 1
 391 #define RFM22_header_cntl2_synclen_3210           0x06  // Synchronization Word 3 followed by 2 followed by 1 followed by 0
 392 #define RFM22_header_cntl2_fixpklen               0x08  // Fix Packet Length. When fixpklen = 1 the packet length (pklen[7:0]) is not included in the header. When fixpklen = 0 the packet length is included in the header.
 393 #define RFM22_header_cntl2_hdlen_none             0x00  // no header
 394 #define RFM22_header_cntl2_hdlen_3                0x10  // header 3
 395 #define RFM22_header_cntl2_hdlen_32               0x20  // header 3 and 2
 396 #define RFM22_header_cntl2_hdlen_321              0x30  // header 3 and 2 and 1
 397 #define RFM22_header_cntl2_hdlen_3210             0x40  // header 3 and 2 and 1 and 0
 398 #define RFM22_header_cntl2_skipsyn                0x80  // If high, the system will ignore the syncword search timeout reset. The chip will not return to searching for Preamble, but instead will remain searching for Sync word.
 399
 400 #define RFM22_preamble_length                     0x34  // R/W
 401
 402 #define RFM22_preamble_detection_ctrl1            0x35  // R/W
 403 #define RFM22_pre_det_ctrl1_preath_mask           0xF8  // Number of nibbles processed during detection.
 404 #define RFM22_pre_det_ctrl1_rssi_offset_mask      0x07  // Value added as offset to RSSI calculation. Every increment in this register results in an increment of +4 dB in the RSSI.
 405
 406 #define RFM22_sync_word3                          0x36  // R/W
 407 #define RFM22_sync_word2                          0x37  // R/W
 408 #define RFM22_sync_word1                          0x38  // R/W
 409 #define RFM22_sync_word0                          0x39  // R/W
 410
 411 #define RFM22_transmit_header3                    0x3A  // R/W
 412 #define RFM22_transmit_header2                    0x3B  // R/W
 413 #define RFM22_transmit_header1                    0x3C  // R/W
 414 #define RFM22_transmit_header0                    0x3D  // R/W
 415
 416 #define RFM22_transmit_packet_length              0x3E  // R/W
 417
 418 #define RFM22_check_header3                       0x3F  // R/W
 419 #define RFM22_check_header2                       0x40  // R/W
 420 #define RFM22_check_header1                       0x41  // R/W
 421 #define RFM22_check_header0                       0x42  // R/W
 422
 423 #define RFM22_header_enable3                      0x43  // R/W
 424 #define RFM22_header_enable2                      0x44  // R/W
 425 #define RFM22_header_enable1                      0x45  // R/W
 426 #define RFM22_header_enable0                      0x46  // R/W
 427
 428 #define RFM22_received_header3                    0x47  // R
 429 #define RFM22_received_header2                    0x48  // R
 430 #define RFM22_received_header1                    0x49  // R
 431 #define RFM22_received_header0                    0x4A  // R
 432
 433 #define RFM22_received_packet_length              0x4B  // R
 434
 435 #define RFM22_adc8_control                        0x4F  // R/W
 436
 437 #define RFM22_channel_filter_coeff_addr           0x60  // R/W
 438 #define RFM22_ch_fil_coeff_ad_inv_pre_th_mask     0xF0  //
 439 #define RFM22_ch_fil_coeff_ad_chfiladd_mask       0x0F  // Channel Filter Coefficient Look-up Table Address. The address for channel filter coefficients used in the RX path.
 440
 441 #define RFM22_xtal_osc_por_ctrl                   0x62  // R/W
 442 #define RFM22_xtal_osc_por_ctrl_pwst_mask         0xE0  // Internal Power States of the Chip.
 443 #define RFM22_xtal_osc_por_ctrl_clkhyst           0x10  // Clock Hysteresis Setting.
 444 #define RFM22_xtal_osc_por_ctrl_enbias2x          0x08  // 2 Times Higher Bias Current Enable.
 445 #define RFM22_xtal_osc_por_ctrl_enamp2x           0x04  // 2 Times Higher Amplification Enable.
 446 #define RFM22_xtal_osc_por_ctrl_bufovr            0x02  // Output Buffer Enable Override.
 447 #define RFM22_xtal_osc_por_ctrl_enbuf             0x01  // Output Buffer Enable.
 448
 449 #define RFM22_agc_override1                       0x69  // R/W
 450 #define RFM22_agc_ovr1_sgi                        0x40  // AGC Loop, Set Gain Increase. If set to 0 then gain increasing will not be allowed. If set to 1 then gain increasing is allowed, default is 0.
 451 #define RFM22_agc_ovr1_agcen                      0x20  // Automatic Gain Control Enable. When this bit is set then the result of the control can be read out from bits [4:0], otherwise the gain can be controlled manually by writing into bits [4:0].
 452 #define RFM22_agc_ovr1_lnagain                    0x10  // LNA Gain Select. 0 = min gain = 5dB, 1 = max gain = 25 dB.
 453 #define RFM22_agc_ovr1_pga_mask                   0x0F  // PGA Gain Override Value.
 454
 455 #define RFM22_tx_power                            0x6D  // R/W
 456 #define RFM22_tx_pwr_lna_sw                       0x08  // LNA Switch Controller. If set, lna_sw control from the digital will go high during TX modes, and low during other times. If reset, the digital control signal is low at all times.
 457
 458 #define RFM22_tx_data_rate1                       0x6E  // R/W
 459 #define RFM22_tx_data_rate0                       0x6F  // R/W
 460
 461 #define RFM22_modulation_mode_control1            0x70  // R/W
 462 #define RFM22_mmc1_enwhite                        0x01  // Data Whitening is Enabled if this bit is set.
 463 #define RFM22_mmc1_enmanch                        0x02  // Manchester Coding is Enabled if this bit is set.
 464 #define RFM22_mmc1_enmaninv                       0x04  // Manchester Data Inversion is Enabled if this bit is set.
 465 #define RFM22_mmc1_manppol                        0x08  // Manchester Preamble Polarity (will transmit a series of 1 if set, or series of 0 if reset).
 466 #define RFM22_mmc1_enphpwdn                       0x10  // If set, the Packet Handler will be powered down when chip is in low power mode.
 467 #define RFM22_mmc1_txdtrtscale                    0x20  // This bit should be set for Data Rates below 30 kbps.
 468
 469 #define RFM22_modulation_mode_control2            0x71  // R/W
 470 #define RFM22_mmc2_modtyp_mask                    0x03  // Modulation type.
 471 #define RFM22_mmc2_modtyp_none                    0x00  //
 472 #define RFM22_mmc2_modtyp_ook                     0x01  //
 473 #define RFM22_mmc2_modtyp_fsk                     0x02  //
 474 #define RFM22_mmc2_modtyp_gfsk                    0x03  //
 475 #define RFM22_mmc2_fd                             0x04  // MSB of Frequency Deviation Setting, see "Register 72h. Frequency Deviation".
 476 #define RFM22_mmc2_eninv                          0x08  // Invert TX and RX Data.
 477 #define RFM22_mmc2_dtmod_mask                     0x30  // Modulation source.
 478 #define RFM22_mmc2_dtmod_dm_gpio                  0x00  //
 479 #define RFM22_mmc2_dtmod_dm_sdi                   0x10  //
 480 #define RFM22_mmc2_dtmod_fifo                     0x20  //
 481 #define RFM22_mmc2_dtmod_pn9                      0x30  //
 482 #define RFM22_mmc2_trclk_mask                     0xC0  // TX Data Clock Configuration.
 483 #define RFM22_mmc2_trclk_clk_none                 0x00  //
 484 #define RFM22_mmc2_trclk_clk_gpio                 0x40  //
 485 #define RFM22_mmc2_trclk_clk_sdo                  0x80  //
 486 #define RFM22_mmc2_trclk_clk_nirq                 0xC0  //
 487
 488 #define RFM22_frequency_deviation                 0x72  // R/W
 489
 490 #define RFM22_frequency_offset1                   0x73  // R/W
 491 #define RFM22_frequency_offset2                   0x74  // R/W
 492
 493 #define RFM22_frequency_band_select               0x75  // R/W
 494 #define RFM22_fb_mask                             0x1F
 495 #define RFM22_fbs_hbsel                           0x20
 496 #define RFM22_fbs_sbse                            0x40
 497
 498 #define RFM22_nominal_carrier_frequency1          0x76  // R/W
 499 #define RFM22_nominal_carrier_frequency0          0x77  // R/W
 500
 501 #define RFM22_frequency_hopping_channel_select    0x79  // R/W
 502 #define RFM22_frequency_hopping_step_size         0x7A  // R/W
 503
 504 #define RFM22_tx_fifo_control1                    0x7C  // R/W .. TX FIFO Almost Full Threshold (0 - 63)
 505 #define RFM22_tx_fifo_control1_mask               0x3F
 506
 507 #define RFM22_tx_fifo_control2                    0x7D  // R/W .. TX FIFO Almost Empty Threshold (0 - 63)
 508 #define RFM22_tx_fifo_control2_mask               0x3F
 509
 510 #define RFM22_rx_fifo_control                     0x7E  // R/W .. RX FIFO Almost Full Threshold (0 - 63)
 511 #define RFM22_rx_fifo_control_mask                0x3F
 512
 513 #define RFM22_fifo_access                         0x7F  // R/W
 514
 515
 516 #endif /* PIOS_RFM22B_REGS_H */
 517
 518 /**
 519  * @}
 520  * @}
 521  */