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Merged in f5soh/librepilot/update_credits (pull request #529)
[librepilot.git] / flight / pios / common / libraries / CMSIS / Include / core_sc300.h
blobcc34d6fc0eee62d3b7f71e7a014417876c4fc277
1 /**************************************************************************//**
2 * @file core_sc300.h
3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
4 * @version V3.20
5 * @date 25. February 2013
6 *
7 * @note
8 *
9 ******************************************************************************/
10 /* Copyright (c) 2009 - 2013 ARM LIMITED
11
12 All rights reserved.
13 Redistribution and use in source and binary forms, with or without
14 modification, are permitted provided that the following conditions are met:
15 - Redistributions of source code must retain the above copyright
16 notice, this list of conditions and the following disclaimer.
17 - Redistributions in binary form must reproduce the above copyright
18 notice, this list of conditions and the following disclaimer in the
19 documentation and/or other materials provided with the distribution.
20 - Neither the name of ARM nor the names of its contributors may be used
21 to endorse or promote products derived from this software without
22 specific prior written permission.
23 *
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 POSSIBILITY OF SUCH DAMAGE.
35 ---------------------------------------------------------------------------*/
36
37
38 #if defined ( __ICCARM__ )
39 #pragma system_include /* treat file as system include file for MISRA check */
40 #endif
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 #ifndef __CORE_SC300_H_GENERIC
47 #define __CORE_SC300_H_GENERIC
48
49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
50 CMSIS violates the following MISRA-C:2004 rules:
51
52 \li Required Rule 8.5, object/function definition in header file.<br>
53 Function definitions in header files are used to allow 'inlining'.
54
55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
56 Unions are used for effective representation of core registers.
57
58 \li Advisory Rule 19.7, Function-like macro defined.<br>
59 Function-like macros are used to allow more efficient code.
60 */
61
62
63 /*******************************************************************************
64 * CMSIS definitions
65 ******************************************************************************/
66 /** \ingroup SC3000
67 @{
68 */
69
70 /* CMSIS SC300 definitions */
71 #define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
72 #define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
75
76 #define __CORTEX_SC (300) /*!< Cortex secure core */
77
78
79 #if defined ( __CC_ARM )
80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
82 #define __STATIC_INLINE static __inline
83
84 #elif defined ( __ICCARM__ )
85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
87 #define __STATIC_INLINE static inline
88
89 #elif defined ( __GNUC__ )
90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
92 #define __STATIC_INLINE static inline
93
94 #elif defined ( __TASKING__ )
95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
97 #define __STATIC_INLINE static inline
98
99 #endif
100
101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
102 */
103 #define __FPU_USED 0
104
105 #if defined ( __CC_ARM )
106 #if defined __TARGET_FPU_VFP
107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108 #endif
109
110 #elif defined ( __ICCARM__ )
111 #if defined __ARMVFP__
112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
113 #endif
114
115 #elif defined ( __GNUC__ )
116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
118 #endif
119
120 #elif defined ( __TASKING__ )
121 #if defined __FPU_VFP__
122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
123 #endif
124 #endif
125
126 #include <stdint.h> /* standard types definitions */
127 #include <core_cmInstr.h> /* Core Instruction Access */
128 #include <core_cmFunc.h> /* Core Function Access */
129
130 #endif /* __CORE_SC300_H_GENERIC */
131
132 #ifndef __CMSIS_GENERIC
133
134 #ifndef __CORE_SC300_H_DEPENDANT
135 #define __CORE_SC300_H_DEPENDANT
136
137 /* check device defines and use defaults */
138 #if defined __CHECK_DEVICE_DEFINES
139 #ifndef __SC300_REV
140 #define __SC300_REV 0x0000
141 #warning "__SC300_REV not defined in device header file; using default!"
142 #endif
143
144 #ifndef __MPU_PRESENT
145 #define __MPU_PRESENT 0
146 #warning "__MPU_PRESENT not defined in device header file; using default!"
147 #endif
148
149 #ifndef __NVIC_PRIO_BITS
150 #define __NVIC_PRIO_BITS 4
151 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
152 #endif
153
154 #ifndef __Vendor_SysTickConfig
155 #define __Vendor_SysTickConfig 0
156 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
157 #endif
158 #endif
159
160 /* IO definitions (access restrictions to peripheral registers) */
161 /**
162 \defgroup CMSIS_glob_defs CMSIS Global Defines
163
164 <strong>IO Type Qualifiers</strong> are used
165 \li to specify the access to peripheral variables.
166 \li for automatic generation of peripheral register debug information.
167 */
168 #ifdef __cplusplus
169 #define __I volatile /*!< Defines 'read only' permissions */
170 #else
171 #define __I volatile const /*!< Defines 'read only' permissions */
172 #endif
173 #define __O volatile /*!< Defines 'write only' permissions */
174 #define __IO volatile /*!< Defines 'read / write' permissions */
175
176 /*@} end of group SC300 */
177
178
179
180 /*******************************************************************************
181 * Register Abstraction
182 Core Register contain:
183 - Core Register
184 - Core NVIC Register
185 - Core SCB Register
186 - Core SysTick Register
187 - Core Debug Register
188 - Core MPU Register
189 ******************************************************************************/
190 /** \defgroup CMSIS_core_register Defines and Type Definitions
191 \brief Type definitions and defines for Cortex-M processor based devices.
192 */
193
194 /** \ingroup CMSIS_core_register
195 \defgroup CMSIS_CORE Status and Control Registers
196 \brief Core Register type definitions.
197 @{
198 */
199
200 /** \brief Union type to access the Application Program Status Register (APSR).
201 */
202 typedef union
203 {
204 struct
205 {
206 #if (__CORTEX_M != 0x04)
207 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
208 #else
209 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
210 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
211 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
212 #endif
213 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
214 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
215 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
216 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
217 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
218 } b; /*!< Structure used for bit access */
219 uint32_t w; /*!< Type used for word access */
220 } APSR_Type;
221
222
223 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
224 */
225 typedef union
226 {
227 struct
228 {
229 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
230 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
231 } b; /*!< Structure used for bit access */
232 uint32_t w; /*!< Type used for word access */
233 } IPSR_Type;
234
235
236 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
237 */
238 typedef union
239 {
240 struct
241 {
242 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
243 #if (__CORTEX_M != 0x04)
244 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
245 #else
246 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
247 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
248 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
249 #endif
250 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
251 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
252 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
253 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
254 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
255 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
256 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
257 } b; /*!< Structure used for bit access */
258 uint32_t w; /*!< Type used for word access */
259 } xPSR_Type;
260
261
262 /** \brief Union type to access the Control Registers (CONTROL).
263 */
264 typedef union
265 {
266 struct
267 {
268 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
269 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
270 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
271 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
272 } b; /*!< Structure used for bit access */
273 uint32_t w; /*!< Type used for word access */
274 } CONTROL_Type;
275
276 /*@} end of group CMSIS_CORE */
277
278
279 /** \ingroup CMSIS_core_register
280 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
281 \brief Type definitions for the NVIC Registers
282 @{
283 */
284
285 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
286 */
287 typedef struct
288 {
289 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
290 uint32_t RESERVED0[24];
291 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
292 uint32_t RSERVED1[24];
293 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
294 uint32_t RESERVED2[24];
295 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
296 uint32_t RESERVED3[24];
297 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
298 uint32_t RESERVED4[56];
299 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
300 uint32_t RESERVED5[644];
301 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
302 } NVIC_Type;
303
304 /* Software Triggered Interrupt Register Definitions */
305 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
306 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
307
308 /*@} end of group CMSIS_NVIC */
309
310
311 /** \ingroup CMSIS_core_register
312 \defgroup CMSIS_SCB System Control Block (SCB)
313 \brief Type definitions for the System Control Block Registers
314 @{
315 */
316
317 /** \brief Structure type to access the System Control Block (SCB).
318 */
319 typedef struct
320 {
321 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
322 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
323 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
324 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
325 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
326 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
327 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
328 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
329 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
330 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
331 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
332 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
333 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
334 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
335 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
336 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
337 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
338 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
339 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
340 uint32_t RESERVED0[5];
341 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
342 } SCB_Type;
343
344 /* SCB CPUID Register Definitions */
345 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
346 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
347
348 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
349 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
350
351 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
352 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
353
354 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
355 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
356
357 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
358 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
359
360 /* SCB Interrupt Control State Register Definitions */
361 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
362 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
363
364 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
365 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
366
367 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
368 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
369
370 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
371 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
372
373 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
374 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
375
376 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
377 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
378
379 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
380 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
381
382 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
383 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
384
385 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
386 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
387
388 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
389 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
390
391 /* SCB Vector Table Offset Register Definitions */
392 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
393 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
394
395 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
396 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
397
398 /* SCB Application Interrupt and Reset Control Register Definitions */
399 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
400 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
401
402 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
403 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
404
405 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
406 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
407
408 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
409 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
410
411 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
412 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
413
414 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
415 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
416
417 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
418 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
419
420 /* SCB System Control Register Definitions */
421 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
422 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
423
424 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
425 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
426
427 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
428 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
429
430 /* SCB Configuration Control Register Definitions */
431 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
432 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
433
434 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
435 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
436
437 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
438 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
439
440 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
441 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
442
443 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
444 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
445
446 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
447 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
448
449 /* SCB System Handler Control and State Register Definitions */
450 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
451 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
452
453 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
454 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
455
456 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
457 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
458
459 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
460 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
461
462 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
463 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
464
465 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
466 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
467
468 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
469 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
470
471 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
472 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
473
474 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
475 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
476
477 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
478 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
479
480 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
481 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
482
483 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
484 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
485
486 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
487 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
488
489 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
490 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
491
492 /* SCB Configurable Fault Status Registers Definitions */
493 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
494 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
495
496 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
497 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
498
499 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
500 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
501
502 /* SCB Hard Fault Status Registers Definitions */
503 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
504 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
505
506 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
507 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
508
509 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
510 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
511
512 /* SCB Debug Fault Status Register Definitions */
513 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
514 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
515
516 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
517 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
518
519 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
520 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
521
522 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
523 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
524
525 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
526 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
527
528 /*@} end of group CMSIS_SCB */
529
530
531 /** \ingroup CMSIS_core_register
532 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
533 \brief Type definitions for the System Control and ID Register not in the SCB
534 @{
535 */
536
537 /** \brief Structure type to access the System Control and ID Register not in the SCB.
538 */
539 typedef struct
540 {
541 uint32_t RESERVED0[1];
542 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
543 uint32_t RESERVED1[1];
544 } SCnSCB_Type;
545
546 /* Interrupt Controller Type Register Definitions */
547 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
548 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
549
550 /*@} end of group CMSIS_SCnotSCB */
551
552
553 /** \ingroup CMSIS_core_register
554 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
555 \brief Type definitions for the System Timer Registers.
556 @{
557 */
558
559 /** \brief Structure type to access the System Timer (SysTick).
560 */
561 typedef struct
562 {
563 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
564 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
565 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
566 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
567 } SysTick_Type;
568
569 /* SysTick Control / Status Register Definitions */
570 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
571 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
572
573 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
574 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
575
576 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
577 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
578
579 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
580 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
581
582 /* SysTick Reload Register Definitions */
583 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
584 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
585
586 /* SysTick Current Register Definitions */
587 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
588 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
589
590 /* SysTick Calibration Register Definitions */
591 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
592 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
593
594 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
595 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
596
597 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
598 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
599
600 /*@} end of group CMSIS_SysTick */
601
602
603 /** \ingroup CMSIS_core_register
604 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
605 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
606 @{
607 */
608
609 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
610 */
611 typedef struct
612 {
613 __O union
614 {
615 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
616 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
617 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
618 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
619 uint32_t RESERVED0[864];
620 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
621 uint32_t RESERVED1[15];
622 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
623 uint32_t RESERVED2[15];
624 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
625 uint32_t RESERVED3[29];
626 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
627 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
628 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
629 uint32_t RESERVED4[43];
630 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
631 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
632 uint32_t RESERVED5[6];
633 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
634 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
635 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
636 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
637 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
638 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
639 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
640 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
641 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
642 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
643 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
644 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
645 } ITM_Type;
646
647 /* ITM Trace Privilege Register Definitions */
648 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
649 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
650
651 /* ITM Trace Control Register Definitions */
652 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
653 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
654
655 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
656 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
657
658 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
659 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
660
661 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
662 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
663
664 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
665 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
666
667 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
668 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
669
670 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
671 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
672
673 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
674 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
675
676 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
677 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
678
679 /* ITM Integration Write Register Definitions */
680 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
681 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
682
683 /* ITM Integration Read Register Definitions */
684 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
685 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
686
687 /* ITM Integration Mode Control Register Definitions */
688 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
689 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
690
691 /* ITM Lock Status Register Definitions */
692 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
693 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
694
695 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
696 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
697
698 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
699 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
700
701 /*@}*/ /* end of group CMSIS_ITM */
702
703
704 /** \ingroup CMSIS_core_register
705 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
706 \brief Type definitions for the Data Watchpoint and Trace (DWT)
707 @{
708 */
709
710 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
711 */
712 typedef struct
713 {
714 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
715 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
716 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
717 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
718 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
719 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
720 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
721 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
722 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
723 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
724 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
725 uint32_t RESERVED0[1];
726 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
727 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
728 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
729 uint32_t RESERVED1[1];
730 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
731 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
732 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
733 uint32_t RESERVED2[1];
734 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
735 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
736 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
737 } DWT_Type;
738
739 /* DWT Control Register Definitions */
740 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
741 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
742
743 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
744 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
745
746 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
747 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
748
749 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
750 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
751
752 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
753 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
754
755 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
756 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
757
758 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
759 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
760
761 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
762 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
763
764 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
765 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
766
767 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
768 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
769
770 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
771 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
772
773 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
774 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
775
776 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
777 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
778
779 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
780 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
781
782 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
783 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
784
785 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
786 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
787
788 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
789 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
790
791 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
792 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
793
794 /* DWT CPI Count Register Definitions */
795 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
796 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
797
798 /* DWT Exception Overhead Count Register Definitions */
799 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
800 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
801
802 /* DWT Sleep Count Register Definitions */
803 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
804 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
805
806 /* DWT LSU Count Register Definitions */
807 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
808 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
809
810 /* DWT Folded-instruction Count Register Definitions */
811 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
812 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
813
814 /* DWT Comparator Mask Register Definitions */
815 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
816 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
817
818 /* DWT Comparator Function Register Definitions */
819 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
820 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
821
822 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
823 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
824
825 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
826 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
827
828 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
829 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
830
831 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
832 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
833
834 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
835 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
836
837 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
838 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
839
840 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
841 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
842
843 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
844 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
845
846 /*@}*/ /* end of group CMSIS_DWT */
847
848
849 /** \ingroup CMSIS_core_register
850 \defgroup CMSIS_TPI Trace Port Interface (TPI)
851 \brief Type definitions for the Trace Port Interface (TPI)
852 @{
853 */
854
855 /** \brief Structure type to access the Trace Port Interface Register (TPI).
856 */
857 typedef struct
858 {
859 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
860 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
861 uint32_t RESERVED0[2];
862 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
863 uint32_t RESERVED1[55];
864 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
865 uint32_t RESERVED2[131];
866 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
867 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
868 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
869 uint32_t RESERVED3[759];
870 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
871 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
872 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
873 uint32_t RESERVED4[1];
874 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
875 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
876 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
877 uint32_t RESERVED5[39];
878 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
879 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
880 uint32_t RESERVED7[8];
881 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
882 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
883 } TPI_Type;
884
885 /* TPI Asynchronous Clock Prescaler Register Definitions */
886 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
887 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
888
889 /* TPI Selected Pin Protocol Register Definitions */
890 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
891 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
892
893 /* TPI Formatter and Flush Status Register Definitions */
894 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
895 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
896
897 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
898 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
899
900 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
901 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
902
903 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
904 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
905
906 /* TPI Formatter and Flush Control Register Definitions */
907 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
908 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
909
910 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
911 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
912
913 /* TPI TRIGGER Register Definitions */
914 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
915 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
916
917 /* TPI Integration ETM Data Register Definitions (FIFO0) */
918 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
919 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
920
921 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
922 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
923
924 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
925 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
926
927 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
928 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
929
930 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
931 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
932
933 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
934 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
935
936 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
937 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
938
939 /* TPI ITATBCTR2 Register Definitions */
940 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
941 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
942
943 /* TPI Integration ITM Data Register Definitions (FIFO1) */
944 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
945 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
946
947 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
948 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
949
950 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
951 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
952
953 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
954 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
955
956 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
957 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
958
959 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
960 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
961
962 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
963 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
964
965 /* TPI ITATBCTR0 Register Definitions */
966 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
967 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
968
969 /* TPI Integration Mode Control Register Definitions */
970 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
971 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
972
973 /* TPI DEVID Register Definitions */
974 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
975 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
976
977 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
978 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
979
980 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
981 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
982
983 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
984 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
985
986 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
987 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
988
989 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
990 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
991
992 /* TPI DEVTYPE Register Definitions */
993 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
994 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
995
996 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
997 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
998
999 /*@}*/ /* end of group CMSIS_TPI */
1000
1001
1002 #if (__MPU_PRESENT == 1)
1003 /** \ingroup CMSIS_core_register
1004 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1005 \brief Type definitions for the Memory Protection Unit (MPU)
1006 @{
1007 */
1008
1009 /** \brief Structure type to access the Memory Protection Unit (MPU).
1010 */
1011 typedef struct
1012 {
1013 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1014 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1015 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
1016 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1017 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
1018 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
1019 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
1020 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
1021 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
1022 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
1023 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
1024 } MPU_Type;
1025
1026 /* MPU Type Register */
1027 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
1028 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1029
1030 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
1031 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1032
1033 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
1034 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
1035
1036 /* MPU Control Register */
1037 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
1038 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1039
1040 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
1041 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1042
1043 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
1044 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
1045
1046 /* MPU Region Number Register */
1047 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
1048 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
1049
1050 /* MPU Region Base Address Register */
1051 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
1052 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
1053
1054 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
1055 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
1056
1057 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
1058 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
1059
1060 /* MPU Region Attribute and Size Register */
1061 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
1062 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
1063
1064 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
1065 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
1066
1067 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
1068 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
1069
1070 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
1071 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
1072
1073 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
1074 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
1075
1076 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
1077 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
1078
1079 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
1080 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
1081
1082 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
1083 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
1084
1085 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
1086 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
1087
1088 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
1089 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
1090
1091 /*@} end of group CMSIS_MPU */
1092 #endif
1093
1094
1095 /** \ingroup CMSIS_core_register
1096 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1097 \brief Type definitions for the Core Debug Registers
1098 @{
1099 */
1100
1101 /** \brief Structure type to access the Core Debug Register (CoreDebug).
1102 */
1103 typedef struct
1104 {
1105 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1106 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1107 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1108 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1109 } CoreDebug_Type;
1110
1111 /* Debug Halting Control and Status Register */
1112 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
1113 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
1114
1115 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
1116 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
1117
1118 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
1119 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
1120
1121 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
1122 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
1123
1124 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
1125 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
1126
1127 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
1128 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
1129
1130 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
1131 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
1132
1133 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
1134 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
1135
1136 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
1137 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
1138
1139 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
1140 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
1141
1142 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
1143 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
1144
1145 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
1146 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
1147
1148 /* Debug Core Register Selector Register */
1149 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
1150 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
1151
1152 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
1153 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
1154
1155 /* Debug Exception and Monitor Control Register */
1156 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
1157 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
1158
1159 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
1160 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
1161
1162 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
1163 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
1164
1165 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
1166 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
1167
1168 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
1169 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
1170
1171 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
1172 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
1173
1174 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
1175 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
1176
1177 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
1178 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
1179
1180 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
1181 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
1182
1183 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
1184 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
1185
1186 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
1187 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
1188
1189 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
1190 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
1191
1192 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
1193 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
1194
1195 /*@} end of group CMSIS_CoreDebug */
1196
1197
1198 /** \ingroup CMSIS_core_register
1199 \defgroup CMSIS_core_base Core Definitions
1200 \brief Definitions for base addresses, unions, and structures.
1201 @{
1202 */
1203
1204 /* Memory mapping of Cortex-M3 Hardware */
1205 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1206 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
1207 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1208 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1209 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
1210 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1211 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1212 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1213
1214 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
1215 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1216 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1217 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1218 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
1219 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1220 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1221 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
1222
1223 #if (__MPU_PRESENT == 1)
1224 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1225 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1226 #endif
1227
1228 /*@} */
1229
1230
1231
1232 /*******************************************************************************
1233 * Hardware Abstraction Layer
1234 Core Function Interface contains:
1235 - Core NVIC Functions
1236 - Core SysTick Functions
1237 - Core Debug Functions
1238 - Core Register Access Functions
1239 ******************************************************************************/
1240 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1241 */
1242
1243
1244
1245 /* ########################## NVIC functions #################################### */
1246 /** \ingroup CMSIS_Core_FunctionInterface
1247 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1248 \brief Functions that manage interrupts and exceptions via the NVIC.
1249 @{
1250 */
1251
1252 /** \brief Set Priority Grouping
1253
1254 The function sets the priority grouping field using the required unlock sequence.
1255 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
1256 Only values from 0..7 are used.
1257 In case of a conflict between priority grouping and available
1258 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1259
1260 \param [in] PriorityGroup Priority grouping field.
1261 */
1262 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
1263 {
1264 uint32_t reg_value;
1265 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
1266
1267 reg_value = SCB->AIRCR; /* read old register configuration */
1268 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
1269 reg_value = (reg_value |
1270 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1271 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
1272 SCB->AIRCR = reg_value;
1273 }
1274
1275
1276 /** \brief Get Priority Grouping
1277
1278 The function reads the priority grouping field from the NVIC Interrupt Controller.
1279
1280 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
1281 */
1282 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
1283 {
1284 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
1285 }
1286
1287
1288 /** \brief Enable External Interrupt
1289
1290 The function enables a device-specific interrupt in the NVIC interrupt controller.
1291
1292 \param [in] IRQn External interrupt number. Value cannot be negative.
1293 */
1294 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
1295 {
1296 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
1297 }
1298
1299
1300 /** \brief Disable External Interrupt
1301
1302 The function disables a device-specific interrupt in the NVIC interrupt controller.
1303
1304 \param [in] IRQn External interrupt number. Value cannot be negative.
1305 */
1306 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
1307 {
1308 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
1309 }
1310
1311
1312 /** \brief Get Pending Interrupt
1313
1314 The function reads the pending register in the NVIC and returns the pending bit
1315 for the specified interrupt.
1316
1317 \param [in] IRQn Interrupt number.
1318
1319 \return 0 Interrupt status is not pending.
1320 \return 1 Interrupt status is pending.
1321 */
1322 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
1323 {
1324 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
1325 }
1326
1327
1328 /** \brief Set Pending Interrupt
1329
1330 The function sets the pending bit of an external interrupt.
1331
1332 \param [in] IRQn Interrupt number. Value cannot be negative.
1333 */
1334 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
1335 {
1336 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
1337 }
1338
1339
1340 /** \brief Clear Pending Interrupt
1341
1342 The function clears the pending bit of an external interrupt.
1343
1344 \param [in] IRQn External interrupt number. Value cannot be negative.
1345 */
1346 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1347 {
1348 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
1349 }
1350
1351
1352 /** \brief Get Active Interrupt
1353
1354 The function reads the active register in NVIC and returns the active bit.
1355
1356 \param [in] IRQn Interrupt number.
1357
1358 \return 0 Interrupt status is not active.
1359 \return 1 Interrupt status is active.
1360 */
1361 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
1362 {
1363 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
1364 }
1365
1366
1367 /** \brief Set Interrupt Priority
1368
1369 The function sets the priority of an interrupt.
1370
1371 \note The priority cannot be set for every core interrupt.
1372
1373 \param [in] IRQn Interrupt number.
1374 \param [in] priority Priority to set.
1375 */
1376 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1377 {
1378 if(IRQn < 0) {
1379 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
1380 else {
1381 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
1382 }
1383
1384
1385 /** \brief Get Interrupt Priority
1386
1387 The function reads the priority of an interrupt. The interrupt
1388 number can be positive to specify an external (device specific)
1389 interrupt, or negative to specify an internal (core) interrupt.
1390
1391
1392 \param [in] IRQn Interrupt number.
1393 \return Interrupt Priority. Value is aligned automatically to the implemented
1394 priority bits of the microcontroller.
1395 */
1396 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
1397 {
1398
1399 if(IRQn < 0) {
1400 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
1401 else {
1402 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
1403 }
1404
1405
1406 /** \brief Encode Priority
1407
1408 The function encodes the priority for an interrupt with the given priority group,
1409 preemptive priority value, and subpriority value.
1410 In case of a conflict between priority grouping and available
1411 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
1412
1413 \param [in] PriorityGroup Used priority group.
1414 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1415 \param [in] SubPriority Subpriority value (starting from 0).
1416 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1417 */
1418 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1419 {
1420 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1421 uint32_t PreemptPriorityBits;
1422 uint32_t SubPriorityBits;
1423
1424 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1425 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1426
1427 return (
1428 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
1429 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
1430 );
1431 }
1432
1433
1434 /** \brief Decode Priority
1435
1436 The function decodes an interrupt priority value with a given priority group to
1437 preemptive priority value and subpriority value.
1438 In case of a conflict between priority grouping and available
1439 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
1440
1441 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1442 \param [in] PriorityGroup Used priority group.
1443 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1444 \param [out] pSubPriority Subpriority value (starting from 0).
1445 */
1446 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
1447 {
1448 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
1449 uint32_t PreemptPriorityBits;
1450 uint32_t SubPriorityBits;
1451
1452 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
1453 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
1454
1455 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
1456 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
1457 }
1458
1459
1460 /** \brief System Reset
1461
1462 The function initiates a system reset request to reset the MCU.
1463 */
1464 __STATIC_INLINE void NVIC_SystemReset(void)
1465 {
1466 __DSB(); /* Ensure all outstanding memory accesses included
1467 buffered write are completed before reset */
1468 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
1469 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
1470 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
1471 __DSB(); /* Ensure completion of memory access */
1472 while(1); /* wait until reset */
1473 }
1474
1475 /*@} end of CMSIS_Core_NVICFunctions */
1476
1477
1478
1479 /* ################################## SysTick function ############################################ */
1480 /** \ingroup CMSIS_Core_FunctionInterface
1481 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
1482 \brief Functions that configure the System.
1483 @{
1484 */
1485
1486 #if (__Vendor_SysTickConfig == 0)
1487
1488 /** \brief System Tick Configuration
1489
1490 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
1491 Counter is in free running mode to generate periodic interrupts.
1492
1493 \param [in] ticks Number of ticks between two interrupts.
1494
1495 \return 0 Function succeeded.
1496 \return 1 Function failed.
1497
1498 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
1499 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
1500 must contain a vendor-specific implementation of this function.
1501
1502 */
1503 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
1504 {
1505 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
1506
1507 SysTick->LOAD = ticks - 1; /* set reload register */
1508 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
1509 SysTick->VAL = 0; /* Load the SysTick Counter Value */
1510 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
1511 SysTick_CTRL_TICKINT_Msk |
1512 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
1513 return (0); /* Function successful */
1514 }
1515
1516 #endif
1517
1518 /*@} end of CMSIS_Core_SysTickFunctions */
1519
1520
1521
1522 /* ##################################### Debug In/Output function ########################################### */
1523 /** \ingroup CMSIS_Core_FunctionInterface
1524 \defgroup CMSIS_core_DebugFunctions ITM Functions
1525 \brief Functions that access the ITM debug interface.
1526 @{
1527 */
1528
1529 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
1530 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
1531
1532
1533 /** \brief ITM Send Character
1534
1535 The function transmits a character via the ITM channel 0, and
1536 \li Just returns when no debugger is connected that has booked the output.
1537 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
1538
1539 \param [in] ch Character to transmit.
1540
1541 \returns Character to transmit.
1542 */
1543 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
1544 {
1545 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
1546 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
1547 {
1548 while (ITM->PORT[0].u32 == 0);
1549 ITM->PORT[0].u8 = (uint8_t) ch;
1550 }
1551 return (ch);
1552 }
1553
1554
1555 /** \brief ITM Receive Character
1556
1557 The function inputs a character via the external variable \ref ITM_RxBuffer.
1558
1559 \return Received character.
1560 \return -1 No character pending.
1561 */
1562 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
1563 int32_t ch = -1; /* no character available */
1564
1565 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
1566 ch = ITM_RxBuffer;
1567 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
1568 }
1569
1570 return (ch);
1571 }
1572
1573
1574 /** \brief ITM Check Character
1575
1576 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
1577
1578 \return 0 No character available.
1579 \return 1 Character available.
1580 */
1581 __STATIC_INLINE int32_t ITM_CheckChar (void) {
1582
1583 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
1584 return (0); /* no character available */
1585 } else {
1586 return (1); /* character available */
1587 }
1588 }
1589
1590 /*@} end of CMSIS_core_DebugFunctions */
1591
1592 #endif /* __CORE_SC300_H_DEPENDANT */
1593
1594 #endif /* __CMSIS_GENERIC */
1595
1596 #ifdef __cplusplus
1597 }
1598 #endif