flight/pios/stm32f30x/pios_spi.c

   1 /**
   2  ******************************************************************************
   3  * @addtogroup PIOS PIOS Core hardware abstraction layer
   4  * @{
   5  * @addtogroup   PIOS_SPI SPI Functions
   6  * @brief PIOS interface to read and write from SPI ports
   7  * @{
   8  *
   9  * @file       pios_spi.c
  10  * @author     The OpenPilot Team, http://www.openpilot.org Copyright (C) 2012.
  11  * @brief      Hardware Abstraction Layer for SPI ports of STM32
  12  * @see        The GNU Public License (GPL) Version 3
  13  * @notes
  14  *
  15  * Note that additional chip select lines can be easily added by using
  16  * the remaining free GPIOs of the core module. Shared SPI ports should be
  17  * arbitrated with (FreeRTOS based) Mutexes to avoid collisions!
  18  *
  19  *****************************************************************************/
  20 /*
  21  * This program is free software; you can redistribute it and/or modify
  22  * it under the terms of the GNU General Public License as published by
  23  * the Free Software Foundation; either version 3 of the License, or
  24  * (at your option) any later version.
  25  *
  26  * This program is distributed in the hope that it will be useful, but
  27  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  28  * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  29  * for more details.
  30  *
  31  * You should have received a copy of the GNU General Public License along
  32  * with this program; if not, write to the Free Software Foundation, Inc.,
  33  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  34  */
  35
  36 #include <pios.h>
  37
  38 #ifdef PIOS_INCLUDE_SPI
  39
  40 #include <pios_spi_priv.h>
  41
  42 #define SPI_MAX_BLOCK_PIO 12800
  43
  44 static bool PIOS_SPI_validate(__attribute__((unused)) struct pios_spi_dev *com_dev)
  45 {
  46     /* Should check device magic here */
  47     return true;
  48 }
  49
  50 #if defined(PIOS_INCLUDE_FREERTOS)
  51 static struct pios_spi_dev *PIOS_SPI_alloc(void)
  52 {
  53     return pios_malloc(sizeof(struct pios_spi_dev));
  54 }
  55 #else
  56 static struct pios_spi_dev pios_spi_devs[PIOS_SPI_MAX_DEVS];
  57 static uint8_t pios_spi_num_devs;
  58 static struct pios_spi_dev *PIOS_SPI_alloc(void)
  59 {
  60     if (pios_spi_num_devs >= PIOS_SPI_MAX_DEVS) {
  61         return NULL;
  62     }
  63
  64     return &pios_spi_devs[pios_spi_num_devs++];
  65 }
  66 #endif
  67
  68 /**
  69  * Initialises SPI pins
  70  * \param[in] mode currently only mode 0 supported
  71  * \return < 0 if initialisation failed
  72  */
  73 int32_t PIOS_SPI_Init(uint32_t *spi_id, const struct pios_spi_cfg *cfg)
  74 {
  75     uint32_t init_ssel = 0;
  76
  77     PIOS_Assert(spi_id);
  78     PIOS_Assert(cfg);
  79
  80     struct pios_spi_dev *spi_dev;
  81
  82     spi_dev = (struct pios_spi_dev *)PIOS_SPI_alloc();
  83     if (!spi_dev) {
  84         goto out_fail;
  85     }
  86
  87     /* Bind the configuration to the device instance */
  88     spi_dev->cfg = cfg;
  89
  90 #if defined(PIOS_INCLUDE_FREERTOS)
  91     vSemaphoreCreateBinary(spi_dev->busy);
  92     xSemaphoreGive(spi_dev->busy);
  93 #else
  94     spi_dev->busy = 0;
  95 #endif
  96
  97     /* Disable callback function */
  98     spi_dev->callback = NULL;
  99
 100     /* Set rx/tx dummy bytes to a known value */
 101     spi_dev->rx_dummy_byte = 0xFF;
 102     spi_dev->tx_dummy_byte = 0xFF;
 103
 104     switch (spi_dev->cfg->init.SPI_NSS) {
 105     case SPI_NSS_Soft:
 106         if (spi_dev->cfg->init.SPI_Mode == SPI_Mode_Master) {
 107             /* We're a master in soft NSS mode, make sure we see NSS high at all times. */
 108             SPI_NSSInternalSoftwareConfig(spi_dev->cfg->regs, SPI_NSSInternalSoft_Set);
 109             /* Init as many slave selects as the config advertises. */
 110             init_ssel = spi_dev->cfg->slave_count;
 111         } else {
 112             /* We're a slave in soft NSS mode, make sure we see NSS low at all times. */
 113             SPI_NSSInternalSoftwareConfig(spi_dev->cfg->regs, SPI_NSSInternalSoft_Reset);
 114         }
 115         break;
 116     case SPI_NSS_Hard:
 117         /* only legal for single-slave config */
 118         PIOS_Assert(spi_dev->cfg->slave_count == 1);
 119         init_ssel = 1;
 120         /* FIXME: Should this also call SPI_SSOutputCmd()? */
 121         break;
 122
 123     default:
 124         PIOS_Assert(0);
 125     }
 126
 127     /* Initialize the GPIO pins */
 128     /* note __builtin_ctz() due to the difference between GPIO_PinX and GPIO_PinSourceX */
 129     if (spi_dev->cfg->remap) {
 130         GPIO_PinAFConfig(spi_dev->cfg->sclk.gpio,
 131                          __builtin_ctz(spi_dev->cfg->sclk.init.GPIO_Pin),
 132                          spi_dev->cfg->remap);
 133         GPIO_PinAFConfig(spi_dev->cfg->mosi.gpio,
 134                          __builtin_ctz(spi_dev->cfg->mosi.init.GPIO_Pin),
 135                          spi_dev->cfg->remap);
 136         GPIO_PinAFConfig(spi_dev->cfg->miso.gpio,
 137                          __builtin_ctz(spi_dev->cfg->miso.init.GPIO_Pin),
 138                          spi_dev->cfg->remap);
 139         for (uint32_t i = 0; i < init_ssel; i++) {
 140             GPIO_PinAFConfig(spi_dev->cfg->ssel[i].gpio,
 141                              __builtin_ctz(spi_dev->cfg->ssel[i].init.GPIO_Pin),
 142                              spi_dev->cfg->remap);
 143         }
 144     }
 145
 146     /* Initialize the GPIO pins */
 147     GPIO_Init(spi_dev->cfg->sclk.gpio, (GPIO_InitTypeDef *)&(spi_dev->cfg->sclk.init));
 148     GPIO_Init(spi_dev->cfg->mosi.gpio, (GPIO_InitTypeDef *)&(spi_dev->cfg->mosi.init));
 149     GPIO_Init(spi_dev->cfg->miso.gpio, (GPIO_InitTypeDef *)&(spi_dev->cfg->miso.init));
 150     for (uint32_t i = 0; i < init_ssel; i++) {
 151         /* Since we're driving the SSEL pin in software, ensure that the slave is deselected */
 152         /* XXX multi-slave support - maybe have another SPI_NSS_ mode? */
 153         GPIO_SetBits(spi_dev->cfg->ssel[i].gpio, spi_dev->cfg->ssel[i].init.GPIO_Pin);
 154         GPIO_Init(spi_dev->cfg->ssel[i].gpio, (GPIO_InitTypeDef *)&(spi_dev->cfg->ssel[i].init));
 155     }
 156
 157     /* Enable the associated peripheral clock */
 158     switch ((uint32_t)spi_dev->cfg->regs) {
 159     case (uint32_t)SPI1:
 160         /* Enable SPI peripheral clock (APB2 == high speed) */
 161         RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
 162         break;
 163     case (uint32_t)SPI2:
 164         /* Enable SPI peripheral clock (APB1 == slow speed) */
 165         RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
 166         break;
 167     case (uint32_t)SPI3:
 168         /* Enable SPI peripheral clock (APB1 == slow speed) */
 169         RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
 170         break;
 171     }
 172
 173     bool use_dma = spi_dev->cfg->dma.rx.channel && spi_dev->cfg->dma.tx.channel;
 174
 175     /* Enable DMA clock */
 176     if (use_dma) {
 177         RCC_AHBPeriphClockCmd(spi_dev->cfg->dma.ahb_clk, ENABLE);
 178
 179         /* Configure DMA for SPI Rx */
 180         DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
 181         DMA_Init(spi_dev->cfg->dma.rx.channel, (DMA_InitTypeDef *)&(spi_dev->cfg->dma.rx.init));
 182
 183         /* Configure DMA for SPI Tx */
 184         DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
 185         DMA_Init(spi_dev->cfg->dma.tx.channel, (DMA_InitTypeDef *)&(spi_dev->cfg->dma.tx.init));
 186     }
 187
 188     /* Initialize the SPI block */
 189     SPI_I2S_DeInit(spi_dev->cfg->regs);
 190     SPI_Init(spi_dev->cfg->regs, (SPI_InitTypeDef *)&(spi_dev->cfg->init));
 191
 192     /* Configure CRC calculation */
 193     if (spi_dev->cfg->use_crc) {
 194         SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
 195     } else {
 196         SPI_CalculateCRC(spi_dev->cfg->regs, DISABLE);
 197     }
 198
 199     /* Configure the RX FIFO Threshold -- 8 bits */
 200     SPI_RxFIFOThresholdConfig(spi_dev->cfg->regs, SPI_RxFIFOThreshold_QF);
 201
 202     /* Enable SPI */
 203     SPI_Cmd(spi_dev->cfg->regs, ENABLE);
 204
 205     /* Enable SPI interrupts to DMA */
 206     if (use_dma) {
 207         SPI_I2S_DMACmd(spi_dev->cfg->regs, SPI_I2S_DMAReq_Tx | SPI_I2S_DMAReq_Rx, ENABLE);
 208     }
 209
 210     /* Configure DMA interrupt */
 211     NVIC_Init((NVIC_InitTypeDef *)&(spi_dev->cfg->dma.irq.init));
 212
 213     *spi_id = (uint32_t)spi_dev;
 214     return 0;
 215
 216 out_fail:
 217     return -1;
 218 }
 219
 220 /**
 221  * (Re-)initialises SPI peripheral clock rate
 222  *
 223  * \param[in] spi SPI number (0 or 1)
 224  * \param[in] spi_prescaler configures the SPI speed:
 225  * <UL>
 226  *   <LI>PIOS_SPI_PRESCALER_2: sets clock rate 27.7~ nS @ 72 MHz (36 MBit/s) (only supported for spi==0, spi1 uses 4 instead)
 227  *   <LI>PIOS_SPI_PRESCALER_4: sets clock rate 55.5~ nS @ 72 MHz (18 MBit/s)
 228  *   <LI>PIOS_SPI_PRESCALER_8: sets clock rate 111.1~ nS @ 72 MHz (9 MBit/s)
 229  *   <LI>PIOS_SPI_PRESCALER_16: sets clock rate 222.2~ nS @ 72 MHz (4.5 MBit/s)
 230  *   <LI>PIOS_SPI_PRESCALER_32: sets clock rate 444.4~ nS @ 72 MHz (2.25 MBit/s)
 231  *   <LI>PIOS_SPI_PRESCALER_64: sets clock rate 888.8~ nS @ 72 MHz (1.125 MBit/s)
 232  *   <LI>PIOS_SPI_PRESCALER_128: sets clock rate 1.7~ nS @ 72 MHz (0.562 MBit/s)
 233  *   <LI>PIOS_SPI_PRESCALER_256: sets clock rate 3.5~ nS @ 72 MHz (0.281 MBit/s)
 234  * </UL>
 235  * \return 0 if no error
 236  * \return -1 if disabled SPI port selected
 237  * \return -3 if invalid spi_prescaler selected
 238  */
 239 int32_t PIOS_SPI_SetClockSpeed(uint32_t spi_id, SPIPrescalerTypeDef spi_prescaler)
 240 {
 241     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 242
 243     bool valid = PIOS_SPI_validate(spi_dev);
 244
 245     PIOS_Assert(valid)
 246
 247     SPI_InitTypeDef SPI_InitStructure;
 248
 249     if (spi_prescaler >= 8) {
 250         /* Invalid prescaler selected */
 251         return -3;
 252     }
 253
 254     /* Start with a copy of the default configuration for the peripheral */
 255     SPI_InitStructure = spi_dev->cfg->init;
 256
 257     /* Adjust the prescaler for the peripheral's clock */
 258     SPI_InitStructure.SPI_BaudRatePrescaler = ((uint16_t)spi_prescaler & 7) << 3;
 259
 260     /* Write back the new configuration */
 261     SPI_Init(spi_dev->cfg->regs, &SPI_InitStructure);
 262
 263     PIOS_SPI_TransferByte(spi_id, 0xFF);
 264     return 0;
 265 }
 266
 267 /**
 268  * Claim the SPI bus semaphore.  Calling the SPI functions does not require this
 269  * \param[in] spi SPI number (0 or 1)
 270  * \return 0 if no error
 271  * \return -1 if timeout before claiming semaphore
 272  */
 273 int32_t PIOS_SPI_ClaimBus(uint32_t spi_id)
 274 {
 275 #if defined(PIOS_INCLUDE_FREERTOS)
 276     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 277
 278     bool valid = PIOS_SPI_validate(spi_dev);
 279     PIOS_Assert(valid)
 280
 281     if (xSemaphoreTake(spi_dev->busy, 0xffff) != pdTRUE) {
 282         return -1;
 283     }
 284 #else
 285     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 286     uint32_t timeout = 0xffff;
 287     while ((PIOS_SPI_Busy(spi_id) || spi_dev->busy) && --timeout) {
 288         ;
 289     }
 290     if (timeout == 0) { // timed out
 291         return -1;
 292     }
 293
 294     PIOS_IRQ_Disable();
 295     if (spi_dev->busy) {
 296         return -1;
 297     }
 298     spi_dev->busy = 1;
 299     PIOS_IRQ_Enable();
 300 #endif /* if defined(PIOS_INCLUDE_FREERTOS) */
 301     return 0;
 302 }
 303
 304 /**
 305  * Claim the SPI bus semaphore from an ISR.  Has no timeout.
 306  * \param[in] spi SPI number (0 or 1)
 307  * \param woken[in,out] If non-NULL, will be set to true if woken was false and a higher priority
 308  *                      task has is now eligible to run, else unchanged
 309  * \return 0 if no error
 310  * \return -1 if timeout before claiming semaphore
 311  */
 312 int32_t PIOS_SPI_ClaimBusISR(uint32_t spi_id, bool *woken)
 313 {
 314 #if defined(PIOS_INCLUDE_FREERTOS)
 315     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 316     signed portBASE_TYPE higherPriorityTaskWoken = pdFALSE;
 317
 318     bool valid = PIOS_SPI_validate(spi_dev);
 319     PIOS_Assert(valid)
 320
 321     if (xSemaphoreTakeFromISR(spi_dev->busy, &higherPriorityTaskWoken) != pdTRUE) {
 322         return -1;
 323     }
 324     if (woken) {
 325         *woken = *woken || (higherPriorityTaskWoken == pdTRUE);
 326     }
 327     return 0;
 328
 329 #else
 330     if (woken) {
 331         *woken = false;
 332     }
 333     return PIOS_SPI_ClaimBus(spi_id);
 334
 335 #endif
 336 }
 337
 338 /**
 339  * Release the SPI bus semaphore.  Calling the SPI functions does not require this
 340  * \param[in] spi SPI number (0 or 1)
 341  * \return 0 if no error
 342  */
 343 int32_t PIOS_SPI_ReleaseBus(uint32_t spi_id)
 344 {
 345 #if defined(PIOS_INCLUDE_FREERTOS)
 346     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 347
 348     bool valid = PIOS_SPI_validate(spi_dev);
 349     PIOS_Assert(valid)
 350
 351     xSemaphoreGive(spi_dev->busy);
 352 #else
 353     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 354     PIOS_IRQ_Disable();
 355     spi_dev->busy = 0;
 356     PIOS_IRQ_Enable();
 357 #endif
 358     return 0;
 359 }
 360
 361 /**
 362  * Release the SPI bus semaphore from ISR.  Calling the SPI functions does not require this
 363  * \param[in] spi SPI number (0 or 1)
 364  * \param woken[in,out] If non-NULL, will be set to true if woken was false and a higher priority
 365  *                      task has is now eligible to run, else unchanged
 366  * \return 0 if no error
 367  */
 368 int32_t PIOS_SPI_ReleaseBusISR(uint32_t spi_id, bool *woken)
 369 {
 370 #if defined(PIOS_INCLUDE_FREERTOS)
 371     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 372     signed portBASE_TYPE higherPriorityTaskWoken = pdFALSE;
 373
 374     bool valid = PIOS_SPI_validate(spi_dev);
 375     PIOS_Assert(valid)
 376
 377     xSemaphoreGiveFromISR(spi_dev->busy, &higherPriorityTaskWoken);
 378     if (woken) {
 379         *woken = *woken || (higherPriorityTaskWoken == pdTRUE);
 380     }
 381     return 0;
 382
 383 #else
 384     if (woken) {
 385         *woken = false;
 386     }
 387     return PIOS_SPI_ReleaseBus(spi_id);
 388
 389 #endif
 390 }
 391
 392
 393 /**
 394  * Controls the RC (Register Clock alias Chip Select) pin of a SPI port
 395  * \param[in] spi SPI number (0 or 1)
 396  * \param[in] pin_value 0 or 1
 397  * \return 0 if no error
 398  */
 399 int32_t PIOS_SPI_RC_PinSet(uint32_t spi_id, uint32_t slave_id, uint8_t pin_value)
 400 {
 401     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 402
 403     bool valid = PIOS_SPI_validate(spi_dev);
 404
 405     PIOS_Assert(valid)
 406     PIOS_Assert(slave_id <= spi_dev->cfg->slave_count)
 407
 408     /* XXX multi-slave support? */
 409     if (pin_value) {
 410         GPIO_SetBits(spi_dev->cfg->ssel[slave_id].gpio, spi_dev->cfg->ssel[slave_id].init.GPIO_Pin);
 411     } else {
 412         GPIO_ResetBits(spi_dev->cfg->ssel[slave_id].gpio, spi_dev->cfg->ssel[slave_id].init.GPIO_Pin);
 413     }
 414
 415     return 0;
 416 }
 417
 418 /**
 419  * Transfers a byte to SPI output and reads back the return value from SPI input
 420  * \param[in] spi SPI number (0 or 1)
 421  * \param[in] b the byte which should be transfered
 422  */
 423 int32_t PIOS_SPI_TransferByte(uint32_t spi_id, uint8_t b)
 424 {
 425     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 426
 427     bool valid = PIOS_SPI_validate(spi_dev);
 428
 429     PIOS_Assert(valid)
 430
 431     uint8_t rx_byte;
 432
 433     /* Make sure the RXNE flag is cleared by reading the DR register */
 434     SPI_ReceiveData8(spi_dev->cfg->regs);
 435
 436     /* Wait until the TXE goes high */
 437     while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE) == RESET) {
 438         ;
 439     }
 440
 441     /* Start the transfer */
 442     SPI_SendData8(spi_dev->cfg->regs, b);
 443
 444     /* Wait until there is a byte to read */
 445     while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_RXNE) == RESET) {
 446         ;
 447     }
 448
 449     /* Read the rx'd byte */
 450     rx_byte = SPI_ReceiveData8(spi_dev->cfg->regs);
 451
 452     /* Wait until the TXE goes high */
 453     while (!(spi_dev->cfg->regs->SR & SPI_I2S_FLAG_TXE)) {
 454         ;
 455     }
 456
 457     /* Wait for SPI transfer to have fully completed */
 458     while (spi_dev->cfg->regs->SR & SPI_I2S_FLAG_BSY) {
 459         ;
 460     }
 461
 462     /* Return received byte */
 463     return rx_byte;
 464 }
 465
 466
 467 /**
 468  * Transfers a block of bytes via PIO.
 469  *
 470  * \param[in] spi_id SPI device handle
 471  * \param[in] send_buffer pointer to buffer which should be sent.<BR>
 472  * If NULL, 0xff (all-one) will be sent.
 473  * \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
 474  * If NULL, received bytes will be discarded.
 475  * \param[in] len number of bytes which should be transfered
 476  * \return >= 0 if no error during transfer
 477  * \return -1 if disabled SPI port selected
 478  */
 479 static int32_t PIOS_SPI_TransferBlock_PIO(struct pios_spi_dev *spi_dev, const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, __attribute__((unused)) void *callback)
 480 {
 481     uint8_t b;
 482
 483     while (len--) {
 484         /* get the byte to send */
 485         b = send_buffer ? *(send_buffer++) : 0xff;
 486
 487         /* Wait until the TXE goes high */
 488         while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE) == RESET) {
 489             ;
 490         }
 491
 492         /* Start the transfer */
 493         SPI_SendData8(spi_dev->cfg->regs, b);
 494
 495         /* Wait until there is a byte to read */
 496         while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_RXNE) == RESET) {
 497             ;
 498         }
 499
 500         /* Read the rx'd byte */
 501         b = SPI_ReceiveData8(spi_dev->cfg->regs);
 502
 503         /* save the received byte */
 504         if (receive_buffer) {
 505             *(receive_buffer++) = b;
 506         }
 507     }
 508
 509     /* Wait for SPI transfer to have fully completed */
 510     while (spi_dev->cfg->regs->SR & SPI_I2S_FLAG_BSY) {
 511         ;
 512     }
 513
 514     return 0;
 515 }
 516
 517
 518 /**
 519  * Transfers a block of bytes via DMA.
 520  * \param[in] spi SPI number (0 or 1)
 521  * \param[in] send_buffer pointer to buffer which should be sent.<BR>
 522  * If NULL, 0xff (all-one) will be sent.
 523  * \param[in] receive_buffer pointer to buffer which should get the received values.<BR>
 524  * If NULL, received bytes will be discarded.
 525  * \param[in] len number of bytes which should be transfered
 526  * \param[in] callback pointer to callback function which will be executed
 527  * from DMA channel interrupt once the transfer is finished.
 528  * If NULL, no callback function will be used, and PIOS_SPI_TransferBlock() will
 529  * block until the transfer is finished.
 530  * \return >= 0 if no error during transfer
 531  * \return -1 if disabled SPI port selected
 532  * \return -3 if function has been called during an ongoing DMA transfer
 533  */
 534 static int32_t PIOS_SPI_TransferBlock_DMA(struct pios_spi_dev *spi_dev, const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, void *callback)
 535 {
 536     DMA_InitTypeDef dma_init;
 537
 538     /* Exit if ongoing transfer */
 539     if (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel)) {
 540         return -3;
 541     }
 542
 543     /* Disable the SPI peripheral */
 544     SPI_Cmd(spi_dev->cfg->regs, DISABLE);
 545
 546     /* Disable the DMA channels */
 547     DMA_Cmd(spi_dev->cfg->dma.rx.channel, DISABLE);
 548     DMA_Cmd(spi_dev->cfg->dma.tx.channel, DISABLE);
 549
 550     /* Set callback function */
 551     spi_dev->callback = callback;
 552
 553     /*
 554      * Configure Rx channel
 555      */
 556
 557     /* Start with the default configuration for this peripheral */
 558     dma_init = spi_dev->cfg->dma.rx.init;
 559
 560     if (receive_buffer != NULL) {
 561         /* Enable memory addr. increment - bytes written into receive buffer */
 562         dma_init.DMA_MemoryBaseAddr = (uint32_t)receive_buffer;
 563         dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
 564     } else {
 565         /* Disable memory addr. increment - bytes written into dummy buffer */
 566         spi_dev->rx_dummy_byte = 0xFF;
 567         dma_init.DMA_MemoryBaseAddr = (uint32_t)&spi_dev->rx_dummy_byte;
 568         dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
 569     }
 570     if (spi_dev->cfg->use_crc) {
 571         /* Make sure the CRC error flag is cleared before we start */
 572         SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
 573     }
 574
 575     dma_init.DMA_BufferSize = len;
 576     DMA_Init(spi_dev->cfg->dma.rx.channel, &(dma_init));
 577
 578     /*
 579      * Configure Tx channel
 580      */
 581
 582     /* Start with the default configuration for this peripheral */
 583     dma_init = spi_dev->cfg->dma.tx.init;
 584
 585     if (send_buffer != NULL) {
 586         /* Enable memory addr. increment - bytes written into receive buffer */
 587         dma_init.DMA_MemoryBaseAddr = (uint32_t)send_buffer;
 588         dma_init.DMA_MemoryInc = DMA_MemoryInc_Enable;
 589     } else {
 590         /* Disable memory addr. increment - bytes written into dummy buffer */
 591         spi_dev->tx_dummy_byte = 0xFF;
 592         dma_init.DMA_MemoryBaseAddr = (uint32_t)&spi_dev->tx_dummy_byte;
 593         dma_init.DMA_MemoryInc = DMA_MemoryInc_Disable;
 594     }
 595
 596     if (spi_dev->cfg->use_crc) {
 597         /* The last byte of the payload will be replaced with the CRC8 */
 598         dma_init.DMA_BufferSize = len - 1;
 599     } else {
 600         dma_init.DMA_BufferSize = len;
 601     }
 602
 603     DMA_Init(spi_dev->cfg->dma.tx.channel, &(dma_init));
 604
 605     /* Enable DMA interrupt if callback function active */
 606     DMA_ITConfig(spi_dev->cfg->dma.rx.channel, DMA_IT_TC, (callback != NULL) ? ENABLE : DISABLE);
 607
 608     /* Flush out the CRC registers */
 609     SPI_CalculateCRC(spi_dev->cfg->regs, DISABLE);
 610     (void)SPI_GetCRC(spi_dev->cfg->regs, SPI_CRC_Rx);
 611     SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
 612
 613     /* Make sure to flush out the receive buffer */
 614     (void)SPI_I2S_ReceiveData16(spi_dev->cfg->regs);
 615
 616     if (spi_dev->cfg->use_crc) {
 617         /* Need a 0->1 transition to reset the CRC logic */
 618         SPI_CalculateCRC(spi_dev->cfg->regs, ENABLE);
 619     }
 620
 621     /* Start DMA transfers */
 622     DMA_Cmd(spi_dev->cfg->dma.rx.channel, ENABLE);
 623     DMA_Cmd(spi_dev->cfg->dma.tx.channel, ENABLE);
 624
 625     /* Reenable the SPI device */
 626     SPI_Cmd(spi_dev->cfg->regs, ENABLE);
 627
 628     if (callback) {
 629         /* User has requested a callback, don't wait for the transfer to complete. */
 630         return 0;
 631     }
 632
 633     /* Wait until all bytes have been transmitted/received */
 634     while (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel)) {
 635         ;
 636     }
 637
 638     /* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
 639     while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) {
 640         ;
 641     }
 642
 643     /* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
 644     while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) {
 645         ;
 646     }
 647
 648     /* Check the CRC on the transfer if enabled. */
 649     if (spi_dev->cfg->use_crc) {
 650         /* Check the SPI CRC error flag */
 651         if (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_FLAG_CRCERR)) {
 652             return -4;
 653         }
 654     }
 655
 656     /* No error */
 657     return 0;
 658 }
 659
 660 int32_t PIOS_SPI_TransferBlock(uint32_t spi_id, const uint8_t *send_buffer, uint8_t *receive_buffer, uint16_t len, void *callback)
 661 {
 662     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 663
 664     bool valid = PIOS_SPI_validate(spi_dev);
 665
 666     PIOS_Assert(valid)
 667
 668     if ((len > SPI_MAX_BLOCK_PIO) && spi_dev->cfg->dma.rx.channel && spi_dev->cfg->dma.tx.channel) {
 669         return PIOS_SPI_TransferBlock_DMA(spi_dev, send_buffer, receive_buffer, len, callback);
 670     }
 671
 672     return PIOS_SPI_TransferBlock_PIO(spi_dev, send_buffer, receive_buffer, len, callback);
 673 }
 674
 675 /**
 676  * Check if a transfer is in progress
 677  * \param[in] spi SPI number (0 or 1)
 678  * \return >= 0 if no transfer is in progress
 679  * \return -1 if disabled SPI port selected
 680  * \return -2 if unsupported SPI port selected
 681  * \return -3 if function has been called during an ongoing DMA transfer
 682  */
 683 int32_t PIOS_SPI_Busy(uint32_t spi_id)
 684 {
 685     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 686
 687     bool valid = PIOS_SPI_validate(spi_dev);
 688
 689     PIOS_Assert(valid)
 690
 691     /* DMA buffer has data or SPI transmit register not empty or SPI is busy*/
 692     if (DMA_GetCurrDataCounter(spi_dev->cfg->dma.rx.channel) ||
 693         !SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE) ||
 694         SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) {
 695         return -3;
 696     }
 697
 698     return 0;
 699 }
 700
 701 void PIOS_SPI_SetPrescalar(uint32_t spi_id, uint32_t prescaler)
 702 {
 703     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 704
 705     bool valid = PIOS_SPI_validate(spi_dev);
 706
 707     PIOS_Assert(valid);
 708     PIOS_Assert(IS_SPI_BAUDRATE_PRESCALER(prescaler));
 709
 710     spi_dev->cfg->regs->CR1 = (spi_dev->cfg->regs->CR1 & ~0x0038) | prescaler;
 711 }
 712
 713 void PIOS_SPI_IRQ_Handler(uint32_t spi_id)
 714 {
 715     struct pios_spi_dev *spi_dev = (struct pios_spi_dev *)spi_id;
 716
 717     bool valid = PIOS_SPI_validate(spi_dev);
 718
 719     PIOS_Assert(valid)
 720
 721     DMA_ClearFlag(spi_dev->cfg->dma.irq.flags);
 722
 723     /* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
 724     while (!(SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_TXE))) {
 725         ;
 726     }
 727
 728     /* Wait for the final bytes of the transfer to complete, including CRC byte(s). */
 729     while (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_I2S_FLAG_BSY)) {
 730         ;
 731     }
 732
 733     if (spi_dev->callback != NULL) {
 734         bool crc_ok = true;
 735         uint8_t crc_val;
 736
 737         if (SPI_I2S_GetFlagStatus(spi_dev->cfg->regs, SPI_FLAG_CRCERR)) {
 738             crc_ok = false;
 739             SPI_I2S_ClearFlag(spi_dev->cfg->regs, SPI_FLAG_CRCERR);
 740         }
 741         crc_val = SPI_GetCRC(spi_dev->cfg->regs, SPI_CRC_Rx);
 742         spi_dev->callback(crc_ok, crc_val);
 743     }
 744 }
 745
 746 #endif /* PIOS_INCLUDE_SPI */
 747
 748 /**
 749  * @}
 750  * @}
 751  */