flight/pios/stm32f30x/pios_usb_hid_istr.c

   1 /******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
   2 * File Name          : usb_istr.c
   3 * Author             : MCD Application Team
   4 * Version            : V3.2.1
   5 * Date               : 07/05/2010
   6 * Description        : ISTR events interrupt service routines
   7 ********************************************************************************
   8 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
   9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
  10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
  11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
  12 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
  13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
  14 *******************************************************************************/
  15
  16 /* Includes ------------------------------------------------------------------*/
  17 #include "pios.h"
  18
  19 #ifdef PIOS_INCLUDE_USB
  20
  21 #include "usb_lib.h"
  22 #include "pios_usb_hid_pwr.h"
  23 #include "pios_usb_hid_istr.h"
  24 #include "pios_usb_hid.h"
  25
  26 /* Private typedef -----------------------------------------------------------*/
  27 /* Private define ------------------------------------------------------------*/
  28 /* Private macro -------------------------------------------------------------*/
  29 /* Private variables ---------------------------------------------------------*/
  30 __IO uint16_t wIstr; /* ISTR register last read value */
  31 __IO uint8_t bIntPackSOF = 0; /* SOFs received between 2 consecutive packets */
  32
  33 /* Extern variables ----------------------------------------------------------*/
  34 /* Private function prototypes -----------------------------------------------*/
  35 /* Private functions ---------------------------------------------------------*/
  36 /* function pointers to non-control endpoints service routines */
  37 void(*pEpInt_IN[7]) (void) = {
  38     EP1_IN_Callback, EP2_IN_Callback, EP3_IN_Callback, EP4_IN_Callback, EP5_IN_Callback, EP6_IN_Callback, EP7_IN_Callback,
  39 };
  40
  41 void(*pEpInt_OUT[7]) (void) = {
  42     EP1_OUT_Callback, EP2_OUT_Callback, EP3_OUT_Callback, EP4_OUT_Callback, EP5_OUT_Callback, EP6_OUT_Callback, EP7_OUT_Callback,
  43 };
  44
  45 #ifndef STM32F10X_CL
  46
  47 /*******************************************************************************
  48 * Function Name  : USB_Istr
  49 * Description    : STR events interrupt service routine
  50 * Input          :
  51 * Output         :
  52 * Return         :
  53 *******************************************************************************/
  54 void USB_LP_CAN1_RX0_IRQHandler(void) // USB_Istr(void)
  55 {
  56     wIstr = _GetISTR();
  57
  58 #if (IMR_MSK & ISTR_CTR)
  59     if (wIstr & ISTR_CTR & wInterrupt_Mask) {
  60         /* servicing of the endpoint correct transfer interrupt */
  61         /* clear of the CTR flag into the sub */
  62         CTR_LP();
  63 #ifdef CTR_CALLBACK
  64         CTR_Callback();
  65 #endif
  66     }
  67 #endif
  68     /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
  69 #if (IMR_MSK & ISTR_RESET)
  70     if (wIstr & ISTR_RESET & wInterrupt_Mask) {
  71         _SetISTR((uint16_t)CLR_RESET);
  72         Device_Property.Reset();
  73 #ifdef RESET_CALLBACK
  74         RESET_Callback();
  75 #endif
  76     }
  77 #endif
  78     /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
  79 #if (IMR_MSK & ISTR_DOVR)
  80     if (wIstr & ISTR_DOVR & wInterrupt_Mask) {
  81         _SetISTR((uint16_t)CLR_DOVR);
  82 #ifdef DOVR_CALLBACK
  83         DOVR_Callback();
  84 #endif
  85     }
  86 #endif
  87     /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
  88 #if (IMR_MSK & ISTR_ERR)
  89     if (wIstr & ISTR_ERR & wInterrupt_Mask) {
  90         _SetISTR((uint16_t)CLR_ERR);
  91 #ifdef ERR_CALLBACK
  92         ERR_Callback();
  93 #endif
  94     }
  95 #endif
  96     /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
  97 #if (IMR_MSK & ISTR_WKUP)
  98     if (wIstr & ISTR_WKUP & wInterrupt_Mask) {
  99         _SetISTR((uint16_t)CLR_WKUP);
 100         Resume(RESUME_EXTERNAL);
 101 #ifdef WKUP_CALLBACK
 102         WKUP_Callback();
 103 #endif
 104     }
 105 #endif
 106     /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 107 #if (IMR_MSK & ISTR_SUSP)
 108     if (wIstr & ISTR_SUSP & wInterrupt_Mask) {
 109         /* check if SUSPEND is possible */
 110         if (fSuspendEnabled) {
 111             Suspend();
 112         } else {
 113             /* if not possible then resume after xx ms */
 114             Resume(RESUME_LATER);
 115         }
 116         /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
 117         _SetISTR((uint16_t)CLR_SUSP);
 118 #ifdef SUSP_CALLBACK
 119         SUSP_Callback();
 120 #endif
 121     }
 122 #endif
 123     /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 124 #if (IMR_MSK & ISTR_SOF)
 125     if (wIstr & ISTR_SOF & wInterrupt_Mask) {
 126         _SetISTR((uint16_t)CLR_SOF);
 127         bIntPackSOF++;
 128
 129 #ifdef SOF_CALLBACK
 130         SOF_Callback();
 131 #endif
 132     }
 133 #endif
 134     /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 135 #if (IMR_MSK & ISTR_ESOF)
 136     if (wIstr & ISTR_ESOF & wInterrupt_Mask) {
 137         _SetISTR((uint16_t)CLR_ESOF);
 138         /* resume handling timing is made with ESOFs */
 139         Resume(RESUME_ESOF); /* request without change of the machine state */
 140
 141 #ifdef ESOF_CALLBACK
 142         ESOF_Callback();
 143 #endif
 144     }
 145 #endif
 146 } /* USB_Istr */
 147
 148 /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 149 #else /* STM32F10X_CL */
 150
 151 /*******************************************************************************
 152 * Function Name  : STM32_PCD_OTG_ISR_Handler
 153 * Description    : Handles all USB Device Interrupts
 154 * Input          : None
 155 * Output         : None
 156 * Return         : status
 157 *******************************************************************************/
 158 u32 STM32_PCD_OTG_ISR_Handler(void)
 159 {
 160     USB_OTG_GINTSTS_TypeDef gintr_status;
 161     u32 retval = 0;
 162
 163     if (USBD_FS_IsDeviceMode()) { /* ensure that we are in device mode */
 164         gintr_status.d32 = OTGD_FS_ReadCoreItr();
 165
 166         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 167
 168         /* If there is no interrupt pending exit the interrupt routine */
 169         if (!gintr_status.d32) {
 170             return 0;
 171         }
 172
 173         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 174         /* Early Suspend interrupt */
 175 #ifdef INTR_ERLYSUSPEND
 176         if (gintr_status.b.erlysuspend) {
 177             retval |= OTGD_FS_Handle_EarlySuspend_ISR();
 178         }
 179 #endif /* INTR_ERLYSUSPEND */
 180
 181         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 182         /* End of Periodic Frame interrupt */
 183 #ifdef INTR_EOPFRAME
 184         if (gintr_status.b.eopframe) {
 185             retval |= OTGD_FS_Handle_EOPF_ISR();
 186         }
 187 #endif /* INTR_EOPFRAME */
 188
 189         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 190         /* Non Periodic Tx FIFO Emty interrupt */
 191 #ifdef INTR_NPTXFEMPTY
 192         if (gintr_status.b.nptxfempty) {
 193             retval |= OTGD_FS_Handle_NPTxFE_ISR();
 194         }
 195 #endif /* INTR_NPTXFEMPTY */
 196
 197         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 198         /* Wakeup or RemoteWakeup interrupt */
 199 #ifdef INTR_WKUPINTR
 200         if (gintr_status.b.wkupintr) {
 201             retval |= OTGD_FS_Handle_Wakeup_ISR();
 202         }
 203 #endif /* INTR_WKUPINTR */
 204
 205         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 206         /* Suspend interrupt */
 207 #ifdef INTR_USBSUSPEND
 208         if (gintr_status.b.usbsuspend) {
 209             /* check if SUSPEND is possible */
 210             if (fSuspendEnabled) {
 211                 Suspend();
 212             } else {
 213                 /* if not possible then resume after xx ms */
 214                 Resume(RESUME_LATER); /* This case shouldn't happen in OTG Device mode because
 215                                          there's no ESOF interrupt to increment the ResumeS.bESOFcnt in the Resume state machine */
 216             }
 217
 218             retval |= OTGD_FS_Handle_USBSuspend_ISR();
 219         }
 220 #endif /* INTR_USBSUSPEND */
 221
 222         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 223         /* Start of Frame interrupt */
 224 #ifdef INTR_SOFINTR
 225         if (gintr_status.b.sofintr) {
 226             /* Update the frame number variable */
 227             bIntPackSOF++;
 228
 229             retval |= OTGD_FS_Handle_Sof_ISR();
 230         }
 231 #endif /* INTR_SOFINTR */
 232
 233         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 234         /* Receive FIFO Queue Status Level interrupt */
 235 #ifdef INTR_RXSTSQLVL
 236         if (gintr_status.b.rxstsqlvl) {
 237             retval |= OTGD_FS_Handle_RxStatusQueueLevel_ISR();
 238         }
 239 #endif /* INTR_RXSTSQLVL */
 240
 241         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 242         /* Enumeration Done interrupt */
 243 #ifdef INTR_ENUMDONE
 244         if (gintr_status.b.enumdone) {
 245             retval |= OTGD_FS_Handle_EnumDone_ISR();
 246         }
 247 #endif /* INTR_ENUMDONE */
 248
 249         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 250         /* Reset interrutp */
 251 #ifdef INTR_USBRESET
 252         if (gintr_status.b.usbreset) {
 253             retval |= OTGD_FS_Handle_UsbReset_ISR();
 254         }
 255 #endif /* INTR_USBRESET */
 256
 257         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 258         /* IN Endpoint interrupt */
 259 #ifdef INTR_INEPINTR
 260         if (gintr_status.b.inepint) {
 261             retval |= OTGD_FS_Handle_InEP_ISR();
 262         }
 263 #endif /* INTR_INEPINTR */
 264
 265         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 266         /* OUT Endpoint interrupt */
 267 #ifdef INTR_OUTEPINTR
 268         if (gintr_status.b.outepintr) {
 269             retval |= OTGD_FS_Handle_OutEP_ISR();
 270         }
 271 #endif /* INTR_OUTEPINTR */
 272
 273         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 274         /* Mode Mismatch interrupt */
 275 #ifdef INTR_MODEMISMATCH
 276         if (gintr_status.b.modemismatch) {
 277             retval |= OTGD_FS_Handle_ModeMismatch_ISR();
 278         }
 279 #endif /* INTR_MODEMISMATCH */
 280
 281         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 282         /* Global IN Endpoints NAK Effective interrupt */
 283 #ifdef INTR_GINNAKEFF
 284         if (gintr_status.b.ginnakeff) {
 285             retval |= OTGD_FS_Handle_GInNakEff_ISR();
 286         }
 287 #endif /* INTR_GINNAKEFF */
 288
 289         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 290         /* Global OUT Endpoints NAK effective interrupt */
 291 #ifdef INTR_GOUTNAKEFF
 292         if (gintr_status.b.goutnakeff) {
 293             retval |= OTGD_FS_Handle_GOutNakEff_ISR();
 294         }
 295 #endif /* INTR_GOUTNAKEFF */
 296
 297         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 298         /* Isochrounous Out packet Dropped interrupt */
 299 #ifdef INTR_ISOOUTDROP
 300         if (gintr_status.b.isooutdrop) {
 301             retval |= OTGD_FS_Handle_IsoOutDrop_ISR();
 302         }
 303 #endif /* INTR_ISOOUTDROP */
 304
 305         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 306         /* Endpoint Mismatch error interrupt */
 307 #ifdef INTR_EPMISMATCH
 308         if (gintr_status.b.epmismatch) {
 309             retval |= OTGD_FS_Handle_EPMismatch_ISR();
 310         }
 311 #endif /* INTR_EPMISMATCH */
 312
 313         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 314         /* Incomplete Isochrous IN tranfer error interrupt */
 315 #ifdef INTR_INCOMPLISOIN
 316         if (gintr_status.b.incomplisoin) {
 317             retval |= OTGD_FS_Handle_IncomplIsoIn_ISR();
 318         }
 319 #endif /* INTR_INCOMPLISOIN */
 320
 321         /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
 322         /* Incomplete Isochrous OUT tranfer error interrupt */
 323 #ifdef INTR_INCOMPLISOOUT
 324         if (gintr_status.b.outepintr) {
 325             retval |= OTGD_FS_Handle_IncomplIsoOut_ISR();
 326         }
 327 #endif /* INTR_INCOMPLISOOUT */
 328     }
 329     return retval;
 330 }
 331
 332 #endif /* STM32F10X_CL */
 333
 334 #endif /* PIOS_INCLUDE_USB */
 335
 336 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/