1 From 07081d82193928ffd0b45df446546f0a41373db7 Mon Sep 17 00:00:00 2001
2 From: Stacey Sheldon <stac@solidgoldbomb.org>
3 Date: Thu, 2 Feb 2012 22:42:03 -0500
4 Subject: [PATCH 1/2] armv7m: remove dummy FP regs for new gdb
7 src/rtos/rtos_standard_stackings.c | 7 +++++++
8 src/target/armv7m.c | 16 ++++++++++++++++
9 2 files changed, 23 insertions(+), 0 deletions(-)
11 diff --git a/src/rtos/rtos_standard_stackings.c b/src/rtos/rtos_standard_stackings.c
12 index 30d9cd9..6ea6565 100644
13 --- a/src/rtos/rtos_standard_stackings.c
14 +++ b/src/rtos/rtos_standard_stackings.c
15 @@ -41,6 +41,7 @@ static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[
17 { 0x34, 32 }, /* lr */
18 { 0x38, 32 }, /* pc */
19 +#ifdef USE_DUMMY_FP_REGS
20 { -1, 96 }, /* FPA1 */
21 { -1, 96 }, /* FPA2 */
22 { -1, 96 }, /* FPA3 */
23 @@ -50,13 +51,19 @@ static const struct stack_register_offset rtos_standard_Cortex_M3_stack_offsets[
24 { -1, 96 }, /* FPA7 */
25 { -1, 96 }, /* FPA8 */
28 { 0x3c, 32 }, /* xPSR */
32 const struct rtos_register_stacking rtos_standard_Cortex_M3_stacking = {
33 0x40, /* stack_registers_size */
34 -1, /* stack_growth_direction */
35 +#ifdef USE_DUMMY_FP_REGS
36 26, /* num_output_registers */
40 8, /* stack_alignment */
41 rtos_standard_Cortex_M3_stack_offsets /* register_offsets */
43 diff --git a/src/target/armv7m.c b/src/target/armv7m.c
44 index 258653e..50b26d4 100644
45 --- a/src/target/armv7m.c
46 +++ b/src/target/armv7m.c
47 @@ -267,6 +267,7 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
48 struct armv7m_common *armv7m = target_to_armv7m(target);
51 +#ifdef USE_DUMMY_FP_REGS
53 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
55 @@ -295,6 +296,21 @@ int armv7m_get_gdb_reg_list(struct target *target, struct reg **reg_list[], int
56 (*reg_list)[25] = &armv7m->core_cache->reg_list[ARMV7M_xPSR];
60 + *reg_list_size = 17;
61 + *reg_list = malloc(sizeof(struct reg*) * (*reg_list_size));
64 + * GDB register packet format for ARM:
65 + * - the first 16 registers are r0..r15
66 + * - followed by xPSR
68 + for (i = 0; i < *reg_list_size; i++)
70 + (*reg_list)[i] = &armv7m->core_cache->reg_list[i];