decoders/jtag_stm32/pd.py

   1 ##
   2 ## This file is part of the libsigrokdecode project.
   3 ##
   4 ## Copyright (C) 2012-2015 Uwe Hermann <uwe@hermann-uwe.de>
   5 ##
   6 ## This program is free software; you can redistribute it and/or modify
   7 ## it under the terms of the GNU General Public License as published by
   8 ## the Free Software Foundation; either version 2 of the License, or
   9 ## (at your option) any later version.
  10 ##
  11 ## This program is distributed in the hope that it will be useful,
  12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ## GNU General Public License for more details.
  15 ##
  16 ## You should have received a copy of the GNU General Public License
  17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
  18 ##
  19
  20 import sigrokdecode as srd
  21
  22 # JTAG debug port data registers (in IR[3:0]) and their sizes (in bits)
  23 # Note: The ARM DAP-DP is not IEEE 1149.1 (JTAG) compliant (as per ARM docs),
  24 #       as it does not implement the EXTEST, SAMPLE, and PRELOAD instructions.
  25 #       Instead, BYPASS is decoded for any of these instructions.
  26 ir = {
  27     '1111': ['BYPASS', 1],  # Bypass register
  28     '1110': ['IDCODE', 32], # ID code register
  29     '1010': ['DPACC', 35],  # Debug port access register
  30     '1011': ['APACC', 35],  # Access port access register
  31     '1000': ['ABORT', 35],  # Abort register # TODO: 32 bits? Datasheet typo?
  32 }
  33
  34 # Boundary scan data registers (in IR[8:4]) and their sizes (in bits)
  35 bs_ir = {
  36     '11111': ['BYPASS', 1], # Bypass register
  37 }
  38
  39 # ARM Cortex-M3 r1p1-01rel0 ID code
  40 cm3_idcode = 0x3ba00477
  41
  42 # http://infocenter.arm.com/help/topic/com.arm.doc.ddi0413c/Chdjibcg.html
  43 cm3_idcode_ver = {
  44     0x3: 'JTAG-DP',
  45     0x2: 'SW-DP',
  46 }
  47 cm3_idcode_part = {
  48     0xba00: 'JTAG-DP',
  49     0xba10: 'SW-DP',
  50 }
  51
  52 # http://infocenter.arm.com/help/topic/com.arm.doc.faqs/ka14408.html
  53 jedec_id = {
  54     5: {
  55         0x3b: 'ARM Ltd.',
  56     },
  57 }
  58
  59 # JTAG ID code in the STM32F10xxx BSC (boundary scan) TAP
  60 jtag_idcode = {
  61     0x06412041: 'Low-density device, rev. A',
  62     0x06410041: 'Medium-density device, rev. A',
  63     0x16410041: 'Medium-density device, rev. B/Z/Y',
  64     0x06414041: 'High-density device, rev. A/Z/Y',
  65     0x06430041: 'XL-density device, rev. A',
  66     0x06418041: 'Connectivity-line device, rev. A/Z',
  67 }
  68
  69 # ACK[2:0] in the DPACC/APACC registers (unlisted values are reserved)
  70 ack_val = {
  71     '001': 'WAIT',
  72     '010': 'OK/FAULT',
  73 }
  74
  75 # 32bit debug port registers (addressed via A[3:2])
  76 dp_reg = {
  77     '00': 'Reserved', # Must be kept at reset value
  78     '01': 'DP CTRL/STAT',
  79     '10': 'DP SELECT',
  80     '11': 'DP RDBUFF',
  81 }
  82
  83 # APB-AP registers (each of them 32 bits wide)
  84 apb_ap_reg = {
  85     0x00: ['CSW', 'Control/status word'],
  86     0x04: ['TAR', 'Transfer address'],
  87     # 0x08: Reserved SBZ
  88     0x0c: ['DRW', 'Data read/write'],
  89     0x10: ['BD0', 'Banked data 0'],
  90     0x14: ['BD1', 'Banked data 1'],
  91     0x18: ['BD2', 'Banked data 2'],
  92     0x1c: ['BD3', 'Banked data 3'],
  93     # 0x20-0xf4: Reserved SBZ
  94     0x800000000: ['ROM', 'Debug ROM address'],
  95     0xfc: ['IDR', 'Identification register'],
  96 }
  97
  98 # TODO: Split off generic ARM/Cortex-M3 parts into another protocol decoder?
  99
 100 # Bits[31:28]: Version (here: 0x3)
 101 #              JTAG-DP: 0x3, SW-DP: 0x2
 102 # Bits[27:12]: Part number (here: 0xba00)
 103 #              JTAG-DP: 0xba00, SW-DP: 0xba10
 104 # Bits[11:1]:  JEDEC (JEP-106) manufacturer ID (here: 0x23b)
 105 #              Bits[11:8]: Continuation code ('ARM Ltd.': 0x04)
 106 #              Bits[7:1]: Identity code ('ARM Ltd.': 0x3b)
 107 # Bits[0:0]:   Reserved (here: 0x1)
 108 def decode_device_id_code(bits):
 109     id_hex = '0x%x' % int('0b' + bits, 2)
 110     ver = cm3_idcode_ver.get(int('0b' + bits[-32:-28], 2), 'UNKNOWN')
 111     part = cm3_idcode_part.get(int('0b' + bits[-28:-12], 2), 'UNKNOWN')
 112     ids = jedec_id.get(int('0b' + bits[-12:-8], 2) + 1, {})
 113     manuf = ids.get(int('0b' + bits[-7:-1], 2), 'UNKNOWN')
 114     return (id_hex, manuf, ver, part)
 115
 116 # DPACC is used to access debug port registers (CTRL/STAT, SELECT, RDBUFF).
 117 # APACC is used to access all Access Port (AHB-AP) registers.
 118
 119 # APACC/DPACC, when transferring data IN:
 120 # Bits[34:3] = DATA[31:0]: 32bit data to transfer (write request)
 121 # Bits[2:1] = A[3:2]: 2-bit address (debug/access port register)
 122 # Bits[0:0] = RnW: Read request (1) or write request (0)
 123 def data_in(instruction, bits):
 124     data, a, rnw = bits[:-3], bits[-3:-1], bits[-1]
 125     data_hex = '0x%x' % int('0b' + data, 2)
 126     r = 'Read request' if (rnw == '1') else 'Write request'
 127     # reg = dp_reg[a] if (instruction == 'DPACC') else apb_ap_reg[a]
 128     reg = dp_reg[a] if (instruction == 'DPACC') else a # TODO
 129     return 'New transaction: DATA: %s, A: %s, RnW: %s' % (data_hex, reg, r)
 130
 131 # APACC/DPACC, when transferring data OUT:
 132 # Bits[34:3] = DATA[31:0]: 32bit data which is read (read request)
 133 # Bits[2:0] = ACK[2:0]: 3-bit acknowledge
 134 def data_out(bits):
 135     data, ack = bits[:-3], bits[-3:]
 136     data_hex = '0x%x' % int('0b' + data, 2)
 137     ack_meaning = ack_val.get(ack, 'Reserved')
 138     return 'Previous transaction result: DATA: %s, ACK: %s' \
 139            % (data_hex, ack_meaning)
 140
 141 class Decoder(srd.Decoder):
 142     api_version = 3
 143     id = 'jtag_stm32'
 144     name = 'JTAG / STM32'
 145     longname = 'Joint Test Action Group / ST STM32'
 146     desc = 'ST STM32-specific JTAG protocol.'
 147     license = 'gplv2+'
 148     inputs = ['jtag']
 149     outputs = []
 150     tags = ['Debug/trace']
 151     annotations = (
 152         ('item', 'Item'),
 153         ('field', 'Field'),
 154         ('command', 'Command'),
 155         ('warning', 'Warning'),
 156     )
 157     annotation_rows = (
 158         ('items', 'Items', (0,)),
 159         ('fields', 'Fields', (1,)),
 160         ('commands', 'Commands', (2,)),
 161         ('warnings', 'Warnings', (3,)),
 162     )
 163
 164     def __init__(self):
 165         self.reset()
 166
 167     def reset(self):
 168         self.state = 'IDLE'
 169         self.samplenums = None
 170
 171     def start(self):
 172         self.out_ann = self.register(srd.OUTPUT_ANN)
 173
 174     def putx(self, data):
 175         self.put(self.ss, self.es, self.out_ann, data)
 176
 177     def putf(self, s, e, data):
 178         self.put(self.samplenums[s][0], self.samplenums[e][1], self.out_ann, data)
 179
 180     def handle_reg_bypass(self, cmd, bits):
 181         self.putx([0, ['BYPASS: ' + bits]])
 182
 183     def handle_reg_idcode(self, cmd, bits):
 184         bits = bits[1:]
 185
 186         id_hex, manuf, ver, part = decode_device_id_code(bits)
 187         cc = '0x%x' % int('0b' + bits[-12:-8], 2)
 188         ic = '0x%x' % int('0b' + bits[-7:-1], 2)
 189
 190         self.putf(0, 0, [1, ['Reserved', 'Res', 'R']])
 191         self.putf(8, 11, [0, ['Continuation code: %s' % cc, 'CC', 'C']])
 192         self.putf(1, 7, [0, ['Identity code: %s' % ic, 'IC', 'I']])
 193         self.putf(1, 11, [1, ['Manufacturer: %s' % manuf, 'Manuf', 'M']])
 194         self.putf(12, 27, [1, ['Part: %s' % part, 'Part', 'P']])
 195         self.putf(28, 31, [1, ['Version: %s' % ver, 'Version', 'V']])
 196         self.putf(32, 32, [1, ['BYPASS (BS TAP)', 'BS', 'B']])
 197
 198         self.putx([2, ['IDCODE: %s (%s: %s/%s)' % \
 199                   decode_device_id_code(bits)]])
 200
 201     def handle_reg_dpacc(self, cmd, bits):
 202         bits = bits[1:]
 203         s = data_in('DPACC', bits) if (cmd == 'DR TDI') else data_out(bits)
 204         self.putx([2, [s]])
 205
 206     def handle_reg_apacc(self, cmd, bits):
 207         bits = bits[1:]
 208         s = data_in('APACC', bits) if (cmd == 'DR TDI') else data_out(bits)
 209         self.putx([2, [s]])
 210
 211     def handle_reg_abort(self, cmd, bits):
 212         bits = bits[1:]
 213         # Bits[31:1]: reserved. Bit[0]: DAPABORT.
 214         a = '' if (bits[0] == '1') else 'No '
 215         s = 'DAPABORT = %s: %sDAP abort generated' % (bits[0], a)
 216         self.putx([2, [s]])
 217
 218         # Warn if DAPABORT[31:1] contains non-zero bits.
 219         if (bits[:-1] != ('0' * 31)):
 220             self.putx([3, ['WARNING: DAPABORT[31:1] reserved!']])
 221
 222     def handle_reg_unknown(self, cmd, bits):
 223         bits = bits[1:]
 224         self.putx([2, ['Unknown instruction: %s' % bits]])
 225
 226     def decode(self, ss, es, data):
 227         cmd, val = data
 228
 229         self.ss, self.es = ss, es
 230
 231         if cmd != 'NEW STATE':
 232             # The right-most char in the 'val' bitstring is the LSB.
 233             val, self.samplenums = val
 234             self.samplenums.reverse()
 235
 236         if cmd == 'IR TDI':
 237             # Switch to the state named after the instruction, or 'UNKNOWN'.
 238             # The STM32F10xxx has two serially connected JTAG TAPs, the
 239             # boundary scan tap (5 bits) and the Cortex-M3 TAP (4 bits).
 240             # See UM 31.5 "STM32F10xxx JTAG TAP connection" for details.
 241             self.state = ir.get(val[5:9], ['UNKNOWN', 0])[0]
 242             bstap_ir = bs_ir.get(val[:5], ['UNKNOWN', 0])[0]
 243             self.putf(4, 8, [1, ['IR (BS TAP): ' + bstap_ir]])
 244             self.putf(0, 3, [1, ['IR (M3 TAP): ' + self.state]])
 245             self.putx([2, ['IR: %s' % self.state]])
 246
 247         # State machine
 248         if self.state == 'BYPASS':
 249             # Here we're interested in incoming bits (TDI).
 250             if cmd != 'DR TDI':
 251                 return
 252             handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
 253             handle_reg(cmd, val)
 254             self.state = 'IDLE'
 255         elif self.state in ('IDCODE', 'ABORT', 'UNKNOWN'):
 256             # Here we're interested in outgoing bits (TDO).
 257             if cmd != 'DR TDO':
 258                 return
 259             handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
 260             handle_reg(cmd, val)
 261             self.state = 'IDLE'
 262         elif self.state in ('DPACC', 'APACC'):
 263             # Here we're interested in incoming and outgoing bits (TDI/TDO).
 264             if cmd not in ('DR TDI', 'DR TDO'):
 265                 return
 266             handle_reg = getattr(self, 'handle_reg_%s' % self.state.lower())
 267             handle_reg(cmd, val)
 268             if cmd == 'DR TDO': # Assumes 'DR TDI' comes before 'DR TDO'.
 269                 self.state = 'IDLE'