decoders/rtc8564/pd.py

   1 ##
   2 ## This file is part of the libsigrokdecode project.
   3 ##
   4 ## Copyright (C) 2012-2014 Uwe Hermann <uwe@hermann-uwe.de>
   5 ##
   6 ## This program is free software; you can redistribute it and/or modify
   7 ## it under the terms of the GNU General Public License as published by
   8 ## the Free Software Foundation; either version 2 of the License, or
   9 ## (at your option) any later version.
  10 ##
  11 ## This program is distributed in the hope that it will be useful,
  12 ## but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 ## GNU General Public License for more details.
  15 ##
  16 ## You should have received a copy of the GNU General Public License
  17 ## along with this program; if not, see <http://www.gnu.org/licenses/>.
  18 ##
  19
  20 import sigrokdecode as srd
  21 from common.srdhelper import bcd2int
  22
  23 def reg_list():
  24     l = []
  25     for i in range(8 + 1):
  26         l.append(('reg-0x%02x' % i, 'Register 0x%02x' % i))
  27
  28     return tuple(l)
  29
  30 class Decoder(srd.Decoder):
  31     api_version = 3
  32     id = 'rtc8564'
  33     name = 'RTC-8564'
  34     longname = 'Epson RTC-8564 JE/NB'
  35     desc = 'Realtime clock module protocol.'
  36     license = 'gplv2+'
  37     inputs = ['i2c']
  38     outputs = []
  39     tags = ['Clock/timing']
  40     annotations = reg_list() + (
  41         ('read', 'Read date/time'),
  42         ('write', 'Write date/time'),
  43         ('bit-reserved', 'Reserved bit'),
  44         ('bit-vl', 'VL bit'),
  45         ('bit-century', 'Century bit'),
  46         ('reg-read', 'Register read'),
  47         ('reg-write', 'Register write'),
  48     )
  49     annotation_rows = (
  50         ('bits', 'Bits', tuple(range(0, 8 + 1)) + (11, 12, 13)),
  51         ('regs', 'Register accesses', (14, 15)),
  52         ('date-time', 'Date/time', (9, 10)),
  53     )
  54
  55     def __init__(self):
  56         self.reset()
  57
  58     def reset(self):
  59         self.state = 'IDLE'
  60         self.hours = -1
  61         self.minutes = -1
  62         self.seconds = -1
  63         self.days = -1
  64         self.weekdays = -1
  65         self.months = -1
  66         self.years = -1
  67         self.bits = []
  68
  69     def start(self):
  70         self.out_ann = self.register(srd.OUTPUT_ANN)
  71
  72     def putx(self, data):
  73         self.put(self.ss, self.es, self.out_ann, data)
  74
  75     def putd(self, bit1, bit2, data):
  76         self.put(self.bits[bit1][1], self.bits[bit2][2], self.out_ann, data)
  77
  78     def putr(self, bit):
  79         self.put(self.bits[bit][1], self.bits[bit][2], self.out_ann,
  80                  [11, ['Reserved bit', 'Reserved', 'Rsvd', 'R']])
  81
  82     def handle_reg_0x00(self, b): # Control register 1
  83         pass
  84
  85     def handle_reg_0x01(self, b): # Control register 2
  86         ti_tp = 1 if (b & (1 << 4)) else 0
  87         af = 1 if (b & (1 << 3)) else 0
  88         tf = 1 if (b & (1 << 2)) else 0
  89         aie = 1 if (b & (1 << 1)) else 0
  90         tie = 1 if (b & (1 << 0)) else 0
  91
  92         ann = ''
  93
  94         s = 'repeated' if ti_tp else 'single-shot'
  95         ann += 'TI/TP = %d: %s operation upon fixed-cycle timer interrupt '\
  96                'events\n' % (ti_tp, s)
  97         s = '' if af else 'no '
  98         ann += 'AF = %d: %salarm interrupt detected\n' % (af, s)
  99         s = '' if tf else 'no '
 100         ann += 'TF = %d: %sfixed-cycle timer interrupt detected\n' % (tf, s)
 101         s = 'enabled' if aie else 'prohibited'
 102         ann += 'AIE = %d: INT# pin output %s when an alarm interrupt '\
 103                'occurs\n' % (aie, s)
 104         s = 'enabled' if tie else 'prohibited'
 105         ann += 'TIE = %d: INT# pin output %s when a fixed-cycle interrupt '\
 106                'event occurs\n' % (tie, s)
 107
 108         self.putx([1, [ann]])
 109
 110     def handle_reg_0x02(self, b): # Seconds / Voltage-low bit
 111         vl = 1 if (b & (1 << 7)) else 0
 112         self.putd(7, 7, [12, ['Voltage low: %d' % vl, 'Volt. low: %d' % vl,
 113                         'VL: %d' % vl, 'VL']])
 114         s = self.seconds = bcd2int(b & 0x7f)
 115         self.putd(6, 0, [2, ['Second: %d' % s, 'Sec: %d' % s, 'S: %d' % s, 'S']])
 116
 117     def handle_reg_0x03(self, b): # Minutes
 118         self.putr(7)
 119         m = self.minutes = bcd2int(b & 0x7f)
 120         self.putd(6, 0, [3, ['Minute: %d' % m, 'Min: %d' % m, 'M: %d' % m, 'M']])
 121
 122     def handle_reg_0x04(self, b): # Hours
 123         self.putr(7)
 124         self.putr(6)
 125         h = self.hours = bcd2int(b & 0x3f)
 126         self.putd(5, 0, [4, ['Hour: %d' % h, 'H: %d' % h, 'H']])
 127
 128     def handle_reg_0x05(self, b): # Days
 129         self.putr(7)
 130         self.putr(6)
 131         d = self.days = bcd2int(b & 0x3f)
 132         self.putd(5, 0, [5, ['Day: %d' % d, 'D: %d' % d, 'D']])
 133
 134     def handle_reg_0x06(self, b): # Weekdays
 135         for i in (7, 6, 5, 4, 3):
 136             self.putr(i)
 137         w = self.weekdays = bcd2int(b & 0x07)
 138         self.putd(2, 0, [6, ['Weekday: %d' % w, 'WD: %d' % w, 'WD', 'W']])
 139
 140     def handle_reg_0x07(self, b): # Months / century bit
 141         c = 1 if (b & (1 << 7)) else 0
 142         self.putd(7, 7, [13, ['Century bit: %d' % c, 'Century: %d' % c,
 143                               'Cent: %d' % c, 'C: %d' % c, 'C']])
 144         self.putr(6)
 145         self.putr(5)
 146         m = self.months = bcd2int(b & 0x1f)
 147         self.putd(4, 0, [7, ['Month: %d' % m, 'Mon: %d' % m, 'M: %d' % m, 'M']])
 148
 149     def handle_reg_0x08(self, b): # Years
 150         y = self.years = bcd2int(b & 0xff)
 151         self.putx([8, ['Year: %d' % y, 'Y: %d' % y, 'Y']])
 152
 153     def handle_reg_0x09(self, b): # Alarm, minute
 154         pass
 155
 156     def handle_reg_0x0a(self, b): # Alarm, hour
 157         pass
 158
 159     def handle_reg_0x0b(self, b): # Alarm, day
 160         pass
 161
 162     def handle_reg_0x0c(self, b): # Alarm, weekday
 163         pass
 164
 165     def handle_reg_0x0d(self, b): # CLKOUT output
 166         pass
 167
 168     def handle_reg_0x0e(self, b): # Timer setting
 169         pass
 170
 171     def handle_reg_0x0f(self, b): # Down counter for fixed-cycle timer
 172         pass
 173
 174     def decode(self, ss, es, data):
 175         cmd, databyte = data
 176
 177         # Collect the 'BITS' packet, then return. The next packet is
 178         # guaranteed to belong to these bits we just stored.
 179         if cmd == 'BITS':
 180             self.bits = databyte
 181             return
 182
 183         # Store the start/end samples of this I²C packet.
 184         self.ss, self.es = ss, es
 185
 186         # State machine.
 187         if self.state == 'IDLE':
 188             # Wait for an I²C START condition.
 189             if cmd != 'START':
 190                 return
 191             self.state = 'GET SLAVE ADDR'
 192             self.ss_block = ss
 193         elif self.state == 'GET SLAVE ADDR':
 194             # Wait for an address write operation.
 195             # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
 196             if cmd != 'ADDRESS WRITE':
 197                 return
 198             self.state = 'GET REG ADDR'
 199         elif self.state == 'GET REG ADDR':
 200             # Wait for a data write (master selects the slave register).
 201             if cmd != 'DATA WRITE':
 202                 return
 203             self.reg = databyte
 204             self.state = 'WRITE RTC REGS'
 205         elif self.state == 'WRITE RTC REGS':
 206             # If we see a Repeated Start here, it's probably an RTC read.
 207             if cmd == 'START REPEAT':
 208                 self.state = 'READ RTC REGS'
 209                 return
 210             # Otherwise: Get data bytes until a STOP condition occurs.
 211             if cmd == 'DATA WRITE':
 212                 r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
 213                 self.putx([15, ['Write register %s' % s, 'Write reg %s' % s,
 214                                 'WR %s' % s, 'WR', 'W']])
 215                 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
 216                 handle_reg(databyte)
 217                 self.reg += 1
 218                 # TODO: Check for NACK!
 219             elif cmd == 'STOP':
 220                 # TODO: Handle read/write of only parts of these items.
 221                 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
 222                     self.years, self.hours, self.minutes, self.seconds)
 223                 self.put(self.ss_block, es, self.out_ann,
 224                          [9, ['Write date/time: %s' % d, 'Write: %s' % d,
 225                               'W: %s' % d]])
 226                 self.state = 'IDLE'
 227             else:
 228                 pass # TODO
 229         elif self.state == 'READ RTC REGS':
 230             # Wait for an address read operation.
 231             # TODO: We should only handle packets to the RTC slave (0xa2/0xa3).
 232             if cmd == 'ADDRESS READ':
 233                 self.state = 'READ RTC REGS2'
 234                 return
 235             else:
 236                 pass # TODO
 237         elif self.state == 'READ RTC REGS2':
 238             if cmd == 'DATA READ':
 239                 r, s = self.reg, '%02X: %02X' % (self.reg, databyte)
 240                 self.putx([15, ['Read register %s' % s, 'Read reg %s' % s,
 241                                 'RR %s' % s, 'RR', 'R']])
 242                 handle_reg = getattr(self, 'handle_reg_0x%02x' % self.reg)
 243                 handle_reg(databyte)
 244                 self.reg += 1
 245                 # TODO: Check for NACK!
 246             elif cmd == 'STOP':
 247                 d = '%02d.%02d.%02d %02d:%02d:%02d' % (self.days, self.months,
 248                     self.years, self.hours, self.minutes, self.seconds)
 249                 self.put(self.ss_block, es, self.out_ann,
 250                          [10, ['Read date/time: %s' % d, 'Read: %s' % d,
 251                                'R: %s' % d]])
 252                 self.state = 'IDLE'
 253             else:
 254                 pass # TODO?