arch/arm/mach-integrator/integrator_cp.c

   1 /*
   2  *  linux/arch/arm/mach-integrator/integrator_cp.c
   3  *
   4  *  Copyright (C) 2003 Deep Blue Solutions Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License.
   9  */
  10 #include <linux/types.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/list.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16 #include <linux/slab.h>
  17 #include <linux/string.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/amba/bus.h>
  20 #include <linux/amba/kmi.h>
  21 #include <linux/amba/clcd.h>
  22
  23 #include <asm/hardware.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26 #include <asm/setup.h>
  27 #include <asm/mach-types.h>
  28 #include <asm/hardware/icst525.h>
  29
  30 #include <asm/arch/cm.h>
  31 #include <asm/arch/lm.h>
  32
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/flash.h>
  35 #include <asm/mach/irq.h>
  36 #include <asm/mach/mmc.h>
  37 #include <asm/mach/map.h>
  38 #include <asm/mach/time.h>
  39
  40 #include "common.h"
  41 #include "clock.h"
  42
  43 #define INTCP_PA_MMC_BASE               0x1c000000
  44 #define INTCP_PA_AACI_BASE              0x1d000000
  45
  46 #define INTCP_PA_FLASH_BASE             0x24000000
  47 #define INTCP_FLASH_SIZE                SZ_32M
  48
  49 #define INTCP_PA_CLCD_BASE              0xc0000000
  50
  51 #ifdef CONFIG_MMU
  52 #define INTCP_VA_CIC_BASE               0xf1000040
  53 #define INTCP_VA_PIC_BASE               0xf1400000
  54 #define INTCP_VA_SIC_BASE               0xfca00000
  55 #else
  56 #define INTCP_VA_CIC_BASE               0x10000040
  57 #define INTCP_VA_PIC_BASE               0x14000000
  58 #define INTCP_VA_SIC_BASE               0xca000000
  59 #endif
  60
  61 #define INTCP_PA_ETH_BASE               0xc8000000
  62 #define INTCP_ETH_SIZE                  0x10
  63
  64 #ifdef CONFIG_MMU
  65 #define INTCP_VA_CTRL_BASE              0xfcb00000
  66 #else
  67 #define INTCP_VA_CTRL_BASE              0xcb000000
  68 #endif
  69 #define INTCP_FLASHPROG                 0x04
  70 #define CINTEGRATOR_FLASHPROG_FLVPPEN   (1 << 0)
  71 #define CINTEGRATOR_FLASHPROG_FLWREN    (1 << 1)
  72
  73 /*
  74  * Logical      Physical
  75  * f1000000     10000000        Core module registers
  76  * f1100000     11000000        System controller registers
  77  * f1200000     12000000        EBI registers
  78  * f1300000     13000000        Counter/Timer
  79  * f1400000     14000000        Interrupt controller
  80  * f1600000     16000000        UART 0
  81  * f1700000     17000000        UART 1
  82  * f1a00000     1a000000        Debug LEDs
  83  * f1b00000     1b000000        GPIO
  84  */
  85
  86 #ifdef CONFIG_MMU
  87 static struct map_desc intcp_io_desc[] __initdata = {
  88         {
  89                 .virtual        = IO_ADDRESS(INTEGRATOR_HDR_BASE),
  90                 .pfn            = __phys_to_pfn(INTEGRATOR_HDR_BASE),
  91                 .length         = SZ_4K,
  92                 .type           = MT_DEVICE
  93         }, {
  94                 .virtual        = IO_ADDRESS(INTEGRATOR_SC_BASE),
  95                 .pfn            = __phys_to_pfn(INTEGRATOR_SC_BASE),
  96                 .length         = SZ_4K,
  97                 .type           = MT_DEVICE
  98         }, {
  99                 .virtual        = IO_ADDRESS(INTEGRATOR_EBI_BASE),
 100                 .pfn            = __phys_to_pfn(INTEGRATOR_EBI_BASE),
 101                 .length         = SZ_4K,
 102                 .type           = MT_DEVICE
 103         }, {
 104                 .virtual        = IO_ADDRESS(INTEGRATOR_CT_BASE),
 105                 .pfn            = __phys_to_pfn(INTEGRATOR_CT_BASE),
 106                 .length         = SZ_4K,
 107                 .type           = MT_DEVICE
 108         }, {
 109                 .virtual        = IO_ADDRESS(INTEGRATOR_IC_BASE),
 110                 .pfn            = __phys_to_pfn(INTEGRATOR_IC_BASE),
 111                 .length         = SZ_4K,
 112                 .type           = MT_DEVICE
 113         }, {
 114                 .virtual        = IO_ADDRESS(INTEGRATOR_UART0_BASE),
 115                 .pfn            = __phys_to_pfn(INTEGRATOR_UART0_BASE),
 116                 .length         = SZ_4K,
 117                 .type           = MT_DEVICE
 118         }, {
 119                 .virtual        = IO_ADDRESS(INTEGRATOR_UART1_BASE),
 120                 .pfn            = __phys_to_pfn(INTEGRATOR_UART1_BASE),
 121                 .length         = SZ_4K,
 122                 .type           = MT_DEVICE
 123         }, {
 124                 .virtual        = IO_ADDRESS(INTEGRATOR_DBG_BASE),
 125                 .pfn            = __phys_to_pfn(INTEGRATOR_DBG_BASE),
 126                 .length         = SZ_4K,
 127                 .type           = MT_DEVICE
 128         }, {
 129                 .virtual        = IO_ADDRESS(INTEGRATOR_GPIO_BASE),
 130                 .pfn            = __phys_to_pfn(INTEGRATOR_GPIO_BASE),
 131                 .length         = SZ_4K,
 132                 .type           = MT_DEVICE
 133         }, {
 134                 .virtual        = 0xfca00000,
 135                 .pfn            = __phys_to_pfn(0xca000000),
 136                 .length         = SZ_4K,
 137                 .type           = MT_DEVICE
 138         }, {
 139                 .virtual        = 0xfcb00000,
 140                 .pfn            = __phys_to_pfn(0xcb000000),
 141                 .length         = SZ_4K,
 142                 .type           = MT_DEVICE
 143         }
 144 };
 145
 146 static void __init intcp_map_io(void)
 147 {
 148         iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
 149 }
 150 #endif
 151
 152 #define cic_writel      __raw_writel
 153 #define cic_readl       __raw_readl
 154 #define pic_writel      __raw_writel
 155 #define pic_readl       __raw_readl
 156 #define sic_writel      __raw_writel
 157 #define sic_readl       __raw_readl
 158
 159 static void cic_mask_irq(unsigned int irq)
 160 {
 161         irq -= IRQ_CIC_START;
 162         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 163 }
 164
 165 static void cic_unmask_irq(unsigned int irq)
 166 {
 167         irq -= IRQ_CIC_START;
 168         cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
 169 }
 170
 171 static struct irq_chip cic_chip = {
 172         .name   = "CIC",
 173         .ack    = cic_mask_irq,
 174         .mask   = cic_mask_irq,
 175         .unmask = cic_unmask_irq,
 176 };
 177
 178 static void pic_mask_irq(unsigned int irq)
 179 {
 180         irq -= IRQ_PIC_START;
 181         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 182 }
 183
 184 static void pic_unmask_irq(unsigned int irq)
 185 {
 186         irq -= IRQ_PIC_START;
 187         pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
 188 }
 189
 190 static struct irq_chip pic_chip = {
 191         .name   = "PIC",
 192         .ack    = pic_mask_irq,
 193         .mask   = pic_mask_irq,
 194         .unmask = pic_unmask_irq,
 195 };
 196
 197 static void sic_mask_irq(unsigned int irq)
 198 {
 199         irq -= IRQ_SIC_START;
 200         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 201 }
 202
 203 static void sic_unmask_irq(unsigned int irq)
 204 {
 205         irq -= IRQ_SIC_START;
 206         sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
 207 }
 208
 209 static struct irq_chip sic_chip = {
 210         .name   = "SIC",
 211         .ack    = sic_mask_irq,
 212         .mask   = sic_mask_irq,
 213         .unmask = sic_unmask_irq,
 214 };
 215
 216 static void
 217 sic_handle_irq(unsigned int irq, struct irqdesc *desc)
 218 {
 219         unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
 220
 221         if (status == 0) {
 222                 do_bad_IRQ(irq, desc);
 223                 return;
 224         }
 225
 226         do {
 227                 irq = ffs(status) - 1;
 228                 status &= ~(1 << irq);
 229
 230                 irq += IRQ_SIC_START;
 231
 232                 desc = irq_desc + irq;
 233                 desc_handle_irq(irq, desc);
 234         } while (status);
 235 }
 236
 237 static void __init intcp_init_irq(void)
 238 {
 239         unsigned int i;
 240
 241         /*
 242          * Disable all interrupt sources
 243          */
 244         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR);
 245         pic_writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR);
 246
 247         for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
 248                 if (i == 11)
 249                         i = 22;
 250                 if (i == 29)
 251                         break;
 252                 set_irq_chip(i, &pic_chip);
 253                 set_irq_handler(i, do_level_IRQ);
 254                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 255         }
 256
 257         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR);
 258         cic_writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR);
 259
 260         for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
 261                 set_irq_chip(i, &cic_chip);
 262                 set_irq_handler(i, do_level_IRQ);
 263                 set_irq_flags(i, IRQF_VALID);
 264         }
 265
 266         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR);
 267         sic_writel(0x00000fff, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR);
 268
 269         for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
 270                 set_irq_chip(i, &sic_chip);
 271                 set_irq_handler(i, do_level_IRQ);
 272                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 273         }
 274
 275         set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
 276 }
 277
 278 /*
 279  * Clock handling
 280  */
 281 #define CM_LOCK (IO_ADDRESS(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
 282 #define CM_AUXOSC (IO_ADDRESS(INTEGRATOR_HDR_BASE)+0x1c)
 283
 284 static const struct icst525_params cp_auxvco_params = {
 285         .ref            = 24000,
 286         .vco_max        = 320000,
 287         .vd_min         = 8,
 288         .vd_max         = 263,
 289         .rd_min         = 3,
 290         .rd_max         = 65,
 291 };
 292
 293 static void cp_auxvco_set(struct clk *clk, struct icst525_vco vco)
 294 {
 295         u32 val;
 296
 297         val = readl(CM_AUXOSC) & ~0x7ffff;
 298         val |= vco.v | (vco.r << 9) | (vco.s << 16);
 299
 300         writel(0xa05f, CM_LOCK);
 301         writel(val, CM_AUXOSC);
 302         writel(0, CM_LOCK);
 303 }
 304
 305 static struct clk cp_clcd_clk = {
 306         .name   = "CLCDCLK",
 307         .params = &cp_auxvco_params,
 308         .setvco = cp_auxvco_set,
 309 };
 310
 311 static struct clk cp_mmci_clk = {
 312         .name   = "MCLK",
 313         .rate   = 14745600,
 314 };
 315
 316 /*
 317  * Flash handling.
 318  */
 319 static int intcp_flash_init(void)
 320 {
 321         u32 val;
 322
 323         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 324         val |= CINTEGRATOR_FLASHPROG_FLWREN;
 325         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 326
 327         return 0;
 328 }
 329
 330 static void intcp_flash_exit(void)
 331 {
 332         u32 val;
 333
 334         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 335         val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
 336         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 337 }
 338
 339 static void intcp_flash_set_vpp(int on)
 340 {
 341         u32 val;
 342
 343         val = readl(INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 344         if (on)
 345                 val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
 346         else
 347                 val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
 348         writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
 349 }
 350
 351 static struct flash_platform_data intcp_flash_data = {
 352         .map_name       = "cfi_probe",
 353         .width          = 4,
 354         .init           = intcp_flash_init,
 355         .exit           = intcp_flash_exit,
 356         .set_vpp        = intcp_flash_set_vpp,
 357 };
 358
 359 static struct resource intcp_flash_resource = {
 360         .start          = INTCP_PA_FLASH_BASE,
 361         .end            = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1,
 362         .flags          = IORESOURCE_MEM,
 363 };
 364
 365 static struct platform_device intcp_flash_device = {
 366         .name           = "armflash",
 367         .id             = 0,
 368         .dev            = {
 369                 .platform_data  = &intcp_flash_data,
 370         },
 371         .num_resources  = 1,
 372         .resource       = &intcp_flash_resource,
 373 };
 374
 375 static struct resource smc91x_resources[] = {
 376         [0] = {
 377                 .start  = INTCP_PA_ETH_BASE,
 378                 .end    = INTCP_PA_ETH_BASE + INTCP_ETH_SIZE - 1,
 379                 .flags  = IORESOURCE_MEM,
 380         },
 381         [1] = {
 382                 .start  = IRQ_CP_ETHINT,
 383                 .end    = IRQ_CP_ETHINT,
 384                 .flags  = IORESOURCE_IRQ,
 385         },
 386 };
 387
 388 static struct platform_device smc91x_device = {
 389         .name           = "smc91x",
 390         .id             = 0,
 391         .num_resources  = ARRAY_SIZE(smc91x_resources),
 392         .resource       = smc91x_resources,
 393 };
 394
 395 static struct platform_device *intcp_devs[] __initdata = {
 396         &intcp_flash_device,
 397         &smc91x_device,
 398 };
 399
 400 /*
 401  * It seems that the card insertion interrupt remains active after
 402  * we've acknowledged it.  We therefore ignore the interrupt, and
 403  * rely on reading it from the SIC.  This also means that we must
 404  * clear the latched interrupt.
 405  */
 406 static unsigned int mmc_status(struct device *dev)
 407 {
 408         unsigned int status = readl(INTCP_VA_SIC_BASE + 4);
 409         writel(8, INTCP_VA_CTRL_BASE + 8);
 410
 411         return status & 8;
 412 }
 413
 414 static struct mmc_platform_data mmc_data = {
 415         .ocr_mask       = MMC_VDD_32_33|MMC_VDD_33_34,
 416         .status         = mmc_status,
 417 };
 418
 419 static struct amba_device mmc_device = {
 420         .dev            = {
 421                 .bus_id = "mb:1c",
 422                 .platform_data = &mmc_data,
 423         },
 424         .res            = {
 425                 .start  = INTCP_PA_MMC_BASE,
 426                 .end    = INTCP_PA_MMC_BASE + SZ_4K - 1,
 427                 .flags  = IORESOURCE_MEM,
 428         },
 429         .irq            = { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 },
 430         .periphid       = 0,
 431 };
 432
 433 static struct amba_device aaci_device = {
 434         .dev            = {
 435                 .bus_id = "mb:1d",
 436         },
 437         .res            = {
 438                 .start  = INTCP_PA_AACI_BASE,
 439                 .end    = INTCP_PA_AACI_BASE + SZ_4K - 1,
 440                 .flags  = IORESOURCE_MEM,
 441         },
 442         .irq            = { IRQ_CP_AACIINT, NO_IRQ },
 443         .periphid       = 0,
 444 };
 445
 446
 447 /*
 448  * CLCD support
 449  */
 450 static struct clcd_panel vga = {
 451         .mode           = {
 452                 .name           = "VGA",
 453                 .refresh        = 60,
 454                 .xres           = 640,
 455                 .yres           = 480,
 456                 .pixclock       = 39721,
 457                 .left_margin    = 40,
 458                 .right_margin   = 24,
 459                 .upper_margin   = 32,
 460                 .lower_margin   = 11,
 461                 .hsync_len      = 96,
 462                 .vsync_len      = 2,
 463                 .sync           = 0,
 464                 .vmode          = FB_VMODE_NONINTERLACED,
 465         },
 466         .width          = -1,
 467         .height         = -1,
 468         .tim2           = TIM2_BCD | TIM2_IPC,
 469         .cntl           = CNTL_LCDTFT | CNTL_LCDVCOMP(1),
 470         .bpp            = 16,
 471         .grayscale      = 0,
 472 };
 473
 474 /*
 475  * Ensure VGA is selected.
 476  */
 477 static void cp_clcd_enable(struct clcd_fb *fb)
 478 {
 479         u32 val;
 480
 481         if (fb->fb.var.bits_per_pixel <= 8)
 482                 val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
 483         else if (fb->fb.var.bits_per_pixel <= 16)
 484                 val = CM_CTRL_LCDMUXSEL_VGA_16BPP
 485                         | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
 486                         | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
 487         else
 488                 val = 0; /* no idea for this, don't trust the docs */
 489
 490         cm_control(CM_CTRL_LCDMUXSEL_MASK|
 491                    CM_CTRL_LCDEN0|
 492                    CM_CTRL_LCDEN1|
 493                    CM_CTRL_STATIC1|
 494                    CM_CTRL_STATIC2|
 495                    CM_CTRL_STATIC|
 496                    CM_CTRL_n24BITEN, val);
 497 }
 498
 499 static unsigned long framesize = SZ_1M;
 500
 501 static int cp_clcd_setup(struct clcd_fb *fb)
 502 {
 503         dma_addr_t dma;
 504
 505         fb->panel = &vga;
 506
 507         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize,
 508                                                     &dma, GFP_KERNEL);
 509         if (!fb->fb.screen_base) {
 510                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
 511                 return -ENOMEM;
 512         }
 513
 514         fb->fb.fix.smem_start   = dma;
 515         fb->fb.fix.smem_len     = framesize;
 516
 517         return 0;
 518 }
 519
 520 static int cp_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 521 {
 522         return dma_mmap_writecombine(&fb->dev->dev, vma,
 523                                      fb->fb.screen_base,
 524                                      fb->fb.fix.smem_start,
 525                                      fb->fb.fix.smem_len);
 526 }
 527
 528 static void cp_clcd_remove(struct clcd_fb *fb)
 529 {
 530         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 531                               fb->fb.screen_base, fb->fb.fix.smem_start);
 532 }
 533
 534 static struct clcd_board clcd_data = {
 535         .name           = "Integrator/CP",
 536         .check          = clcdfb_check,
 537         .decode         = clcdfb_decode,
 538         .enable         = cp_clcd_enable,
 539         .setup          = cp_clcd_setup,
 540         .mmap           = cp_clcd_mmap,
 541         .remove         = cp_clcd_remove,
 542 };
 543
 544 static struct amba_device clcd_device = {
 545         .dev            = {
 546                 .bus_id = "mb:c0",
 547                 .coherent_dma_mask = ~0,
 548                 .platform_data = &clcd_data,
 549         },
 550         .res            = {
 551                 .start  = INTCP_PA_CLCD_BASE,
 552                 .end    = INTCP_PA_CLCD_BASE + SZ_4K - 1,
 553                 .flags  = IORESOURCE_MEM,
 554         },
 555         .dma_mask       = ~0,
 556         .irq            = { IRQ_CP_CLCDCINT, NO_IRQ },
 557         .periphid       = 0,
 558 };
 559
 560 static struct amba_device *amba_devs[] __initdata = {
 561         &mmc_device,
 562         &aaci_device,
 563         &clcd_device,
 564 };
 565
 566 static void __init intcp_init(void)
 567 {
 568         int i;
 569
 570         clk_register(&cp_clcd_clk);
 571         clk_register(&cp_mmci_clk);
 572
 573         platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
 574
 575         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 576                 struct amba_device *d = amba_devs[i];
 577                 amba_device_register(d, &iomem_resource);
 578         }
 579 }
 580
 581 #define TIMER_CTRL_IE   (1 << 5)                        /* Interrupt Enable */
 582
 583 static void __init intcp_timer_init(void)
 584 {
 585         integrator_time_init(1000000 / HZ, TIMER_CTRL_IE);
 586 }
 587
 588 static struct sys_timer cp_timer = {
 589         .init           = intcp_timer_init,
 590         .offset         = integrator_gettimeoffset,
 591 };
 592
 593 MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
 594         /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
 595         .phys_io        = 0x16000000,
 596 #ifdef CONFIG_MMU
 597         .io_pg_offst    = ((0xf1600000) >> 18) & 0xfffc,
 598 #endif
 599         .boot_params    = 0x00000100,
 600 #ifdef CONFIG_MMU
 601         .map_io         = intcp_map_io,
 602 #endif
 603         .init_irq       = intcp_init_irq,
 604         .timer          = &cp_timer,
 605         .init_machine   = intcp_init,
 606 MACHINE_END