drivers/ata/pata_efar.c

   1 /*
   2  *    pata_efar.c - EFAR PIIX clone controller driver
   3  *
   4  *      (C) 2005 Red Hat <alan@redhat.com>
   5  *
   6  *    Some parts based on ata_piix.c by Jeff Garzik and others.
   7  *
   8  *    The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
   9  *    Intel ICH controllers the EFAR widened the UDMA mode register bits
  10  *    and doesn't require the funky clock selection.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/pci.h>
  16 #include <linux/init.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/delay.h>
  19 #include <linux/device.h>
  20 #include <scsi/scsi_host.h>
  21 #include <linux/libata.h>
  22 #include <linux/ata.h>
  23
  24 #define DRV_NAME        "pata_efar"
  25 #define DRV_VERSION     "0.4.2"
  26
  27 /**
  28  *      efar_pre_reset  -       check for 40/80 pin
  29  *      @ap: Port
  30  *
  31  *      Perform cable detection for the EFAR ATA interface. This is
  32  *      different to the PIIX arrangement
  33  */
  34
  35 static int efar_pre_reset(struct ata_port *ap)
  36 {
  37         static const struct pci_bits efar_enable_bits[] = {
  38                 { 0x41U, 1U, 0x80UL, 0x80UL },  /* port 0 */
  39                 { 0x43U, 1U, 0x80UL, 0x80UL },  /* port 1 */
  40         };
  41
  42         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  43         u8 tmp;
  44
  45         if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
  46                 return -ENOENT;
  47
  48         pci_read_config_byte(pdev, 0x47, &tmp);
  49         if (tmp & (2 >> ap->port_no))
  50                 ap->cbl = ATA_CBL_PATA40;
  51         else
  52                 ap->cbl = ATA_CBL_PATA80;
  53         return ata_std_prereset(ap);
  54 }
  55
  56 /**
  57  *      efar_probe_reset - Probe specified port on PATA host controller
  58  *      @ap: Port to probe
  59  *
  60  *      LOCKING:
  61  *      None (inherited from caller).
  62  */
  63
  64 static void efar_error_handler(struct ata_port *ap)
  65 {
  66         ata_bmdma_drive_eh(ap, efar_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
  67 }
  68
  69 /**
  70  *      efar_set_piomode - Initialize host controller PATA PIO timings
  71  *      @ap: Port whose timings we are configuring
  72  *      @adev: um
  73  *
  74  *      Set PIO mode for device, in host controller PCI config space.
  75  *
  76  *      LOCKING:
  77  *      None (inherited from caller).
  78  */
  79
  80 static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
  81 {
  82         unsigned int pio        = adev->pio_mode - XFER_PIO_0;
  83         struct pci_dev *dev     = to_pci_dev(ap->host->dev);
  84         unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
  85         u16 idetm_data;
  86         int control = 0;
  87
  88         /*
  89          *      See Intel Document 298600-004 for the timing programing rules
  90          *      for PIIX/ICH. The EFAR is a clone so very similar
  91          */
  92
  93         static const     /* ISP  RTC */
  94         u8 timings[][2] = { { 0, 0 },
  95                             { 0, 0 },
  96                             { 1, 0 },
  97                             { 2, 1 },
  98                             { 2, 3 }, };
  99
 100         if (pio > 2)
 101                 control |= 1;   /* TIME1 enable */
 102         if (ata_pio_need_iordy(adev))   /* PIO 3/4 require IORDY */
 103                 control |= 2;   /* IE enable */
 104         /* Intel specifies that the PPE functionality is for disk only */
 105         if (adev->class == ATA_DEV_ATA)
 106                 control |= 4;   /* PPE enable */
 107
 108         pci_read_config_word(dev, idetm_port, &idetm_data);
 109
 110         /* Enable PPE, IE and TIME as appropriate */
 111
 112         if (adev->devno == 0) {
 113                 idetm_data &= 0xCCF0;
 114                 idetm_data |= control;
 115                 idetm_data |= (timings[pio][0] << 12) |
 116                         (timings[pio][1] << 8);
 117         } else {
 118                 int shift = 4 * ap->port_no;
 119                 u8 slave_data;
 120
 121                 idetm_data &= 0xCC0F;
 122                 idetm_data |= (control << 4);
 123
 124                 /* Slave timing in seperate register */
 125                 pci_read_config_byte(dev, 0x44, &slave_data);
 126                 slave_data &= 0x0F << shift;
 127                 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
 128                 pci_write_config_byte(dev, 0x44, slave_data);
 129         }
 130
 131         idetm_data |= 0x4000;   /* Ensure SITRE is enabled */
 132         pci_write_config_word(dev, idetm_port, idetm_data);
 133 }
 134
 135 /**
 136  *      efar_set_dmamode - Initialize host controller PATA DMA timings
 137  *      @ap: Port whose timings we are configuring
 138  *      @adev: Device to program
 139  *
 140  *      Set UDMA/MWDMA mode for device, in host controller PCI config space.
 141  *
 142  *      LOCKING:
 143  *      None (inherited from caller).
 144  */
 145
 146 static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
 147 {
 148         struct pci_dev *dev     = to_pci_dev(ap->host->dev);
 149         u8 master_port          = ap->port_no ? 0x42 : 0x40;
 150         u16 master_data;
 151         u8 speed                = adev->dma_mode;
 152         int devid               = adev->devno + 2 * ap->port_no;
 153         u8 udma_enable;
 154
 155         static const     /* ISP  RTC */
 156         u8 timings[][2] = { { 0, 0 },
 157                             { 0, 0 },
 158                             { 1, 0 },
 159                             { 2, 1 },
 160                             { 2, 3 }, };
 161
 162         pci_read_config_word(dev, master_port, &master_data);
 163         pci_read_config_byte(dev, 0x48, &udma_enable);
 164
 165         if (speed >= XFER_UDMA_0) {
 166                 unsigned int udma       = adev->dma_mode - XFER_UDMA_0;
 167                 u16 udma_timing;
 168
 169                 udma_enable |= (1 << devid);
 170
 171                 /* Load the UDMA mode number */
 172                 pci_read_config_word(dev, 0x4A, &udma_timing);
 173                 udma_timing &= ~(7 << (4 * devid));
 174                 udma_timing |= udma << (4 * devid);
 175                 pci_write_config_word(dev, 0x4A, udma_timing);
 176         } else {
 177                 /*
 178                  * MWDMA is driven by the PIO timings. We must also enable
 179                  * IORDY unconditionally along with TIME1. PPE has already
 180                  * been set when the PIO timing was set.
 181                  */
 182                 unsigned int mwdma      = adev->dma_mode - XFER_MW_DMA_0;
 183                 unsigned int control;
 184                 u8 slave_data;
 185                 const unsigned int needed_pio[3] = {
 186                         XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
 187                 };
 188                 int pio = needed_pio[mwdma] - XFER_PIO_0;
 189
 190                 control = 3;    /* IORDY|TIME1 */
 191
 192                 /* If the drive MWDMA is faster than it can do PIO then
 193                    we must force PIO into PIO0 */
 194
 195                 if (adev->pio_mode < needed_pio[mwdma])
 196                         /* Enable DMA timing only */
 197                         control |= 8;   /* PIO cycles in PIO0 */
 198
 199                 if (adev->devno) {      /* Slave */
 200                         master_data &= 0xFF4F;  /* Mask out IORDY|TIME1|DMAONLY */
 201                         master_data |= control << 4;
 202                         pci_read_config_byte(dev, 0x44, &slave_data);
 203                         slave_data &= (0x0F + 0xE1 * ap->port_no);
 204                         /* Load the matching timing */
 205                         slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
 206                         pci_write_config_byte(dev, 0x44, slave_data);
 207                 } else {        /* Master */
 208                         master_data &= 0xCCF4;  /* Mask out IORDY|TIME1|DMAONLY
 209                                                    and master timing bits */
 210                         master_data |= control;
 211                         master_data |=
 212                                 (timings[pio][0] << 12) |
 213                                 (timings[pio][1] << 8);
 214                 }
 215                 udma_enable &= ~(1 << devid);
 216                 pci_write_config_word(dev, master_port, master_data);
 217         }
 218         pci_write_config_byte(dev, 0x48, udma_enable);
 219 }
 220
 221 static struct scsi_host_template efar_sht = {
 222         .module                 = THIS_MODULE,
 223         .name                   = DRV_NAME,
 224         .ioctl                  = ata_scsi_ioctl,
 225         .queuecommand           = ata_scsi_queuecmd,
 226         .can_queue              = ATA_DEF_QUEUE,
 227         .this_id                = ATA_SHT_THIS_ID,
 228         .sg_tablesize           = LIBATA_MAX_PRD,
 229         .max_sectors            = ATA_MAX_SECTORS,
 230         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 231         .emulated               = ATA_SHT_EMULATED,
 232         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 233         .proc_name              = DRV_NAME,
 234         .dma_boundary           = ATA_DMA_BOUNDARY,
 235         .slave_configure        = ata_scsi_slave_config,
 236         .bios_param             = ata_std_bios_param,
 237 };
 238
 239 static const struct ata_port_operations efar_ops = {
 240         .port_disable           = ata_port_disable,
 241         .set_piomode            = efar_set_piomode,
 242         .set_dmamode            = efar_set_dmamode,
 243         .mode_filter            = ata_pci_default_filter,
 244
 245         .tf_load                = ata_tf_load,
 246         .tf_read                = ata_tf_read,
 247         .check_status           = ata_check_status,
 248         .exec_command           = ata_exec_command,
 249         .dev_select             = ata_std_dev_select,
 250
 251         .freeze                 = ata_bmdma_freeze,
 252         .thaw                   = ata_bmdma_thaw,
 253         .error_handler          = efar_error_handler,
 254         .post_internal_cmd      = ata_bmdma_post_internal_cmd,
 255
 256         .bmdma_setup            = ata_bmdma_setup,
 257         .bmdma_start            = ata_bmdma_start,
 258         .bmdma_stop             = ata_bmdma_stop,
 259         .bmdma_status           = ata_bmdma_status,
 260         .qc_prep                = ata_qc_prep,
 261         .qc_issue               = ata_qc_issue_prot,
 262         .data_xfer              = ata_pio_data_xfer,
 263
 264         .irq_handler            = ata_interrupt,
 265         .irq_clear              = ata_bmdma_irq_clear,
 266
 267         .port_start             = ata_port_start,
 268         .port_stop              = ata_port_stop,
 269         .host_stop              = ata_host_stop,
 270 };
 271
 272
 273 /**
 274  *      efar_init_one - Register EFAR ATA PCI device with kernel services
 275  *      @pdev: PCI device to register
 276  *      @ent: Entry in efar_pci_tbl matching with @pdev
 277  *
 278  *      Called from kernel PCI layer.
 279  *
 280  *      LOCKING:
 281  *      Inherited from PCI layer (may sleep).
 282  *
 283  *      RETURNS:
 284  *      Zero on success, or -ERRNO value.
 285  */
 286
 287 static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 288 {
 289         static int printed_version;
 290         static struct ata_port_info info = {
 291                 .sht            = &efar_sht,
 292                 .flags          = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
 293                 .pio_mask       = 0x1f, /* pio0-4 */
 294                 .mwdma_mask     = 0x07, /* mwdma1-2 */
 295                 .udma_mask      = 0x0f, /* UDMA 66 */
 296                 .port_ops       = &efar_ops,
 297         };
 298         static struct ata_port_info *port_info[2] = { &info, &info };
 299
 300         if (!printed_version++)
 301                 dev_printk(KERN_DEBUG, &pdev->dev,
 302                            "version " DRV_VERSION "\n");
 303
 304         return ata_pci_init_one(pdev, port_info, 2);
 305 }
 306
 307 static const struct pci_device_id efar_pci_tbl[] = {
 308         { PCI_VDEVICE(EFAR, 0x9130), },
 309
 310         { }     /* terminate list */
 311 };
 312
 313 static struct pci_driver efar_pci_driver = {
 314         .name                   = DRV_NAME,
 315         .id_table               = efar_pci_tbl,
 316         .probe                  = efar_init_one,
 317         .remove                 = ata_pci_remove_one,
 318 };
 319
 320 static int __init efar_init(void)
 321 {
 322         return pci_register_driver(&efar_pci_driver);
 323 }
 324
 325 static void __exit efar_exit(void)
 326 {
 327         pci_unregister_driver(&efar_pci_driver);
 328 }
 329
 330 module_init(efar_init);
 331 module_exit(efar_exit);
 332
 333 MODULE_AUTHOR("Alan Cox");
 334 MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
 335 MODULE_LICENSE("GPL");
 336 MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
 337 MODULE_VERSION(DRV_VERSION);
 338