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MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / drivers / ata / sata_mv.c
blob1b8e0eb9e0321a2254b1c8a162f71afca0f4cdea
1 /*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2005: EMC Corporation, all rights reserved.
5 * Copyright 2005 Red Hat, Inc. All rights reserved.
6 *
7 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27 #include <linux/init.h>
28 #include <linux/blkdev.h>
29 #include <linux/delay.h>
30 #include <linux/interrupt.h>
31 #include <linux/sched.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/device.h>
34 #include <scsi/scsi_host.h>
35 #include <scsi/scsi_cmnd.h>
36 #include <linux/libata.h>
37 #include <asm/io.h>
38
39 #define DRV_NAME "sata_mv"
40 #define DRV_VERSION "0.7"
41
42 enum {
43 /* BAR's are enumerated in terms of pci_resource_start() terms */
44 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
45 MV_IO_BAR = 2, /* offset 0x18: IO space */
46 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
47
48 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
49 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50
51 MV_PCI_REG_BASE = 0,
52 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
53 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
54 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
55 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
56 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
57 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
58
59 MV_SATAHC0_REG_BASE = 0x20000,
60 MV_FLASH_CTL = 0x1046c,
61 MV_GPIO_PORT_CTL = 0x104f0,
62 MV_RESET_CFG = 0x180d8,
63
64 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
65 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
66 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
67 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
68
69 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
70
71 MV_MAX_Q_DEPTH = 32,
72 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
73
74 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
75 * CRPB needs alignment on a 256B boundary. Size == 256B
76 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
77 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
78 */
79 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
80 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
81 MV_MAX_SG_CT = 176,
82 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
83 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
84
85 MV_PORTS_PER_HC = 4,
86 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
87 MV_PORT_HC_SHIFT = 2,
88 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
89 MV_PORT_MASK = 3,
90
91 /* Host Flags */
92 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
93 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
94 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
95 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
96 ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING),
97 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
98
99 CRQB_FLAG_READ = (1 << 0),
100 CRQB_TAG_SHIFT = 1,
101 CRQB_CMD_ADDR_SHIFT = 8,
102 CRQB_CMD_CS = (0x2 << 11),
103 CRQB_CMD_LAST = (1 << 15),
104
105 CRPB_FLAG_STATUS_SHIFT = 8,
106
107 EPRD_FLAG_END_OF_TBL = (1 << 31),
108
109 /* PCI interface registers */
110
111 PCI_COMMAND_OFS = 0xc00,
112
113 PCI_MAIN_CMD_STS_OFS = 0xd30,
114 STOP_PCI_MASTER = (1 << 2),
115 PCI_MASTER_EMPTY = (1 << 3),
116 GLOB_SFT_RST = (1 << 4),
117
118 MV_PCI_MODE = 0xd00,
119 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
120 MV_PCI_DISC_TIMER = 0xd04,
121 MV_PCI_MSI_TRIGGER = 0xc38,
122 MV_PCI_SERR_MASK = 0xc28,
123 MV_PCI_XBAR_TMOUT = 0x1d04,
124 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
125 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
126 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
127 MV_PCI_ERR_COMMAND = 0x1d50,
128
129 PCI_IRQ_CAUSE_OFS = 0x1d58,
130 PCI_IRQ_MASK_OFS = 0x1d5c,
131 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
132
133 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
134 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
135 PORT0_ERR = (1 << 0), /* shift by port # */
136 PORT0_DONE = (1 << 1), /* shift by port # */
137 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
138 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
139 PCI_ERR = (1 << 18),
140 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
141 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
142 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
143 GPIO_INT = (1 << 22),
144 SELF_INT = (1 << 23),
145 TWSI_INT = (1 << 24),
146 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
147 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
148 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
149 HC_MAIN_RSVD),
150
151 /* SATAHC registers */
152 HC_CFG_OFS = 0,
153
154 HC_IRQ_CAUSE_OFS = 0x14,
155 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
156 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
157 DEV_IRQ = (1 << 8), /* shift by port # */
158
159 /* Shadow block registers */
160 SHD_BLK_OFS = 0x100,
161 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
162
163 /* SATA registers */
164 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
165 SATA_ACTIVE_OFS = 0x350,
166 PHY_MODE3 = 0x310,
167 PHY_MODE4 = 0x314,
168 PHY_MODE2 = 0x330,
169 MV5_PHY_MODE = 0x74,
170 MV5_LT_MODE = 0x30,
171 MV5_PHY_CTL = 0x0C,
172 SATA_INTERFACE_CTL = 0x050,
173
174 MV_M2_PREAMP_MASK = 0x7e0,
175
176 /* Port registers */
177 EDMA_CFG_OFS = 0,
178 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
179 EDMA_CFG_NCQ = (1 << 5),
180 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
181 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
182 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
183
184 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
185 EDMA_ERR_IRQ_MASK_OFS = 0xc,
186 EDMA_ERR_D_PAR = (1 << 0),
187 EDMA_ERR_PRD_PAR = (1 << 1),
188 EDMA_ERR_DEV = (1 << 2),
189 EDMA_ERR_DEV_DCON = (1 << 3),
190 EDMA_ERR_DEV_CON = (1 << 4),
191 EDMA_ERR_SERR = (1 << 5),
192 EDMA_ERR_SELF_DIS = (1 << 7),
193 EDMA_ERR_BIST_ASYNC = (1 << 8),
194 EDMA_ERR_CRBQ_PAR = (1 << 9),
195 EDMA_ERR_CRPB_PAR = (1 << 10),
196 EDMA_ERR_INTRL_PAR = (1 << 11),
197 EDMA_ERR_IORDY = (1 << 12),
198 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
199 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
200 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
201 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
202 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
203 EDMA_ERR_TRANS_PROTO = (1 << 31),
204 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
205 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
206 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
207 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
208 EDMA_ERR_LNK_DATA_RX |
209 EDMA_ERR_LNK_DATA_TX |
210 EDMA_ERR_TRANS_PROTO),
211
212 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
213 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
214
215 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
216 EDMA_REQ_Q_PTR_SHIFT = 5,
217
218 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
219 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
220 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
221 EDMA_RSP_Q_PTR_SHIFT = 3,
222
223 EDMA_CMD_OFS = 0x28,
224 EDMA_EN = (1 << 0),
225 EDMA_DS = (1 << 1),
226 ATA_RST = (1 << 2),
227
228 EDMA_IORDY_TMOUT = 0x34,
229 EDMA_ARB_CFG = 0x38,
230
231 /* Host private flags (hp_flags) */
232 MV_HP_FLAG_MSI = (1 << 0),
233 MV_HP_ERRATA_50XXB0 = (1 << 1),
234 MV_HP_ERRATA_50XXB2 = (1 << 2),
235 MV_HP_ERRATA_60X1B2 = (1 << 3),
236 MV_HP_ERRATA_60X1C0 = (1 << 4),
237 MV_HP_ERRATA_XX42A0 = (1 << 5),
238 MV_HP_50XX = (1 << 6),
239 MV_HP_GEN_IIE = (1 << 7),
240
241 /* Port private flags (pp_flags) */
242 MV_PP_FLAG_EDMA_EN = (1 << 0),
243 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
244 };
245
246 #define IS_50XX(hpriv) ((hpriv)->hp_flags & MV_HP_50XX)
247 #define IS_60XX(hpriv) (((hpriv)->hp_flags & MV_HP_50XX) == 0)
248 #define IS_GEN_I(hpriv) IS_50XX(hpriv)
249 #define IS_GEN_II(hpriv) IS_60XX(hpriv)
250 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
251
252 enum {
253 /* Our DMA boundary is determined by an ePRD being unable to handle
254 * anything larger than 64KB
255 */
256 MV_DMA_BOUNDARY = 0xffffU,
257
258 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
259
260 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
261 };
262
263 enum chip_type {
264 chip_504x,
265 chip_508x,
266 chip_5080,
267 chip_604x,
268 chip_608x,
269 chip_6042,
270 chip_7042,
271 };
272
273 /* Command ReQuest Block: 32B */
274 struct mv_crqb {
275 __le32 sg_addr;
276 __le32 sg_addr_hi;
277 __le16 ctrl_flags;
278 __le16 ata_cmd[11];
279 };
280
281 struct mv_crqb_iie {
282 __le32 addr;
283 __le32 addr_hi;
284 __le32 flags;
285 __le32 len;
286 __le32 ata_cmd[4];
287 };
288
289 /* Command ResPonse Block: 8B */
290 struct mv_crpb {
291 __le16 id;
292 __le16 flags;
293 __le32 tmstmp;
294 };
295
296 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
297 struct mv_sg {
298 __le32 addr;
299 __le32 flags_size;
300 __le32 addr_hi;
301 __le32 reserved;
302 };
303
304 struct mv_port_priv {
305 struct mv_crqb *crqb;
306 dma_addr_t crqb_dma;
307 struct mv_crpb *crpb;
308 dma_addr_t crpb_dma;
309 struct mv_sg *sg_tbl;
310 dma_addr_t sg_tbl_dma;
311 u32 pp_flags;
312 };
313
314 struct mv_port_signal {
315 u32 amps;
316 u32 pre;
317 };
318
319 struct mv_host_priv;
320 struct mv_hw_ops {
321 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
322 unsigned int port);
323 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
324 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
325 void __iomem *mmio);
326 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
327 unsigned int n_hc);
328 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
329 void (*reset_bus)(struct pci_dev *pdev, void __iomem *mmio);
330 };
331
332 struct mv_host_priv {
333 u32 hp_flags;
334 struct mv_port_signal signal[8];
335 const struct mv_hw_ops *ops;
336 };
337
338 static void mv_irq_clear(struct ata_port *ap);
339 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
340 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
341 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
342 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
343 static void mv_phy_reset(struct ata_port *ap);
344 static void __mv_phy_reset(struct ata_port *ap, int can_sleep);
345 static void mv_host_stop(struct ata_host *host);
346 static int mv_port_start(struct ata_port *ap);
347 static void mv_port_stop(struct ata_port *ap);
348 static void mv_qc_prep(struct ata_queued_cmd *qc);
349 static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
350 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
351 static irqreturn_t mv_interrupt(int irq, void *dev_instance);
352 static void mv_eng_timeout(struct ata_port *ap);
353 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
354
355 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
356 unsigned int port);
357 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
358 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
359 void __iomem *mmio);
360 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
361 unsigned int n_hc);
362 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
363 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio);
364
365 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
366 unsigned int port);
367 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
368 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
369 void __iomem *mmio);
370 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
371 unsigned int n_hc);
372 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
373 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio);
374 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
375 unsigned int port_no);
376 static void mv_stop_and_reset(struct ata_port *ap);
377
378 static struct scsi_host_template mv_sht = {
379 .module = THIS_MODULE,
380 .name = DRV_NAME,
381 .ioctl = ata_scsi_ioctl,
382 .queuecommand = ata_scsi_queuecmd,
383 .can_queue = MV_USE_Q_DEPTH,
384 .this_id = ATA_SHT_THIS_ID,
385 .sg_tablesize = MV_MAX_SG_CT / 2,
386 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
387 .emulated = ATA_SHT_EMULATED,
388 .use_clustering = ATA_SHT_USE_CLUSTERING,
389 .proc_name = DRV_NAME,
390 .dma_boundary = MV_DMA_BOUNDARY,
391 .slave_configure = ata_scsi_slave_config,
392 .slave_destroy = ata_scsi_slave_destroy,
393 .bios_param = ata_std_bios_param,
394 };
395
396 static const struct ata_port_operations mv5_ops = {
397 .port_disable = ata_port_disable,
398
399 .tf_load = ata_tf_load,
400 .tf_read = ata_tf_read,
401 .check_status = ata_check_status,
402 .exec_command = ata_exec_command,
403 .dev_select = ata_std_dev_select,
404
405 .phy_reset = mv_phy_reset,
406
407 .qc_prep = mv_qc_prep,
408 .qc_issue = mv_qc_issue,
409 .data_xfer = ata_mmio_data_xfer,
410
411 .eng_timeout = mv_eng_timeout,
412
413 .irq_handler = mv_interrupt,
414 .irq_clear = mv_irq_clear,
415
416 .scr_read = mv5_scr_read,
417 .scr_write = mv5_scr_write,
418
419 .port_start = mv_port_start,
420 .port_stop = mv_port_stop,
421 .host_stop = mv_host_stop,
422 };
423
424 static const struct ata_port_operations mv6_ops = {
425 .port_disable = ata_port_disable,
426
427 .tf_load = ata_tf_load,
428 .tf_read = ata_tf_read,
429 .check_status = ata_check_status,
430 .exec_command = ata_exec_command,
431 .dev_select = ata_std_dev_select,
432
433 .phy_reset = mv_phy_reset,
434
435 .qc_prep = mv_qc_prep,
436 .qc_issue = mv_qc_issue,
437 .data_xfer = ata_mmio_data_xfer,
438
439 .eng_timeout = mv_eng_timeout,
440
441 .irq_handler = mv_interrupt,
442 .irq_clear = mv_irq_clear,
443
444 .scr_read = mv_scr_read,
445 .scr_write = mv_scr_write,
446
447 .port_start = mv_port_start,
448 .port_stop = mv_port_stop,
449 .host_stop = mv_host_stop,
450 };
451
452 static const struct ata_port_operations mv_iie_ops = {
453 .port_disable = ata_port_disable,
454
455 .tf_load = ata_tf_load,
456 .tf_read = ata_tf_read,
457 .check_status = ata_check_status,
458 .exec_command = ata_exec_command,
459 .dev_select = ata_std_dev_select,
460
461 .phy_reset = mv_phy_reset,
462
463 .qc_prep = mv_qc_prep_iie,
464 .qc_issue = mv_qc_issue,
465 .data_xfer = ata_mmio_data_xfer,
466
467 .eng_timeout = mv_eng_timeout,
468
469 .irq_handler = mv_interrupt,
470 .irq_clear = mv_irq_clear,
471
472 .scr_read = mv_scr_read,
473 .scr_write = mv_scr_write,
474
475 .port_start = mv_port_start,
476 .port_stop = mv_port_stop,
477 .host_stop = mv_host_stop,
478 };
479
480 static const struct ata_port_info mv_port_info[] = {
481 { /* chip_504x */
482 .sht = &mv_sht,
483 .flags = MV_COMMON_FLAGS,
484 .pio_mask = 0x1f, /* pio0-4 */
485 .udma_mask = 0x7f, /* udma0-6 */
486 .port_ops = &mv5_ops,
487 },
488 { /* chip_508x */
489 .sht = &mv_sht,
490 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
491 .pio_mask = 0x1f, /* pio0-4 */
492 .udma_mask = 0x7f, /* udma0-6 */
493 .port_ops = &mv5_ops,
494 },
495 { /* chip_5080 */
496 .sht = &mv_sht,
497 .flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
498 .pio_mask = 0x1f, /* pio0-4 */
499 .udma_mask = 0x7f, /* udma0-6 */
500 .port_ops = &mv5_ops,
501 },
502 { /* chip_604x */
503 .sht = &mv_sht,
504 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
505 .pio_mask = 0x1f, /* pio0-4 */
506 .udma_mask = 0x7f, /* udma0-6 */
507 .port_ops = &mv6_ops,
508 },
509 { /* chip_608x */
510 .sht = &mv_sht,
511 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
512 MV_FLAG_DUAL_HC),
513 .pio_mask = 0x1f, /* pio0-4 */
514 .udma_mask = 0x7f, /* udma0-6 */
515 .port_ops = &mv6_ops,
516 },
517 { /* chip_6042 */
518 .sht = &mv_sht,
519 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
520 .pio_mask = 0x1f, /* pio0-4 */
521 .udma_mask = 0x7f, /* udma0-6 */
522 .port_ops = &mv_iie_ops,
523 },
524 { /* chip_7042 */
525 .sht = &mv_sht,
526 .flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
527 MV_FLAG_DUAL_HC),
528 .pio_mask = 0x1f, /* pio0-4 */
529 .udma_mask = 0x7f, /* udma0-6 */
530 .port_ops = &mv_iie_ops,
531 },
532 };
533
534 static const struct pci_device_id mv_pci_tbl[] = {
535 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
536 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
537 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
538 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
539
540 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
541 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
542 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
543 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
544 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
545
546 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
547
548 { } /* terminate list */
549 };
550
551 static struct pci_driver mv_pci_driver = {
552 .name = DRV_NAME,
553 .id_table = mv_pci_tbl,
554 .probe = mv_init_one,
555 .remove = ata_pci_remove_one,
556 };
557
558 static const struct mv_hw_ops mv5xxx_ops = {
559 .phy_errata = mv5_phy_errata,
560 .enable_leds = mv5_enable_leds,
561 .read_preamp = mv5_read_preamp,
562 .reset_hc = mv5_reset_hc,
563 .reset_flash = mv5_reset_flash,
564 .reset_bus = mv5_reset_bus,
565 };
566
567 static const struct mv_hw_ops mv6xxx_ops = {
568 .phy_errata = mv6_phy_errata,
569 .enable_leds = mv6_enable_leds,
570 .read_preamp = mv6_read_preamp,
571 .reset_hc = mv6_reset_hc,
572 .reset_flash = mv6_reset_flash,
573 .reset_bus = mv_reset_pci_bus,
574 };
575
576 /*
577 * module options
578 */
579 static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
580
581
582 /*
583 * Functions
584 */
585
586 static inline void writelfl(unsigned long data, void __iomem *addr)
587 {
588 writel(data, addr);
589 (void) readl(addr); /* flush to avoid PCI posted write */
590 }
591
592 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
593 {
594 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
595 }
596
597 static inline unsigned int mv_hc_from_port(unsigned int port)
598 {
599 return port >> MV_PORT_HC_SHIFT;
600 }
601
602 static inline unsigned int mv_hardport_from_port(unsigned int port)
603 {
604 return port & MV_PORT_MASK;
605 }
606
607 static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
608 unsigned int port)
609 {
610 return mv_hc_base(base, mv_hc_from_port(port));
611 }
612
613 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
614 {
615 return mv_hc_base_from_port(base, port) +
616 MV_SATAHC_ARBTR_REG_SZ +
617 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
618 }
619
620 static inline void __iomem *mv_ap_base(struct ata_port *ap)
621 {
622 return mv_port_base(ap->host->mmio_base, ap->port_no);
623 }
624
625 static inline int mv_get_hc_count(unsigned long port_flags)
626 {
627 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
628 }
629
630 static void mv_irq_clear(struct ata_port *ap)
631 {
632 }
633
634 /**
635 * mv_start_dma - Enable eDMA engine
636 * @base: port base address
637 * @pp: port private data
638 *
639 * Verify the local cache of the eDMA state is accurate with a
640 * WARN_ON.
641 *
642 * LOCKING:
643 * Inherited from caller.
644 */
645 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
646 {
647 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
648 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
649 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
650 }
651 WARN_ON(!(EDMA_EN & readl(base + EDMA_CMD_OFS)));
652 }
653
654 /**
655 * mv_stop_dma - Disable eDMA engine
656 * @ap: ATA channel to manipulate
657 *
658 * Verify the local cache of the eDMA state is accurate with a
659 * WARN_ON.
660 *
661 * LOCKING:
662 * Inherited from caller.
663 */
664 static void mv_stop_dma(struct ata_port *ap)
665 {
666 void __iomem *port_mmio = mv_ap_base(ap);
667 struct mv_port_priv *pp = ap->private_data;
668 u32 reg;
669 int i;
670
671 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
672 /* Disable EDMA if active. The disable bit auto clears.
673 */
674 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
675 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
676 } else {
677 WARN_ON(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS));
678 }
679
680 /* now properly wait for the eDMA to stop */
681 for (i = 1000; i > 0; i--) {
682 reg = readl(port_mmio + EDMA_CMD_OFS);
683 if (!(EDMA_EN & reg)) {
684 break;
685 }
686 udelay(100);
687 }
688
689 if (EDMA_EN & reg) {
690 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
691 /* FIXME: Consider doing a reset here to recover */
692 }
693 }
694
695 #ifdef ATA_DEBUG
696 static void mv_dump_mem(void __iomem *start, unsigned bytes)
697 {
698 int b, w;
699 for (b = 0; b < bytes; ) {
700 DPRINTK("%p: ", start + b);
701 for (w = 0; b < bytes && w < 4; w++) {
702 printk("%08x ",readl(start + b));
703 b += sizeof(u32);
704 }
705 printk("\n");
706 }
707 }
708 #endif
709
710 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
711 {
712 #ifdef ATA_DEBUG
713 int b, w;
714 u32 dw;
715 for (b = 0; b < bytes; ) {
716 DPRINTK("%02x: ", b);
717 for (w = 0; b < bytes && w < 4; w++) {
718 (void) pci_read_config_dword(pdev,b,&dw);
719 printk("%08x ",dw);
720 b += sizeof(u32);
721 }
722 printk("\n");
723 }
724 #endif
725 }
726 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
727 struct pci_dev *pdev)
728 {
729 #ifdef ATA_DEBUG
730 void __iomem *hc_base = mv_hc_base(mmio_base,
731 port >> MV_PORT_HC_SHIFT);
732 void __iomem *port_base;
733 int start_port, num_ports, p, start_hc, num_hcs, hc;
734
735 if (0 > port) {
736 start_hc = start_port = 0;
737 num_ports = 8; /* shld be benign for 4 port devs */
738 num_hcs = 2;
739 } else {
740 start_hc = port >> MV_PORT_HC_SHIFT;
741 start_port = port;
742 num_ports = num_hcs = 1;
743 }
744 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
745 num_ports > 1 ? num_ports - 1 : start_port);
746
747 if (NULL != pdev) {
748 DPRINTK("PCI config space regs:\n");
749 mv_dump_pci_cfg(pdev, 0x68);
750 }
751 DPRINTK("PCI regs:\n");
752 mv_dump_mem(mmio_base+0xc00, 0x3c);
753 mv_dump_mem(mmio_base+0xd00, 0x34);
754 mv_dump_mem(mmio_base+0xf00, 0x4);
755 mv_dump_mem(mmio_base+0x1d00, 0x6c);
756 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
757 hc_base = mv_hc_base(mmio_base, hc);
758 DPRINTK("HC regs (HC %i):\n", hc);
759 mv_dump_mem(hc_base, 0x1c);
760 }
761 for (p = start_port; p < start_port + num_ports; p++) {
762 port_base = mv_port_base(mmio_base, p);
763 DPRINTK("EDMA regs (port %i):\n",p);
764 mv_dump_mem(port_base, 0x54);
765 DPRINTK("SATA regs (port %i):\n",p);
766 mv_dump_mem(port_base+0x300, 0x60);
767 }
768 #endif
769 }
770
771 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
772 {
773 unsigned int ofs;
774
775 switch (sc_reg_in) {
776 case SCR_STATUS:
777 case SCR_CONTROL:
778 case SCR_ERROR:
779 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
780 break;
781 case SCR_ACTIVE:
782 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
783 break;
784 default:
785 ofs = 0xffffffffU;
786 break;
787 }
788 return ofs;
789 }
790
791 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
792 {
793 unsigned int ofs = mv_scr_offset(sc_reg_in);
794
795 if (0xffffffffU != ofs) {
796 return readl(mv_ap_base(ap) + ofs);
797 } else {
798 return (u32) ofs;
799 }
800 }
801
802 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
803 {
804 unsigned int ofs = mv_scr_offset(sc_reg_in);
805
806 if (0xffffffffU != ofs) {
807 writelfl(val, mv_ap_base(ap) + ofs);
808 }
809 }
810
811 /**
812 * mv_host_stop - Host specific cleanup/stop routine.
813 * @host: host data structure
814 *
815 * Disable ints, cleanup host memory, call general purpose
816 * host_stop.
817 *
818 * LOCKING:
819 * Inherited from caller.
820 */
821 static void mv_host_stop(struct ata_host *host)
822 {
823 struct mv_host_priv *hpriv = host->private_data;
824 struct pci_dev *pdev = to_pci_dev(host->dev);
825
826 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
827 pci_disable_msi(pdev);
828 } else {
829 pci_intx(pdev, 0);
830 }
831 kfree(hpriv);
832 ata_host_stop(host);
833 }
834
835 static inline void mv_priv_free(struct mv_port_priv *pp, struct device *dev)
836 {
837 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
838 }
839
840 static void mv_edma_cfg(struct mv_host_priv *hpriv, void __iomem *port_mmio)
841 {
842 u32 cfg = readl(port_mmio + EDMA_CFG_OFS);
843
844 /* set up non-NCQ EDMA configuration */
845 cfg &= ~0x1f; /* clear queue depth */
846 cfg &= ~EDMA_CFG_NCQ; /* clear NCQ mode */
847 cfg &= ~(1 << 9); /* disable equeue */
848
849 if (IS_GEN_I(hpriv))
850 cfg |= (1 << 8); /* enab config burst size mask */
851
852 else if (IS_GEN_II(hpriv))
853 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
854
855 else if (IS_GEN_IIE(hpriv)) {
856 cfg |= (1 << 23); /* dis RX PM port mask */
857 cfg &= ~(1 << 16); /* dis FIS-based switching (for now) */
858 cfg &= ~(1 << 19); /* dis 128-entry queue (for now?) */
859 cfg |= (1 << 18); /* enab early completion */
860 cfg |= (1 << 17); /* enab host q cache */
861 cfg |= (1 << 22); /* enab cutthrough */
862 }
863
864 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
865 }
866
867 /**
868 * mv_port_start - Port specific init/start routine.
869 * @ap: ATA channel to manipulate
870 *
871 * Allocate and point to DMA memory, init port private memory,
872 * zero indices.
873 *
874 * LOCKING:
875 * Inherited from caller.
876 */
877 static int mv_port_start(struct ata_port *ap)
878 {
879 struct device *dev = ap->host->dev;
880 struct mv_host_priv *hpriv = ap->host->private_data;
881 struct mv_port_priv *pp;
882 void __iomem *port_mmio = mv_ap_base(ap);
883 void *mem;
884 dma_addr_t mem_dma;
885 int rc = -ENOMEM;
886
887 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
888 if (!pp)
889 goto err_out;
890 memset(pp, 0, sizeof(*pp));
891
892 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
893 GFP_KERNEL);
894 if (!mem)
895 goto err_out_pp;
896 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
897
898 rc = ata_pad_alloc(ap, dev);
899 if (rc)
900 goto err_out_priv;
901
902 /* First item in chunk of DMA memory:
903 * 32-slot command request table (CRQB), 32 bytes each in size
904 */
905 pp->crqb = mem;
906 pp->crqb_dma = mem_dma;
907 mem += MV_CRQB_Q_SZ;
908 mem_dma += MV_CRQB_Q_SZ;
909
910 /* Second item:
911 * 32-slot command response table (CRPB), 8 bytes each in size
912 */
913 pp->crpb = mem;
914 pp->crpb_dma = mem_dma;
915 mem += MV_CRPB_Q_SZ;
916 mem_dma += MV_CRPB_Q_SZ;
917
918 /* Third item:
919 * Table of scatter-gather descriptors (ePRD), 16 bytes each
920 */
921 pp->sg_tbl = mem;
922 pp->sg_tbl_dma = mem_dma;
923
924 mv_edma_cfg(hpriv, port_mmio);
925
926 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
927 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
928 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
929
930 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
931 writelfl(pp->crqb_dma & 0xffffffff,
932 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
933 else
934 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
935
936 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
937
938 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
939 writelfl(pp->crpb_dma & 0xffffffff,
940 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
941 else
942 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
943
944 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
945 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
946
947 /* Don't turn on EDMA here...do it before DMA commands only. Else
948 * we'll be unable to send non-data, PIO, etc due to restricted access
949 * to shadow regs.
950 */
951 ap->private_data = pp;
952 return 0;
953
954 err_out_priv:
955 mv_priv_free(pp, dev);
956 err_out_pp:
957 kfree(pp);
958 err_out:
959 return rc;
960 }
961
962 /**
963 * mv_port_stop - Port specific cleanup/stop routine.
964 * @ap: ATA channel to manipulate
965 *
966 * Stop DMA, cleanup port memory.
967 *
968 * LOCKING:
969 * This routine uses the host lock to protect the DMA stop.
970 */
971 static void mv_port_stop(struct ata_port *ap)
972 {
973 struct device *dev = ap->host->dev;
974 struct mv_port_priv *pp = ap->private_data;
975 unsigned long flags;
976
977 spin_lock_irqsave(&ap->host->lock, flags);
978 mv_stop_dma(ap);
979 spin_unlock_irqrestore(&ap->host->lock, flags);
980
981 ap->private_data = NULL;
982 ata_pad_free(ap, dev);
983 mv_priv_free(pp, dev);
984 kfree(pp);
985 }
986
987 /**
988 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
989 * @qc: queued command whose SG list to source from
990 *
991 * Populate the SG list and mark the last entry.
992 *
993 * LOCKING:
994 * Inherited from caller.
995 */
996 static void mv_fill_sg(struct ata_queued_cmd *qc)
997 {
998 struct mv_port_priv *pp = qc->ap->private_data;
999 unsigned int i = 0;
1000 struct scatterlist *sg;
1001
1002 ata_for_each_sg(sg, qc) {
1003 dma_addr_t addr;
1004 u32 sg_len, len, offset;
1005
1006 addr = sg_dma_address(sg);
1007 sg_len = sg_dma_len(sg);
1008
1009 while (sg_len) {
1010 offset = addr & MV_DMA_BOUNDARY;
1011 len = sg_len;
1012 if ((offset + sg_len) > 0x10000)
1013 len = 0x10000 - offset;
1014
1015 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
1016 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
1017 pp->sg_tbl[i].flags_size = cpu_to_le32(len & 0xffff);
1018
1019 sg_len -= len;
1020 addr += len;
1021
1022 if (!sg_len && ata_sg_is_last(sg, qc))
1023 pp->sg_tbl[i].flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
1024
1025 i++;
1026 }
1027 }
1028 }
1029
1030 static inline unsigned mv_inc_q_index(unsigned index)
1031 {
1032 return (index + 1) & MV_MAX_Q_DEPTH_MASK;
1033 }
1034
1035 static inline void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
1036 {
1037 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
1038 (last ? CRQB_CMD_LAST : 0);
1039 *cmdw = cpu_to_le16(tmp);
1040 }
1041
1042 /**
1043 * mv_qc_prep - Host specific command preparation.
1044 * @qc: queued command to prepare
1045 *
1046 * This routine simply redirects to the general purpose routine
1047 * if command is not DMA. Else, it handles prep of the CRQB
1048 * (command request block), does some sanity checking, and calls
1049 * the SG load routine.
1050 *
1051 * LOCKING:
1052 * Inherited from caller.
1053 */
1054 static void mv_qc_prep(struct ata_queued_cmd *qc)
1055 {
1056 struct ata_port *ap = qc->ap;
1057 struct mv_port_priv *pp = ap->private_data;
1058 __le16 *cw;
1059 struct ata_taskfile *tf;
1060 u16 flags = 0;
1061 unsigned in_index;
1062
1063 if (ATA_PROT_DMA != qc->tf.protocol)
1064 return;
1065
1066 /* Fill in command request block
1067 */
1068 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1069 flags |= CRQB_FLAG_READ;
1070 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1071 flags |= qc->tag << CRQB_TAG_SHIFT;
1072
1073 /* get current queue index from hardware */
1074 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1075 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1076
1077 pp->crqb[in_index].sg_addr =
1078 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1079 pp->crqb[in_index].sg_addr_hi =
1080 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1081 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
1082
1083 cw = &pp->crqb[in_index].ata_cmd[0];
1084 tf = &qc->tf;
1085
1086 /* Sadly, the CRQB cannot accomodate all registers--there are
1087 * only 11 bytes...so we must pick and choose required
1088 * registers based on the command. So, we drop feature and
1089 * hob_feature for [RW] DMA commands, but they are needed for
1090 * NCQ. NCQ will drop hob_nsect.
1091 */
1092 switch (tf->command) {
1093 case ATA_CMD_READ:
1094 case ATA_CMD_READ_EXT:
1095 case ATA_CMD_WRITE:
1096 case ATA_CMD_WRITE_EXT:
1097 case ATA_CMD_WRITE_FUA_EXT:
1098 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1099 break;
1100 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
1101 case ATA_CMD_FPDMA_READ:
1102 case ATA_CMD_FPDMA_WRITE:
1103 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
1104 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1105 break;
1106 #endif /* FIXME: remove this line when NCQ added */
1107 default:
1108 /* The only other commands EDMA supports in non-queued and
1109 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1110 * of which are defined/used by Linux. If we get here, this
1111 * driver needs work.
1112 *
1113 * FIXME: modify libata to give qc_prep a return value and
1114 * return error here.
1115 */
1116 BUG_ON(tf->command);
1117 break;
1118 }
1119 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1120 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1121 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1122 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1123 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1124 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1125 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1126 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1127 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1128
1129 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1130 return;
1131 mv_fill_sg(qc);
1132 }
1133
1134 /**
1135 * mv_qc_prep_iie - Host specific command preparation.
1136 * @qc: queued command to prepare
1137 *
1138 * This routine simply redirects to the general purpose routine
1139 * if command is not DMA. Else, it handles prep of the CRQB
1140 * (command request block), does some sanity checking, and calls
1141 * the SG load routine.
1142 *
1143 * LOCKING:
1144 * Inherited from caller.
1145 */
1146 static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1147 {
1148 struct ata_port *ap = qc->ap;
1149 struct mv_port_priv *pp = ap->private_data;
1150 struct mv_crqb_iie *crqb;
1151 struct ata_taskfile *tf;
1152 unsigned in_index;
1153 u32 flags = 0;
1154
1155 if (ATA_PROT_DMA != qc->tf.protocol)
1156 return;
1157
1158 /* Fill in Gen IIE command request block
1159 */
1160 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1161 flags |= CRQB_FLAG_READ;
1162
1163 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
1164 flags |= qc->tag << CRQB_TAG_SHIFT;
1165
1166 /* get current queue index from hardware */
1167 in_index = (readl(mv_ap_base(ap) + EDMA_REQ_Q_IN_PTR_OFS)
1168 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1169
1170 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
1171 crqb->addr = cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
1172 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
1173 crqb->flags = cpu_to_le32(flags);
1174
1175 tf = &qc->tf;
1176 crqb->ata_cmd[0] = cpu_to_le32(
1177 (tf->command << 16) |
1178 (tf->feature << 24)
1179 );
1180 crqb->ata_cmd[1] = cpu_to_le32(
1181 (tf->lbal << 0) |
1182 (tf->lbam << 8) |
1183 (tf->lbah << 16) |
1184 (tf->device << 24)
1185 );
1186 crqb->ata_cmd[2] = cpu_to_le32(
1187 (tf->hob_lbal << 0) |
1188 (tf->hob_lbam << 8) |
1189 (tf->hob_lbah << 16) |
1190 (tf->hob_feature << 24)
1191 );
1192 crqb->ata_cmd[3] = cpu_to_le32(
1193 (tf->nsect << 0) |
1194 (tf->hob_nsect << 8)
1195 );
1196
1197 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1198 return;
1199 mv_fill_sg(qc);
1200 }
1201
1202 /**
1203 * mv_qc_issue - Initiate a command to the host
1204 * @qc: queued command to start
1205 *
1206 * This routine simply redirects to the general purpose routine
1207 * if command is not DMA. Else, it sanity checks our local
1208 * caches of the request producer/consumer indices then enables
1209 * DMA and bumps the request producer index.
1210 *
1211 * LOCKING:
1212 * Inherited from caller.
1213 */
1214 static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
1215 {
1216 void __iomem *port_mmio = mv_ap_base(qc->ap);
1217 struct mv_port_priv *pp = qc->ap->private_data;
1218 unsigned in_index;
1219 u32 in_ptr;
1220
1221 if (ATA_PROT_DMA != qc->tf.protocol) {
1222 /* We're about to send a non-EDMA capable command to the
1223 * port. Turn off EDMA so there won't be problems accessing
1224 * shadow block, etc registers.
1225 */
1226 mv_stop_dma(qc->ap);
1227 return ata_qc_issue_prot(qc);
1228 }
1229
1230 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1231 in_index = (in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1232
1233 /* until we do queuing, the queue should be empty at this point */
1234 WARN_ON(in_index != ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1235 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1236
1237 in_index = mv_inc_q_index(in_index); /* now incr producer index */
1238
1239 mv_start_dma(port_mmio, pp);
1240
1241 /* and write the request in pointer to kick the EDMA to life */
1242 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
1243 in_ptr |= in_index << EDMA_REQ_Q_PTR_SHIFT;
1244 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1245
1246 return 0;
1247 }
1248
1249 /**
1250 * mv_get_crpb_status - get status from most recently completed cmd
1251 * @ap: ATA channel to manipulate
1252 *
1253 * This routine is for use when the port is in DMA mode, when it
1254 * will be using the CRPB (command response block) method of
1255 * returning command completion information. We check indices
1256 * are good, grab status, and bump the response consumer index to
1257 * prove that we're up to date.
1258 *
1259 * LOCKING:
1260 * Inherited from caller.
1261 */
1262 static u8 mv_get_crpb_status(struct ata_port *ap)
1263 {
1264 void __iomem *port_mmio = mv_ap_base(ap);
1265 struct mv_port_priv *pp = ap->private_data;
1266 unsigned out_index;
1267 u32 out_ptr;
1268 u8 ata_status;
1269
1270 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1271 out_index = (out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1272
1273 ata_status = le16_to_cpu(pp->crpb[out_index].flags)
1274 >> CRPB_FLAG_STATUS_SHIFT;
1275
1276 /* increment our consumer index... */
1277 out_index = mv_inc_q_index(out_index);
1278
1279 /* and, until we do NCQ, there should only be 1 CRPB waiting */
1280 WARN_ON(out_index != ((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
1281 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
1282
1283 /* write out our inc'd consumer index so EDMA knows we're caught up */
1284 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
1285 out_ptr |= out_index << EDMA_RSP_Q_PTR_SHIFT;
1286 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
1287
1288 /* Return ATA status register for completed CRPB */
1289 return ata_status;
1290 }
1291
1292 /**
1293 * mv_err_intr - Handle error interrupts on the port
1294 * @ap: ATA channel to manipulate
1295 * @reset_allowed: bool: 0 == don't trigger from reset here
1296 *
1297 * In most cases, just clear the interrupt and move on. However,
1298 * some cases require an eDMA reset, which is done right before
1299 * the COMRESET in mv_phy_reset(). The SERR case requires a
1300 * clear of pending errors in the SATA SERROR register. Finally,
1301 * if the port disabled DMA, update our cached copy to match.
1302 *
1303 * LOCKING:
1304 * Inherited from caller.
1305 */
1306 static void mv_err_intr(struct ata_port *ap, int reset_allowed)
1307 {
1308 void __iomem *port_mmio = mv_ap_base(ap);
1309 u32 edma_err_cause, serr = 0;
1310
1311 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1312
1313 if (EDMA_ERR_SERR & edma_err_cause) {
1314 sata_scr_read(ap, SCR_ERROR, &serr);
1315 sata_scr_write_flush(ap, SCR_ERROR, serr);
1316 }
1317 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1318 struct mv_port_priv *pp = ap->private_data;
1319 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1320 }
1321 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1322 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1323
1324 /* Clear EDMA now that SERR cleanup done */
1325 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1326
1327 /* check for fatal here and recover if needed */
1328 if (reset_allowed && (EDMA_ERR_FATAL & edma_err_cause))
1329 mv_stop_and_reset(ap);
1330 }
1331
1332 /**
1333 * mv_host_intr - Handle all interrupts on the given host controller
1334 * @host: host specific structure
1335 * @relevant: port error bits relevant to this host controller
1336 * @hc: which host controller we're to look at
1337 *
1338 * Read then write clear the HC interrupt status then walk each
1339 * port connected to the HC and see if it needs servicing. Port
1340 * success ints are reported in the HC interrupt status reg, the
1341 * port error ints are reported in the higher level main
1342 * interrupt status register and thus are passed in via the
1343 * 'relevant' argument.
1344 *
1345 * LOCKING:
1346 * Inherited from caller.
1347 */
1348 static void mv_host_intr(struct ata_host *host, u32 relevant, unsigned int hc)
1349 {
1350 void __iomem *mmio = host->mmio_base;
1351 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1352 struct ata_queued_cmd *qc;
1353 u32 hc_irq_cause;
1354 int shift, port, port0, hard_port, handled;
1355 unsigned int err_mask;
1356
1357 if (hc == 0) {
1358 port0 = 0;
1359 } else {
1360 port0 = MV_PORTS_PER_HC;
1361 }
1362
1363 /* we'll need the HC success int register in most cases */
1364 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1365 if (hc_irq_cause) {
1366 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1367 }
1368
1369 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1370 hc,relevant,hc_irq_cause);
1371
1372 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1373 u8 ata_status = 0;
1374 struct ata_port *ap = host->ports[port];
1375 struct mv_port_priv *pp = ap->private_data;
1376
1377 hard_port = mv_hardport_from_port(port); /* range 0..3 */
1378 handled = 0; /* ensure ata_status is set if handled++ */
1379
1380 /* Note that DEV_IRQ might happen spuriously during EDMA,
1381 * and should be ignored in such cases.
1382 * The cause of this is still under investigation.
1383 */
1384 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1385 /* EDMA: check for response queue interrupt */
1386 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1387 ata_status = mv_get_crpb_status(ap);
1388 handled = 1;
1389 }
1390 } else {
1391 /* PIO: check for device (drive) interrupt */
1392 if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1393 ata_status = readb((void __iomem *)
1394 ap->ioaddr.status_addr);
1395 handled = 1;
1396 /* ignore spurious intr if drive still BUSY */
1397 if (ata_status & ATA_BUSY) {
1398 ata_status = 0;
1399 handled = 0;
1400 }
1401 }
1402 }
1403
1404 if (ap && (ap->flags & ATA_FLAG_DISABLED))
1405 continue;
1406
1407 err_mask = ac_err_mask(ata_status);
1408
1409 shift = port << 1; /* (port * 2) */
1410 if (port >= MV_PORTS_PER_HC) {
1411 shift++; /* skip bit 8 in the HC Main IRQ reg */
1412 }
1413 if ((PORT0_ERR << shift) & relevant) {
1414 mv_err_intr(ap, 1);
1415 err_mask |= AC_ERR_OTHER;
1416 handled = 1;
1417 }
1418
1419 if (handled) {
1420 qc = ata_qc_from_tag(ap, ap->active_tag);
1421 if (qc && (qc->flags & ATA_QCFLAG_ACTIVE)) {
1422 VPRINTK("port %u IRQ found for qc, "
1423 "ata_status 0x%x\n", port,ata_status);
1424 /* mark qc status appropriately */
1425 if (!(qc->tf.flags & ATA_TFLAG_POLLING)) {
1426 qc->err_mask |= err_mask;
1427 ata_qc_complete(qc);
1428 }
1429 }
1430 }
1431 }
1432 VPRINTK("EXIT\n");
1433 }
1434
1435 /**
1436 * mv_interrupt -
1437 * @irq: unused
1438 * @dev_instance: private data; in this case the host structure
1439 * @regs: unused
1440 *
1441 * Read the read only register to determine if any host
1442 * controllers have pending interrupts. If so, call lower level
1443 * routine to handle. Also check for PCI errors which are only
1444 * reported here.
1445 *
1446 * LOCKING:
1447 * This routine holds the host lock while processing pending
1448 * interrupts.
1449 */
1450 static irqreturn_t mv_interrupt(int irq, void *dev_instance)
1451 {
1452 struct ata_host *host = dev_instance;
1453 unsigned int hc, handled = 0, n_hcs;
1454 void __iomem *mmio = host->mmio_base;
1455 struct mv_host_priv *hpriv;
1456 u32 irq_stat;
1457
1458 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1459
1460 /* check the cases where we either have nothing pending or have read
1461 * a bogus register value which can indicate HW removal or PCI fault
1462 */
1463 if (!irq_stat || (0xffffffffU == irq_stat)) {
1464 return IRQ_NONE;
1465 }
1466
1467 n_hcs = mv_get_hc_count(host->ports[0]->flags);
1468 spin_lock(&host->lock);
1469
1470 for (hc = 0; hc < n_hcs; hc++) {
1471 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1472 if (relevant) {
1473 mv_host_intr(host, relevant, hc);
1474 handled++;
1475 }
1476 }
1477
1478 hpriv = host->private_data;
1479 if (IS_60XX(hpriv)) {
1480 /* deal with the interrupt coalescing bits */
1481 if (irq_stat & (TRAN_LO_DONE | TRAN_HI_DONE | PORTS_0_7_COAL_DONE)) {
1482 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_LO);
1483 writelfl(0, mmio + MV_IRQ_COAL_CAUSE_HI);
1484 writelfl(0, mmio + MV_IRQ_COAL_CAUSE);
1485 }
1486 }
1487
1488 if (PCI_ERR & irq_stat) {
1489 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1490 readl(mmio + PCI_IRQ_CAUSE_OFS));
1491
1492 DPRINTK("All regs @ PCI error\n");
1493 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
1494
1495 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1496 handled++;
1497 }
1498 spin_unlock(&host->lock);
1499
1500 return IRQ_RETVAL(handled);
1501 }
1502
1503 static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
1504 {
1505 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
1506 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
1507
1508 return hc_mmio + ofs;
1509 }
1510
1511 static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
1512 {
1513 unsigned int ofs;
1514
1515 switch (sc_reg_in) {
1516 case SCR_STATUS:
1517 case SCR_ERROR:
1518 case SCR_CONTROL:
1519 ofs = sc_reg_in * sizeof(u32);
1520 break;
1521 default:
1522 ofs = 0xffffffffU;
1523 break;
1524 }
1525 return ofs;
1526 }
1527
1528 static u32 mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
1529 {
1530 void __iomem *mmio = mv5_phy_base(ap->host->mmio_base, ap->port_no);
1531 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1532
1533 if (ofs != 0xffffffffU)
1534 return readl(mmio + ofs);
1535 else
1536 return (u32) ofs;
1537 }
1538
1539 static void mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
1540 {
1541 void __iomem *mmio = mv5_phy_base(ap->host->mmio_base, ap->port_no);
1542 unsigned int ofs = mv5_scr_offset(sc_reg_in);
1543
1544 if (ofs != 0xffffffffU)
1545 writelfl(val, mmio + ofs);
1546 }
1547
1548 static void mv5_reset_bus(struct pci_dev *pdev, void __iomem *mmio)
1549 {
1550 u8 rev_id;
1551 int early_5080;
1552
1553 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1554
1555 early_5080 = (pdev->device == 0x5080) && (rev_id == 0);
1556
1557 if (!early_5080) {
1558 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1559 tmp |= (1 << 0);
1560 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1561 }
1562
1563 mv_reset_pci_bus(pdev, mmio);
1564 }
1565
1566 static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1567 {
1568 writel(0x0fcfffff, mmio + MV_FLASH_CTL);
1569 }
1570
1571 static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
1572 void __iomem *mmio)
1573 {
1574 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
1575 u32 tmp;
1576
1577 tmp = readl(phy_mmio + MV5_PHY_MODE);
1578
1579 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
1580 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
1581 }
1582
1583 static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1584 {
1585 u32 tmp;
1586
1587 writel(0, mmio + MV_GPIO_PORT_CTL);
1588
1589 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
1590
1591 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
1592 tmp |= ~(1 << 0);
1593 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
1594 }
1595
1596 static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1597 unsigned int port)
1598 {
1599 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
1600 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
1601 u32 tmp;
1602 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
1603
1604 if (fix_apm_sq) {
1605 tmp = readl(phy_mmio + MV5_LT_MODE);
1606 tmp |= (1 << 19);
1607 writel(tmp, phy_mmio + MV5_LT_MODE);
1608
1609 tmp = readl(phy_mmio + MV5_PHY_CTL);
1610 tmp &= ~0x3;
1611 tmp |= 0x1;
1612 writel(tmp, phy_mmio + MV5_PHY_CTL);
1613 }
1614
1615 tmp = readl(phy_mmio + MV5_PHY_MODE);
1616 tmp &= ~mask;
1617 tmp |= hpriv->signal[port].pre;
1618 tmp |= hpriv->signal[port].amps;
1619 writel(tmp, phy_mmio + MV5_PHY_MODE);
1620 }
1621
1622
1623 #undef ZERO
1624 #define ZERO(reg) writel(0, port_mmio + (reg))
1625 static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
1626 unsigned int port)
1627 {
1628 void __iomem *port_mmio = mv_port_base(mmio, port);
1629
1630 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
1631
1632 mv_channel_reset(hpriv, mmio, port);
1633
1634 ZERO(0x028); /* command */
1635 writel(0x11f, port_mmio + EDMA_CFG_OFS);
1636 ZERO(0x004); /* timer */
1637 ZERO(0x008); /* irq err cause */
1638 ZERO(0x00c); /* irq err mask */
1639 ZERO(0x010); /* rq bah */
1640 ZERO(0x014); /* rq inp */
1641 ZERO(0x018); /* rq outp */
1642 ZERO(0x01c); /* respq bah */
1643 ZERO(0x024); /* respq outp */
1644 ZERO(0x020); /* respq inp */
1645 ZERO(0x02c); /* test control */
1646 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
1647 }
1648 #undef ZERO
1649
1650 #define ZERO(reg) writel(0, hc_mmio + (reg))
1651 static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1652 unsigned int hc)
1653 {
1654 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1655 u32 tmp;
1656
1657 ZERO(0x00c);
1658 ZERO(0x010);
1659 ZERO(0x014);
1660 ZERO(0x018);
1661
1662 tmp = readl(hc_mmio + 0x20);
1663 tmp &= 0x1c1c1c1c;
1664 tmp |= 0x03030303;
1665 writel(tmp, hc_mmio + 0x20);
1666 }
1667 #undef ZERO
1668
1669 static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1670 unsigned int n_hc)
1671 {
1672 unsigned int hc, port;
1673
1674 for (hc = 0; hc < n_hc; hc++) {
1675 for (port = 0; port < MV_PORTS_PER_HC; port++)
1676 mv5_reset_hc_port(hpriv, mmio,
1677 (hc * MV_PORTS_PER_HC) + port);
1678
1679 mv5_reset_one_hc(hpriv, mmio, hc);
1680 }
1681
1682 return 0;
1683 }
1684
1685 #undef ZERO
1686 #define ZERO(reg) writel(0, mmio + (reg))
1687 static void mv_reset_pci_bus(struct pci_dev *pdev, void __iomem *mmio)
1688 {
1689 u32 tmp;
1690
1691 tmp = readl(mmio + MV_PCI_MODE);
1692 tmp &= 0xff00ffff;
1693 writel(tmp, mmio + MV_PCI_MODE);
1694
1695 ZERO(MV_PCI_DISC_TIMER);
1696 ZERO(MV_PCI_MSI_TRIGGER);
1697 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
1698 ZERO(HC_MAIN_IRQ_MASK_OFS);
1699 ZERO(MV_PCI_SERR_MASK);
1700 ZERO(PCI_IRQ_CAUSE_OFS);
1701 ZERO(PCI_IRQ_MASK_OFS);
1702 ZERO(MV_PCI_ERR_LOW_ADDRESS);
1703 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
1704 ZERO(MV_PCI_ERR_ATTRIBUTE);
1705 ZERO(MV_PCI_ERR_COMMAND);
1706 }
1707 #undef ZERO
1708
1709 static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
1710 {
1711 u32 tmp;
1712
1713 mv5_reset_flash(hpriv, mmio);
1714
1715 tmp = readl(mmio + MV_GPIO_PORT_CTL);
1716 tmp &= 0x3;
1717 tmp |= (1 << 5) | (1 << 6);
1718 writel(tmp, mmio + MV_GPIO_PORT_CTL);
1719 }
1720
1721 /**
1722 * mv6_reset_hc - Perform the 6xxx global soft reset
1723 * @mmio: base address of the HBA
1724 *
1725 * This routine only applies to 6xxx parts.
1726 *
1727 * LOCKING:
1728 * Inherited from caller.
1729 */
1730 static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
1731 unsigned int n_hc)
1732 {
1733 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
1734 int i, rc = 0;
1735 u32 t;
1736
1737 /* Following procedure defined in PCI "main command and status
1738 * register" table.
1739 */
1740 t = readl(reg);
1741 writel(t | STOP_PCI_MASTER, reg);
1742
1743 for (i = 0; i < 1000; i++) {
1744 udelay(1);
1745 t = readl(reg);
1746 if (PCI_MASTER_EMPTY & t) {
1747 break;
1748 }
1749 }
1750 if (!(PCI_MASTER_EMPTY & t)) {
1751 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
1752 rc = 1;
1753 goto done;
1754 }
1755
1756 /* set reset */
1757 i = 5;
1758 do {
1759 writel(t | GLOB_SFT_RST, reg);
1760 t = readl(reg);
1761 udelay(1);
1762 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
1763
1764 if (!(GLOB_SFT_RST & t)) {
1765 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
1766 rc = 1;
1767 goto done;
1768 }
1769
1770 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
1771 i = 5;
1772 do {
1773 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
1774 t = readl(reg);
1775 udelay(1);
1776 } while ((GLOB_SFT_RST & t) && (i-- > 0));
1777
1778 if (GLOB_SFT_RST & t) {
1779 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
1780 rc = 1;
1781 }
1782 done:
1783 return rc;
1784 }
1785
1786 static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
1787 void __iomem *mmio)
1788 {
1789 void __iomem *port_mmio;
1790 u32 tmp;
1791
1792 tmp = readl(mmio + MV_RESET_CFG);
1793 if ((tmp & (1 << 0)) == 0) {
1794 hpriv->signal[idx].amps = 0x7 << 8;
1795 hpriv->signal[idx].pre = 0x1 << 5;
1796 return;
1797 }
1798
1799 port_mmio = mv_port_base(mmio, idx);
1800 tmp = readl(port_mmio + PHY_MODE2);
1801
1802 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
1803 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
1804 }
1805
1806 static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
1807 {
1808 writel(0x00000060, mmio + MV_GPIO_PORT_CTL);
1809 }
1810
1811 static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
1812 unsigned int port)
1813 {
1814 void __iomem *port_mmio = mv_port_base(mmio, port);
1815
1816 u32 hp_flags = hpriv->hp_flags;
1817 int fix_phy_mode2 =
1818 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1819 int fix_phy_mode4 =
1820 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
1821 u32 m2, tmp;
1822
1823 if (fix_phy_mode2) {
1824 m2 = readl(port_mmio + PHY_MODE2);
1825 m2 &= ~(1 << 16);
1826 m2 |= (1 << 31);
1827 writel(m2, port_mmio + PHY_MODE2);
1828
1829 udelay(200);
1830
1831 m2 = readl(port_mmio + PHY_MODE2);
1832 m2 &= ~((1 << 16) | (1 << 31));
1833 writel(m2, port_mmio + PHY_MODE2);
1834
1835 udelay(200);
1836 }
1837
1838 /* who knows what this magic does */
1839 tmp = readl(port_mmio + PHY_MODE3);
1840 tmp &= ~0x7F800000;
1841 tmp |= 0x2A800000;
1842 writel(tmp, port_mmio + PHY_MODE3);
1843
1844 if (fix_phy_mode4) {
1845 u32 m4;
1846
1847 m4 = readl(port_mmio + PHY_MODE4);
1848
1849 if (hp_flags & MV_HP_ERRATA_60X1B2)
1850 tmp = readl(port_mmio + 0x310);
1851
1852 m4 = (m4 & ~(1 << 1)) | (1 << 0);
1853
1854 writel(m4, port_mmio + PHY_MODE4);
1855
1856 if (hp_flags & MV_HP_ERRATA_60X1B2)
1857 writel(tmp, port_mmio + 0x310);
1858 }
1859
1860 /* Revert values of pre-emphasis and signal amps to the saved ones */
1861 m2 = readl(port_mmio + PHY_MODE2);
1862
1863 m2 &= ~MV_M2_PREAMP_MASK;
1864 m2 |= hpriv->signal[port].amps;
1865 m2 |= hpriv->signal[port].pre;
1866 m2 &= ~(1 << 16);
1867
1868 /* according to mvSata 3.6.1, some IIE values are fixed */
1869 if (IS_GEN_IIE(hpriv)) {
1870 m2 &= ~0xC30FF01F;
1871 m2 |= 0x0000900F;
1872 }
1873
1874 writel(m2, port_mmio + PHY_MODE2);
1875 }
1876
1877 static void mv_channel_reset(struct mv_host_priv *hpriv, void __iomem *mmio,
1878 unsigned int port_no)
1879 {
1880 void __iomem *port_mmio = mv_port_base(mmio, port_no);
1881
1882 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1883
1884 if (IS_60XX(hpriv)) {
1885 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
1886 ifctl |= (1 << 7); /* enable gen2i speed */
1887 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
1888 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
1889 }
1890
1891 udelay(25); /* allow reset propagation */
1892
1893 /* Spec never mentions clearing the bit. Marvell's driver does
1894 * clear the bit, however.
1895 */
1896 writelfl(0, port_mmio + EDMA_CMD_OFS);
1897
1898 hpriv->ops->phy_errata(hpriv, mmio, port_no);
1899
1900 if (IS_50XX(hpriv))
1901 mdelay(1);
1902 }
1903
1904 static void mv_stop_and_reset(struct ata_port *ap)
1905 {
1906 struct mv_host_priv *hpriv = ap->host->private_data;
1907 void __iomem *mmio = ap->host->mmio_base;
1908
1909 mv_stop_dma(ap);
1910
1911 mv_channel_reset(hpriv, mmio, ap->port_no);
1912
1913 __mv_phy_reset(ap, 0);
1914 }
1915
1916 static inline void __msleep(unsigned int msec, int can_sleep)
1917 {
1918 if (can_sleep)
1919 msleep(msec);
1920 else
1921 mdelay(msec);
1922 }
1923
1924 /**
1925 * __mv_phy_reset - Perform eDMA reset followed by COMRESET
1926 * @ap: ATA channel to manipulate
1927 *
1928 * Part of this is taken from __sata_phy_reset and modified to
1929 * not sleep since this routine gets called from interrupt level.
1930 *
1931 * LOCKING:
1932 * Inherited from caller. This is coded to safe to call at
1933 * interrupt level, i.e. it does not sleep.
1934 */
1935 static void __mv_phy_reset(struct ata_port *ap, int can_sleep)
1936 {
1937 struct mv_port_priv *pp = ap->private_data;
1938 struct mv_host_priv *hpriv = ap->host->private_data;
1939 void __iomem *port_mmio = mv_ap_base(ap);
1940 struct ata_taskfile tf;
1941 struct ata_device *dev = &ap->device[0];
1942 unsigned long timeout;
1943 int retry = 5;
1944 u32 sstatus;
1945
1946 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1947
1948 DPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1949 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1950 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1951
1952 /* Issue COMRESET via SControl */
1953 comreset_retry:
1954 sata_scr_write_flush(ap, SCR_CONTROL, 0x301);
1955 __msleep(1, can_sleep);
1956
1957 sata_scr_write_flush(ap, SCR_CONTROL, 0x300);
1958 __msleep(20, can_sleep);
1959
1960 timeout = jiffies + msecs_to_jiffies(200);
1961 do {
1962 sata_scr_read(ap, SCR_STATUS, &sstatus);
1963 if (((sstatus & 0x3) == 3) || ((sstatus & 0x3) == 0))
1964 break;
1965
1966 __msleep(1, can_sleep);
1967 } while (time_before(jiffies, timeout));
1968
1969 /* work around errata */
1970 if (IS_60XX(hpriv) &&
1971 (sstatus != 0x0) && (sstatus != 0x113) && (sstatus != 0x123) &&
1972 (retry-- > 0))
1973 goto comreset_retry;
1974
1975 DPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1976 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1977 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1978
1979 if (ata_port_online(ap)) {
1980 ata_port_probe(ap);
1981 } else {
1982 sata_scr_read(ap, SCR_STATUS, &sstatus);
1983 ata_port_printk(ap, KERN_INFO,
1984 "no device found (phy stat %08x)\n", sstatus);
1985 ata_port_disable(ap);
1986 return;
1987 }
1988 ap->cbl = ATA_CBL_SATA;
1989
1990 /* even after SStatus reflects that device is ready,
1991 * it seems to take a while for link to be fully
1992 * established (and thus Status no longer 0x80/0x7F),
1993 * so we poll a bit for that, here.
1994 */
1995 retry = 20;
1996 while (1) {
1997 u8 drv_stat = ata_check_status(ap);
1998 if ((drv_stat != 0x80) && (drv_stat != 0x7f))
1999 break;
2000 __msleep(500, can_sleep);
2001 if (retry-- <= 0)
2002 break;
2003 }
2004
2005 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
2006 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
2007 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
2008 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
2009
2010 dev->class = ata_dev_classify(&tf);
2011 if (!ata_dev_enabled(dev)) {
2012 VPRINTK("Port disabled post-sig: No device present.\n");
2013 ata_port_disable(ap);
2014 }
2015
2016 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2017
2018 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
2019
2020 VPRINTK("EXIT\n");
2021 }
2022
2023 static void mv_phy_reset(struct ata_port *ap)
2024 {
2025 __mv_phy_reset(ap, 1);
2026 }
2027
2028 /**
2029 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
2030 * @ap: ATA channel to manipulate
2031 *
2032 * Intent is to clear all pending error conditions, reset the
2033 * chip/bus, fail the command, and move on.
2034 *
2035 * LOCKING:
2036 * This routine holds the host lock while failing the command.
2037 */
2038 static void mv_eng_timeout(struct ata_port *ap)
2039 {
2040 struct ata_queued_cmd *qc;
2041 unsigned long flags;
2042
2043 ata_port_printk(ap, KERN_ERR, "Entering mv_eng_timeout\n");
2044 DPRINTK("All regs @ start of eng_timeout\n");
2045 mv_dump_all_regs(ap->host->mmio_base, ap->port_no,
2046 to_pci_dev(ap->host->dev));
2047
2048 qc = ata_qc_from_tag(ap, ap->active_tag);
2049 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
2050 ap->host->mmio_base, ap, qc, qc->scsicmd, &qc->scsicmd->cmnd);
2051
2052 spin_lock_irqsave(&ap->host->lock, flags);
2053 mv_err_intr(ap, 0);
2054 mv_stop_and_reset(ap);
2055 spin_unlock_irqrestore(&ap->host->lock, flags);
2056
2057 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
2058 if (qc->flags & ATA_QCFLAG_ACTIVE) {
2059 qc->err_mask |= AC_ERR_TIMEOUT;
2060 ata_eh_qc_complete(qc);
2061 }
2062 }
2063
2064 /**
2065 * mv_port_init - Perform some early initialization on a single port.
2066 * @port: libata data structure storing shadow register addresses
2067 * @port_mmio: base address of the port
2068 *
2069 * Initialize shadow register mmio addresses, clear outstanding
2070 * interrupts on the port, and unmask interrupts for the future
2071 * start of the port.
2072 *
2073 * LOCKING:
2074 * Inherited from caller.
2075 */
2076 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
2077 {
2078 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
2079 unsigned serr_ofs;
2080
2081 /* PIO related setup
2082 */
2083 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
2084 port->error_addr =
2085 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2086 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2087 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2088 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2089 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2090 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
2091 port->status_addr =
2092 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2093 /* special case: control/altstatus doesn't have ATA_REG_ address */
2094 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2095
2096 /* unused: */
2097 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
2098
2099 /* Clear any currently outstanding port interrupt conditions */
2100 serr_ofs = mv_scr_offset(SCR_ERROR);
2101 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2102 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2103
2104 /* unmask all EDMA error interrupts */
2105 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
2106
2107 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
2108 readl(port_mmio + EDMA_CFG_OFS),
2109 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2110 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
2111 }
2112
2113 static int mv_chip_id(struct pci_dev *pdev, struct mv_host_priv *hpriv,
2114 unsigned int board_idx)
2115 {
2116 u8 rev_id;
2117 u32 hp_flags = hpriv->hp_flags;
2118
2119 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2120
2121 switch(board_idx) {
2122 case chip_5080:
2123 hpriv->ops = &mv5xxx_ops;
2124 hp_flags |= MV_HP_50XX;
2125
2126 switch (rev_id) {
2127 case 0x1:
2128 hp_flags |= MV_HP_ERRATA_50XXB0;
2129 break;
2130 case 0x3:
2131 hp_flags |= MV_HP_ERRATA_50XXB2;
2132 break;
2133 default:
2134 dev_printk(KERN_WARNING, &pdev->dev,
2135 "Applying 50XXB2 workarounds to unknown rev\n");
2136 hp_flags |= MV_HP_ERRATA_50XXB2;
2137 break;
2138 }
2139 break;
2140
2141 case chip_504x:
2142 case chip_508x:
2143 hpriv->ops = &mv5xxx_ops;
2144 hp_flags |= MV_HP_50XX;
2145
2146 switch (rev_id) {
2147 case 0x0:
2148 hp_flags |= MV_HP_ERRATA_50XXB0;
2149 break;
2150 case 0x3:
2151 hp_flags |= MV_HP_ERRATA_50XXB2;
2152 break;
2153 default:
2154 dev_printk(KERN_WARNING, &pdev->dev,
2155 "Applying B2 workarounds to unknown rev\n");
2156 hp_flags |= MV_HP_ERRATA_50XXB2;
2157 break;
2158 }
2159 break;
2160
2161 case chip_604x:
2162 case chip_608x:
2163 hpriv->ops = &mv6xxx_ops;
2164
2165 switch (rev_id) {
2166 case 0x7:
2167 hp_flags |= MV_HP_ERRATA_60X1B2;
2168 break;
2169 case 0x9:
2170 hp_flags |= MV_HP_ERRATA_60X1C0;
2171 break;
2172 default:
2173 dev_printk(KERN_WARNING, &pdev->dev,
2174 "Applying B2 workarounds to unknown rev\n");
2175 hp_flags |= MV_HP_ERRATA_60X1B2;
2176 break;
2177 }
2178 break;
2179
2180 case chip_7042:
2181 case chip_6042:
2182 hpriv->ops = &mv6xxx_ops;
2183
2184 hp_flags |= MV_HP_GEN_IIE;
2185
2186 switch (rev_id) {
2187 case 0x0:
2188 hp_flags |= MV_HP_ERRATA_XX42A0;
2189 break;
2190 case 0x1:
2191 hp_flags |= MV_HP_ERRATA_60X1C0;
2192 break;
2193 default:
2194 dev_printk(KERN_WARNING, &pdev->dev,
2195 "Applying 60X1C0 workarounds to unknown rev\n");
2196 hp_flags |= MV_HP_ERRATA_60X1C0;
2197 break;
2198 }
2199 break;
2200
2201 default:
2202 printk(KERN_ERR DRV_NAME ": BUG: invalid board index %u\n", board_idx);
2203 return 1;
2204 }
2205
2206 hpriv->hp_flags = hp_flags;
2207
2208 return 0;
2209 }
2210
2211 /**
2212 * mv_init_host - Perform some early initialization of the host.
2213 * @pdev: host PCI device
2214 * @probe_ent: early data struct representing the host
2215 *
2216 * If possible, do an early global reset of the host. Then do
2217 * our port init and clear/unmask all/relevant host interrupts.
2218 *
2219 * LOCKING:
2220 * Inherited from caller.
2221 */
2222 static int mv_init_host(struct pci_dev *pdev, struct ata_probe_ent *probe_ent,
2223 unsigned int board_idx)
2224 {
2225 int rc = 0, n_hc, port, hc;
2226 void __iomem *mmio = probe_ent->mmio_base;
2227 struct mv_host_priv *hpriv = probe_ent->private_data;
2228
2229 /* global interrupt mask */
2230 writel(0, mmio + HC_MAIN_IRQ_MASK_OFS);
2231
2232 rc = mv_chip_id(pdev, hpriv, board_idx);
2233 if (rc)
2234 goto done;
2235
2236 n_hc = mv_get_hc_count(probe_ent->port_flags);
2237 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
2238
2239 for (port = 0; port < probe_ent->n_ports; port++)
2240 hpriv->ops->read_preamp(hpriv, port, mmio);
2241
2242 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
2243 if (rc)
2244 goto done;
2245
2246 hpriv->ops->reset_flash(hpriv, mmio);
2247 hpriv->ops->reset_bus(pdev, mmio);
2248 hpriv->ops->enable_leds(hpriv, mmio);
2249
2250 for (port = 0; port < probe_ent->n_ports; port++) {
2251 if (IS_60XX(hpriv)) {
2252 void __iomem *port_mmio = mv_port_base(mmio, port);
2253
2254 u32 ifctl = readl(port_mmio + SATA_INTERFACE_CTL);
2255 ifctl |= (1 << 7); /* enable gen2i speed */
2256 ifctl = (ifctl & 0xfff) | 0x9b1000; /* from chip spec */
2257 writelfl(ifctl, port_mmio + SATA_INTERFACE_CTL);
2258 }
2259
2260 hpriv->ops->phy_errata(hpriv, mmio, port);
2261 }
2262
2263 for (port = 0; port < probe_ent->n_ports; port++) {
2264 void __iomem *port_mmio = mv_port_base(mmio, port);
2265 mv_port_init(&probe_ent->port[port], port_mmio);
2266 }
2267
2268 for (hc = 0; hc < n_hc; hc++) {
2269 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2270
2271 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
2272 "(before clear)=0x%08x\n", hc,
2273 readl(hc_mmio + HC_CFG_OFS),
2274 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
2275
2276 /* Clear any currently outstanding hc interrupt conditions */
2277 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
2278 }
2279
2280 /* Clear any currently outstanding host interrupt conditions */
2281 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
2282
2283 /* and unmask interrupt generation for host regs */
2284 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
2285 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
2286
2287 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
2288 "PCI int cause/mask=0x%08x/0x%08x\n",
2289 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
2290 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
2291 readl(mmio + PCI_IRQ_CAUSE_OFS),
2292 readl(mmio + PCI_IRQ_MASK_OFS));
2293
2294 done:
2295 return rc;
2296 }
2297
2298 /**
2299 * mv_print_info - Dump key info to kernel log for perusal.
2300 * @probe_ent: early data struct representing the host
2301 *
2302 * FIXME: complete this.
2303 *
2304 * LOCKING:
2305 * Inherited from caller.
2306 */
2307 static void mv_print_info(struct ata_probe_ent *probe_ent)
2308 {
2309 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
2310 struct mv_host_priv *hpriv = probe_ent->private_data;
2311 u8 rev_id, scc;
2312 const char *scc_s;
2313
2314 /* Use this to determine the HW stepping of the chip so we know
2315 * what errata to workaround
2316 */
2317 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
2318
2319 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
2320 if (scc == 0)
2321 scc_s = "SCSI";
2322 else if (scc == 0x01)
2323 scc_s = "RAID";
2324 else
2325 scc_s = "unknown";
2326
2327 dev_printk(KERN_INFO, &pdev->dev,
2328 "%u slots %u ports %s mode IRQ via %s\n",
2329 (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
2330 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
2331 }
2332
2333 /**
2334 * mv_init_one - handle a positive probe of a Marvell host
2335 * @pdev: PCI device found
2336 * @ent: PCI device ID entry for the matched host
2337 *
2338 * LOCKING:
2339 * Inherited from caller.
2340 */
2341 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2342 {
2343 static int printed_version = 0;
2344 struct ata_probe_ent *probe_ent = NULL;
2345 struct mv_host_priv *hpriv;
2346 unsigned int board_idx = (unsigned int)ent->driver_data;
2347 void __iomem *mmio_base;
2348 int pci_dev_busy = 0, rc;
2349
2350 if (!printed_version++)
2351 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2352
2353 rc = pci_enable_device(pdev);
2354 if (rc) {
2355 return rc;
2356 }
2357 pci_set_master(pdev);
2358
2359 rc = pci_request_regions(pdev, DRV_NAME);
2360 if (rc) {
2361 pci_dev_busy = 1;
2362 goto err_out;
2363 }
2364
2365 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
2366 if (probe_ent == NULL) {
2367 rc = -ENOMEM;
2368 goto err_out_regions;
2369 }
2370
2371 memset(probe_ent, 0, sizeof(*probe_ent));
2372 probe_ent->dev = pci_dev_to_dev(pdev);
2373 INIT_LIST_HEAD(&probe_ent->node);
2374
2375 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
2376 if (mmio_base == NULL) {
2377 rc = -ENOMEM;
2378 goto err_out_free_ent;
2379 }
2380
2381 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
2382 if (!hpriv) {
2383 rc = -ENOMEM;
2384 goto err_out_iounmap;
2385 }
2386 memset(hpriv, 0, sizeof(*hpriv));
2387
2388 probe_ent->sht = mv_port_info[board_idx].sht;
2389 probe_ent->port_flags = mv_port_info[board_idx].flags;
2390 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
2391 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
2392 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
2393
2394 probe_ent->irq = pdev->irq;
2395 probe_ent->irq_flags = IRQF_SHARED;
2396 probe_ent->mmio_base = mmio_base;
2397 probe_ent->private_data = hpriv;
2398
2399 /* initialize adapter */
2400 rc = mv_init_host(pdev, probe_ent, board_idx);
2401 if (rc) {
2402 goto err_out_hpriv;
2403 }
2404
2405 /* Enable interrupts */
2406 if (msi && pci_enable_msi(pdev) == 0) {
2407 hpriv->hp_flags |= MV_HP_FLAG_MSI;
2408 } else {
2409 pci_intx(pdev, 1);
2410 }
2411
2412 mv_dump_pci_cfg(pdev, 0x68);
2413 mv_print_info(probe_ent);
2414
2415 if (ata_device_add(probe_ent) == 0) {
2416 rc = -ENODEV; /* No devices discovered */
2417 goto err_out_dev_add;
2418 }
2419
2420 kfree(probe_ent);
2421 return 0;
2422
2423 err_out_dev_add:
2424 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
2425 pci_disable_msi(pdev);
2426 } else {
2427 pci_intx(pdev, 0);
2428 }
2429 err_out_hpriv:
2430 kfree(hpriv);
2431 err_out_iounmap:
2432 pci_iounmap(pdev, mmio_base);
2433 err_out_free_ent:
2434 kfree(probe_ent);
2435 err_out_regions:
2436 pci_release_regions(pdev);
2437 err_out:
2438 if (!pci_dev_busy) {
2439 pci_disable_device(pdev);
2440 }
2441
2442 return rc;
2443 }
2444
2445 static int __init mv_init(void)
2446 {
2447 return pci_register_driver(&mv_pci_driver);
2448 }
2449
2450 static void __exit mv_exit(void)
2451 {
2452 pci_unregister_driver(&mv_pci_driver);
2453 }
2454
2455 MODULE_AUTHOR("Brett Russ");
2456 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
2457 MODULE_LICENSE("GPL");
2458 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
2459 MODULE_VERSION(DRV_VERSION);
2460
2461 module_param(msi, int, 0444);
2462 MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
2463
2464 module_init(mv_init);
2465 module_exit(mv_exit);
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz