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MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / drivers / mtd / chips / jedec_probe.c
blob1c653bbe34ca99a12d4419fcf007cf455946297e
1 /*
2 Common Flash Interface probe code.
3 (C) 2000 Red Hat. GPL'd.
4 $Id: jedec_probe.c,v 1.66 2005/11/07 11:14:23 gleixner Exp $
5 See JEDEC (http://www.jedec.org/) standard JESD21C (section 3.5)
6 for the standard this probe goes back to.
7
8 Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
9 */
10
11 #include <linux/module.h>
12 #include <linux/init.h>
13 #include <linux/types.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <asm/io.h>
17 #include <asm/byteorder.h>
18 #include <linux/errno.h>
19 #include <linux/slab.h>
20 #include <linux/interrupt.h>
21 #include <linux/init.h>
22
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/map.h>
25 #include <linux/mtd/cfi.h>
26 #include <linux/mtd/gen_probe.h>
27
28 /* Manufacturers */
29 #define MANUFACTURER_AMD 0x0001
30 #define MANUFACTURER_ATMEL 0x001f
31 #define MANUFACTURER_FUJITSU 0x0004
32 #define MANUFACTURER_HYUNDAI 0x00AD
33 #define MANUFACTURER_INTEL 0x0089
34 #define MANUFACTURER_MACRONIX 0x00C2
35 #define MANUFACTURER_NEC 0x0010
36 #define MANUFACTURER_PMC 0x009D
37 #define MANUFACTURER_SHARP 0x00b0
38 #define MANUFACTURER_SST 0x00BF
39 #define MANUFACTURER_ST 0x0020
40 #define MANUFACTURER_TOSHIBA 0x0098
41 #define MANUFACTURER_WINBOND 0x00da
42
43
44 /* AMD */
45 #define AM29DL800BB 0x22C8
46 #define AM29DL800BT 0x224A
47
48 #define AM29F800BB 0x2258
49 #define AM29F800BT 0x22D6
50 #define AM29LV400BB 0x22BA
51 #define AM29LV400BT 0x22B9
52 #define AM29LV800BB 0x225B
53 #define AM29LV800BT 0x22DA
54 #define AM29LV160DT 0x22C4
55 #define AM29LV160DB 0x2249
56 #define AM29BDD160GB 0x7E08
57 #define AM29F017D 0x003D
58 #define AM29F016D 0x00AD
59 #define AM29F080 0x00D5
60 #define AM29F040 0x00A4
61 #define AM29LV040B 0x004F
62 #define AM29F032B 0x0041
63 #define AM29LV065D 0x0093
64 #define AM29DL323GB 0x2253
65 #define AM29F002T 0x00B0
66 #define AM29LV004T 0x00B5
67 #define AM29LV004B 0x00B6
68
69 /* Atmel */
70 #define AT49BV512 0x0003
71 #define AT29LV512 0x003d
72 #define AT49BV16X 0x00C0
73 #define AT49BV16XT 0x00C2
74 #define AT49BV32X 0x00C8
75 #define AT49BV32XT 0x00C9
76
77 /* Fujitsu */
78 #define MBM29F040C 0x00A4
79 #define MBM29LV650UE 0x22D7
80 #define MBM29LV320TE 0x22F6
81 #define MBM29LV320BE 0x22F9
82 #define MBM29LV160TE 0x22C4
83 #define MBM29LV160BE 0x2249
84 #define MBM29LV800BA 0x225B
85 #define MBM29LV800TA 0x22DA
86 #define MBM29LV400TC 0x22B9
87 #define MBM29LV400BC 0x22BA
88
89 /* Hyundai */
90 #define HY29F002T 0x00B0
91
92 /* Intel */
93 #define I28F004B3T 0x00d4
94 #define I28F004B3B 0x00d5
95 #define I28F400B3T 0x8894
96 #define I28F400B3B 0x8895
97 #define I28F008S5 0x00a6
98 #define I28F016S5 0x00a0
99 #define I28F008SA 0x00a2
100 #define I28F008B3T 0x00d2
101 #define I28F008B3B 0x00d3
102 #define I28F800B3T 0x8892
103 #define I28F800B3B 0x8893
104 #define I28F016S3 0x00aa
105 #define I28F016B3T 0x00d0
106 #define I28F016B3B 0x00d1
107 #define I28F160B3T 0x8890
108 #define I28F160B3B 0x8891
109 #define I28F320B3T 0x8896
110 #define I28F320B3B 0x8897
111 #define I28F640B3T 0x8898
112 #define I28F640B3B 0x8899
113 #define I82802AB 0x00ad
114 #define I82802AC 0x00ac
115
116 /* Macronix */
117 #define MX29LV040C 0x004F
118 #define MX29LV160T 0x22C4
119 #define MX29LV160B 0x2249
120 #define MX29F040 0x00A4
121 #define MX29F016 0x00AD
122 #define MX29F002T 0x00B0
123 #define MX29F004T 0x0045
124 #define MX29F004B 0x0046
125
126 /* NEC */
127 #define UPD29F064115 0x221C
128
129 /* PMC */
130 #define PM49FL002 0x006D
131 #define PM49FL004 0x006E
132 #define PM49FL008 0x006A
133
134 /* Sharp */
135 #define LH28F640BF 0x00b0
136
137 /* ST - www.st.com */
138 #define M29W800DT 0x00D7
139 #define M29W800DB 0x005B
140 #define M29W160DT 0x22C4
141 #define M29W160DB 0x2249
142 #define M29W040B 0x00E3
143 #define M50FW040 0x002C
144 #define M50FW080 0x002D
145 #define M50FW016 0x002E
146 #define M50LPW080 0x002F
147
148 /* SST */
149 #define SST29EE020 0x0010
150 #define SST29LE020 0x0012
151 #define SST29EE512 0x005d
152 #define SST29LE512 0x003d
153 #define SST39LF800 0x2781
154 #define SST39LF160 0x2782
155 #define SST39VF1601 0x234b
156 #define SST39LF512 0x00D4
157 #define SST39LF010 0x00D5
158 #define SST39LF020 0x00D6
159 #define SST39LF040 0x00D7
160 #define SST39SF010A 0x00B5
161 #define SST39SF020A 0x00B6
162 #define SST49LF004B 0x0060
163 #define SST49LF008A 0x005a
164 #define SST49LF030A 0x001C
165 #define SST49LF040A 0x0051
166 #define SST49LF080A 0x005B
167
168 /* Toshiba */
169 #define TC58FVT160 0x00C2
170 #define TC58FVB160 0x0043
171 #define TC58FVT321 0x009A
172 #define TC58FVB321 0x009C
173 #define TC58FVT641 0x0093
174 #define TC58FVB641 0x0095
175
176 /* Winbond */
177 #define W49V002A 0x00b0
178
179
180 /*
181 * Unlock address sets for AMD command sets.
182 * Intel command sets use the MTD_UADDR_UNNECESSARY.
183 * Each identifier, except MTD_UADDR_UNNECESSARY, and
184 * MTD_UADDR_NO_SUPPORT must be defined below in unlock_addrs[].
185 * MTD_UADDR_NOT_SUPPORTED must be 0 so that structure
186 * initialization need not require initializing all of the
187 * unlock addresses for all bit widths.
188 */
189 enum uaddr {
190 MTD_UADDR_NOT_SUPPORTED = 0, /* data width not supported */
191 MTD_UADDR_0x0555_0x02AA,
192 MTD_UADDR_0x0555_0x0AAA,
193 MTD_UADDR_0x5555_0x2AAA,
194 MTD_UADDR_0x0AAA_0x0555,
195 MTD_UADDR_DONT_CARE, /* Requires an arbitrary address */
196 MTD_UADDR_UNNECESSARY, /* Does not require any address */
197 };
198
199
200 struct unlock_addr {
201 u32 addr1;
202 u32 addr2;
203 };
204
205
206 /*
207 * I don't like the fact that the first entry in unlock_addrs[]
208 * exists, but is for MTD_UADDR_NOT_SUPPORTED - and, therefore,
209 * should not be used. The problem is that structures with
210 * initializers have extra fields initialized to 0. It is _very_
211 * desireable to have the unlock address entries for unsupported
212 * data widths automatically initialized - that means that
213 * MTD_UADDR_NOT_SUPPORTED must be 0 and the first entry here
214 * must go unused.
215 */
216 static const struct unlock_addr unlock_addrs[] = {
217 [MTD_UADDR_NOT_SUPPORTED] = {
218 .addr1 = 0xffff,
219 .addr2 = 0xffff
220 },
221
222 [MTD_UADDR_0x0555_0x02AA] = {
223 .addr1 = 0x0555,
224 .addr2 = 0x02aa
225 },
226
227 [MTD_UADDR_0x0555_0x0AAA] = {
228 .addr1 = 0x0555,
229 .addr2 = 0x0aaa
230 },
231
232 [MTD_UADDR_0x5555_0x2AAA] = {
233 .addr1 = 0x5555,
234 .addr2 = 0x2aaa
235 },
236
237 [MTD_UADDR_0x0AAA_0x0555] = {
238 .addr1 = 0x0AAA,
239 .addr2 = 0x0555
240 },
241
242 [MTD_UADDR_DONT_CARE] = {
243 .addr1 = 0x0000, /* Doesn't matter which address */
244 .addr2 = 0x0000 /* is used - must be last entry */
245 },
246
247 [MTD_UADDR_UNNECESSARY] = {
248 .addr1 = 0x0000,
249 .addr2 = 0x0000
250 }
251 };
252
253
254 struct amd_flash_info {
255 const __u16 mfr_id;
256 const __u16 dev_id;
257 const char *name;
258 const int DevSize;
259 const int NumEraseRegions;
260 const int CmdSet;
261 const __u8 uaddr[4]; /* unlock addrs for 8, 16, 32, 64 */
262 const ulong regions[6];
263 };
264
265 #define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
266
267 #define SIZE_64KiB 16
268 #define SIZE_128KiB 17
269 #define SIZE_256KiB 18
270 #define SIZE_512KiB 19
271 #define SIZE_1MiB 20
272 #define SIZE_2MiB 21
273 #define SIZE_4MiB 22
274 #define SIZE_8MiB 23
275
276
277 /*
278 * Please keep this list ordered by manufacturer!
279 * Fortunately, the list isn't searched often and so a
280 * slow, linear search isn't so bad.
281 */
282 static const struct amd_flash_info jedec_table[] = {
283 {
284 .mfr_id = MANUFACTURER_AMD,
285 .dev_id = AM29LV004T,
286 .name = "AMD AM29LV004T",
287 .uaddr = {
288 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
289 },
290 .DevSize = SIZE_512KiB,
291 .CmdSet = P_ID_AMD_STD,
292 .NumEraseRegions= 4,
293 .regions = {
294 ERASEINFO(0x10000,7),
295 ERASEINFO(0x08000,1),
296 ERASEINFO(0x02000,2),
297 ERASEINFO(0x04000,1)
298 }
299 }, {
300 .mfr_id = MANUFACTURER_AMD,
301 .dev_id = AM29LV004B,
302 .name = "AMD AM29LV004B",
303 .uaddr = {
304 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
305 },
306 .DevSize = SIZE_512KiB,
307 .CmdSet = P_ID_AMD_STD,
308 .NumEraseRegions= 4,
309 .regions = {
310 ERASEINFO(0x04000,1),
311 ERASEINFO(0x02000,2),
312 ERASEINFO(0x08000,1),
313 ERASEINFO(0x10000,7)
314 }
315 }, {
316 .mfr_id = MANUFACTURER_AMD,
317 .dev_id = AM29LV065D,
318 .name = "AMD AM29LV065D",
319 .uaddr = {
320 [0] = MTD_UADDR_DONT_CARE /* x8 */
321 },
322 .DevSize = SIZE_8MiB,
323 .CmdSet = P_ID_AMD_STD,
324 .NumEraseRegions= 1,
325 .regions = {
326 ERASEINFO(0x10000,128)
327 }
328 },{
329 .mfr_id = MANUFACTURER_AMD,
330 .dev_id = AM29DL323GB,
331 .name = "AMD AM29DL323GB",
332 .uaddr = {
333 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
334 [1] = MTD_UADDR_0x0AAA_0x0555 /* x16 */
335 },
336 .DevSize = SIZE_4MiB,
337 .CmdSet = P_ID_AMD_STD,
338 .NumEraseRegions= 2,
339 .regions = {
340 ERASEINFO(0x2000,8),
341 ERASEINFO(0x10000,63)
342 }
343 },{
344 .mfr_id = MANUFACTURER_AMD,
345 .dev_id = AM29F032B,
346 .name = "AMD AM29F032B",
347 .uaddr = {
348 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
349 },
350 .DevSize = SIZE_4MiB,
351 .CmdSet = P_ID_AMD_STD,
352 .NumEraseRegions= 1,
353 .regions = {
354 ERASEINFO(0x10000,64)
355 }
356 }, {
357 .mfr_id = MANUFACTURER_AMD,
358 .dev_id = AM29LV160DT,
359 .name = "AMD AM29LV160DT",
360 .uaddr = {
361 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
362 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
363 },
364 .DevSize = SIZE_2MiB,
365 .CmdSet = P_ID_AMD_STD,
366 .NumEraseRegions= 4,
367 .regions = {
368 ERASEINFO(0x10000,31),
369 ERASEINFO(0x08000,1),
370 ERASEINFO(0x02000,2),
371 ERASEINFO(0x04000,1)
372 }
373 }, {
374 .mfr_id = MANUFACTURER_AMD,
375 .dev_id = AM29LV160DB,
376 .name = "AMD AM29LV160DB",
377 .uaddr = {
378 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
379 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
380 },
381 .DevSize = SIZE_2MiB,
382 .CmdSet = P_ID_AMD_STD,
383 .NumEraseRegions= 4,
384 .regions = {
385 ERASEINFO(0x04000,1),
386 ERASEINFO(0x02000,2),
387 ERASEINFO(0x08000,1),
388 ERASEINFO(0x10000,31)
389 }
390 }, {
391 .mfr_id = MANUFACTURER_AMD,
392 .dev_id = AM29BDD160GB,
393 .name = "AMD AM29BDD160GB",
394 .uaddr = {
395 [0] = MTD_UADDR_0x1554_0x0AAA /* x32 */
396 },
397 .DevSize = SIZE_2MiB,
398 .CmdSet = P_ID_AMD_STD,
399 .NumEraseRegions= 3,
400 .regions = {
401 ERASEINFO(0x01000,8),
402 ERASEINFO(0x10000,32),
403 ERASEINFO(0x01000,8)
404 }
405 }, {
406 .mfr_id = MANUFACTURER_AMD,
407 .dev_id = AM29LV400BB,
408 .name = "AMD AM29LV400BB",
409 .uaddr = {
410 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
411 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
412 },
413 .DevSize = SIZE_512KiB,
414 .CmdSet = P_ID_AMD_STD,
415 .NumEraseRegions= 4,
416 .regions = {
417 ERASEINFO(0x04000,1),
418 ERASEINFO(0x02000,2),
419 ERASEINFO(0x08000,1),
420 ERASEINFO(0x10000,7)
421 }
422 }, {
423 .mfr_id = MANUFACTURER_AMD,
424 .dev_id = AM29LV400BT,
425 .name = "AMD AM29LV400BT",
426 .uaddr = {
427 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
428 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
429 },
430 .DevSize = SIZE_512KiB,
431 .CmdSet = P_ID_AMD_STD,
432 .NumEraseRegions= 4,
433 .regions = {
434 ERASEINFO(0x10000,7),
435 ERASEINFO(0x08000,1),
436 ERASEINFO(0x02000,2),
437 ERASEINFO(0x04000,1)
438 }
439 }, {
440 .mfr_id = MANUFACTURER_AMD,
441 .dev_id = AM29LV800BB,
442 .name = "AMD AM29LV800BB",
443 .uaddr = {
444 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
445 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
446 },
447 .DevSize = SIZE_1MiB,
448 .CmdSet = P_ID_AMD_STD,
449 .NumEraseRegions= 4,
450 .regions = {
451 ERASEINFO(0x04000,1),
452 ERASEINFO(0x02000,2),
453 ERASEINFO(0x08000,1),
454 ERASEINFO(0x10000,15),
455 }
456 }, {
457 /* add DL */
458 .mfr_id = MANUFACTURER_AMD,
459 .dev_id = AM29DL800BB,
460 .name = "AMD AM29DL800BB",
461 .uaddr = {
462 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
463 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
464 },
465 .DevSize = SIZE_1MiB,
466 .CmdSet = P_ID_AMD_STD,
467 .NumEraseRegions= 6,
468 .regions = {
469 ERASEINFO(0x04000,1),
470 ERASEINFO(0x08000,1),
471 ERASEINFO(0x02000,4),
472 ERASEINFO(0x08000,1),
473 ERASEINFO(0x04000,1),
474 ERASEINFO(0x10000,14)
475 }
476 }, {
477 .mfr_id = MANUFACTURER_AMD,
478 .dev_id = AM29DL800BT,
479 .name = "AMD AM29DL800BT",
480 .uaddr = {
481 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
482 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
483 },
484 .DevSize = SIZE_1MiB,
485 .CmdSet = P_ID_AMD_STD,
486 .NumEraseRegions= 6,
487 .regions = {
488 ERASEINFO(0x10000,14),
489 ERASEINFO(0x04000,1),
490 ERASEINFO(0x08000,1),
491 ERASEINFO(0x02000,4),
492 ERASEINFO(0x08000,1),
493 ERASEINFO(0x04000,1)
494 }
495 }, {
496 .mfr_id = MANUFACTURER_AMD,
497 .dev_id = AM29F800BB,
498 .name = "AMD AM29F800BB",
499 .uaddr = {
500 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
501 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
502 },
503 .DevSize = SIZE_1MiB,
504 .CmdSet = P_ID_AMD_STD,
505 .NumEraseRegions= 4,
506 .regions = {
507 ERASEINFO(0x04000,1),
508 ERASEINFO(0x02000,2),
509 ERASEINFO(0x08000,1),
510 ERASEINFO(0x10000,15),
511 }
512 }, {
513 .mfr_id = MANUFACTURER_AMD,
514 .dev_id = AM29LV800BT,
515 .name = "AMD AM29LV800BT",
516 .uaddr = {
517 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
518 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
519 },
520 .DevSize = SIZE_1MiB,
521 .CmdSet = P_ID_AMD_STD,
522 .NumEraseRegions= 4,
523 .regions = {
524 ERASEINFO(0x10000,15),
525 ERASEINFO(0x08000,1),
526 ERASEINFO(0x02000,2),
527 ERASEINFO(0x04000,1)
528 }
529 }, {
530 .mfr_id = MANUFACTURER_AMD,
531 .dev_id = AM29F800BT,
532 .name = "AMD AM29F800BT",
533 .uaddr = {
534 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
535 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
536 },
537 .DevSize = SIZE_1MiB,
538 .CmdSet = P_ID_AMD_STD,
539 .NumEraseRegions= 4,
540 .regions = {
541 ERASEINFO(0x10000,15),
542 ERASEINFO(0x08000,1),
543 ERASEINFO(0x02000,2),
544 ERASEINFO(0x04000,1)
545 }
546 }, {
547 .mfr_id = MANUFACTURER_AMD,
548 .dev_id = AM29F017D,
549 .name = "AMD AM29F017D",
550 .uaddr = {
551 [0] = MTD_UADDR_DONT_CARE /* x8 */
552 },
553 .DevSize = SIZE_2MiB,
554 .CmdSet = P_ID_AMD_STD,
555 .NumEraseRegions= 1,
556 .regions = {
557 ERASEINFO(0x10000,32),
558 }
559 }, {
560 .mfr_id = MANUFACTURER_AMD,
561 .dev_id = AM29F016D,
562 .name = "AMD AM29F016D",
563 .uaddr = {
564 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
565 },
566 .DevSize = SIZE_2MiB,
567 .CmdSet = P_ID_AMD_STD,
568 .NumEraseRegions= 1,
569 .regions = {
570 ERASEINFO(0x10000,32),
571 }
572 }, {
573 .mfr_id = MANUFACTURER_AMD,
574 .dev_id = AM29F080,
575 .name = "AMD AM29F080",
576 .uaddr = {
577 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
578 },
579 .DevSize = SIZE_1MiB,
580 .CmdSet = P_ID_AMD_STD,
581 .NumEraseRegions= 1,
582 .regions = {
583 ERASEINFO(0x10000,16),
584 }
585 }, {
586 .mfr_id = MANUFACTURER_AMD,
587 .dev_id = AM29F040,
588 .name = "AMD AM29F040",
589 .uaddr = {
590 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
591 },
592 .DevSize = SIZE_512KiB,
593 .CmdSet = P_ID_AMD_STD,
594 .NumEraseRegions= 1,
595 .regions = {
596 ERASEINFO(0x10000,8),
597 }
598 }, {
599 .mfr_id = MANUFACTURER_AMD,
600 .dev_id = AM29LV040B,
601 .name = "AMD AM29LV040B",
602 .uaddr = {
603 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
604 },
605 .DevSize = SIZE_512KiB,
606 .CmdSet = P_ID_AMD_STD,
607 .NumEraseRegions= 1,
608 .regions = {
609 ERASEINFO(0x10000,8),
610 }
611 }, {
612 .mfr_id = MANUFACTURER_AMD,
613 .dev_id = AM29F002T,
614 .name = "AMD AM29F002T",
615 .uaddr = {
616 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
617 },
618 .DevSize = SIZE_256KiB,
619 .CmdSet = P_ID_AMD_STD,
620 .NumEraseRegions= 4,
621 .regions = {
622 ERASEINFO(0x10000,3),
623 ERASEINFO(0x08000,1),
624 ERASEINFO(0x02000,2),
625 ERASEINFO(0x04000,1),
626 }
627 }, {
628 .mfr_id = MANUFACTURER_ATMEL,
629 .dev_id = AT49BV512,
630 .name = "Atmel AT49BV512",
631 .uaddr = {
632 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
633 },
634 .DevSize = SIZE_64KiB,
635 .CmdSet = P_ID_AMD_STD,
636 .NumEraseRegions= 1,
637 .regions = {
638 ERASEINFO(0x10000,1)
639 }
640 }, {
641 .mfr_id = MANUFACTURER_ATMEL,
642 .dev_id = AT29LV512,
643 .name = "Atmel AT29LV512",
644 .uaddr = {
645 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
646 },
647 .DevSize = SIZE_64KiB,
648 .CmdSet = P_ID_AMD_STD,
649 .NumEraseRegions= 1,
650 .regions = {
651 ERASEINFO(0x80,256),
652 ERASEINFO(0x80,256)
653 }
654 }, {
655 .mfr_id = MANUFACTURER_ATMEL,
656 .dev_id = AT49BV16X,
657 .name = "Atmel AT49BV16X",
658 .uaddr = {
659 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
660 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
661 },
662 .DevSize = SIZE_2MiB,
663 .CmdSet = P_ID_AMD_STD,
664 .NumEraseRegions= 2,
665 .regions = {
666 ERASEINFO(0x02000,8),
667 ERASEINFO(0x10000,31)
668 }
669 }, {
670 .mfr_id = MANUFACTURER_ATMEL,
671 .dev_id = AT49BV16XT,
672 .name = "Atmel AT49BV16XT",
673 .uaddr = {
674 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
675 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
676 },
677 .DevSize = SIZE_2MiB,
678 .CmdSet = P_ID_AMD_STD,
679 .NumEraseRegions= 2,
680 .regions = {
681 ERASEINFO(0x10000,31),
682 ERASEINFO(0x02000,8)
683 }
684 }, {
685 .mfr_id = MANUFACTURER_ATMEL,
686 .dev_id = AT49BV32X,
687 .name = "Atmel AT49BV32X",
688 .uaddr = {
689 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
690 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
691 },
692 .DevSize = SIZE_4MiB,
693 .CmdSet = P_ID_AMD_STD,
694 .NumEraseRegions= 2,
695 .regions = {
696 ERASEINFO(0x02000,8),
697 ERASEINFO(0x10000,63)
698 }
699 }, {
700 .mfr_id = MANUFACTURER_ATMEL,
701 .dev_id = AT49BV32XT,
702 .name = "Atmel AT49BV32XT",
703 .uaddr = {
704 [0] = MTD_UADDR_0x0555_0x0AAA, /* x8 */
705 [1] = MTD_UADDR_0x0555_0x0AAA /* x16 */
706 },
707 .DevSize = SIZE_4MiB,
708 .CmdSet = P_ID_AMD_STD,
709 .NumEraseRegions= 2,
710 .regions = {
711 ERASEINFO(0x10000,63),
712 ERASEINFO(0x02000,8)
713 }
714 }, {
715 .mfr_id = MANUFACTURER_FUJITSU,
716 .dev_id = MBM29F040C,
717 .name = "Fujitsu MBM29F040C",
718 .uaddr = {
719 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
720 },
721 .DevSize = SIZE_512KiB,
722 .CmdSet = P_ID_AMD_STD,
723 .NumEraseRegions= 1,
724 .regions = {
725 ERASEINFO(0x10000,8)
726 }
727 }, {
728 .mfr_id = MANUFACTURER_FUJITSU,
729 .dev_id = MBM29LV650UE,
730 .name = "Fujitsu MBM29LV650UE",
731 .uaddr = {
732 [0] = MTD_UADDR_DONT_CARE /* x16 */
733 },
734 .DevSize = SIZE_8MiB,
735 .CmdSet = P_ID_AMD_STD,
736 .NumEraseRegions= 1,
737 .regions = {
738 ERASEINFO(0x10000,128)
739 }
740 }, {
741 .mfr_id = MANUFACTURER_FUJITSU,
742 .dev_id = MBM29LV320TE,
743 .name = "Fujitsu MBM29LV320TE",
744 .uaddr = {
745 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
746 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
747 },
748 .DevSize = SIZE_4MiB,
749 .CmdSet = P_ID_AMD_STD,
750 .NumEraseRegions= 2,
751 .regions = {
752 ERASEINFO(0x10000,63),
753 ERASEINFO(0x02000,8)
754 }
755 }, {
756 .mfr_id = MANUFACTURER_FUJITSU,
757 .dev_id = MBM29LV320BE,
758 .name = "Fujitsu MBM29LV320BE",
759 .uaddr = {
760 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
761 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
762 },
763 .DevSize = SIZE_4MiB,
764 .CmdSet = P_ID_AMD_STD,
765 .NumEraseRegions= 2,
766 .regions = {
767 ERASEINFO(0x02000,8),
768 ERASEINFO(0x10000,63)
769 }
770 }, {
771 .mfr_id = MANUFACTURER_FUJITSU,
772 .dev_id = MBM29LV160TE,
773 .name = "Fujitsu MBM29LV160TE",
774 .uaddr = {
775 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
776 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
777 },
778 .DevSize = SIZE_2MiB,
779 .CmdSet = P_ID_AMD_STD,
780 .NumEraseRegions= 4,
781 .regions = {
782 ERASEINFO(0x10000,31),
783 ERASEINFO(0x08000,1),
784 ERASEINFO(0x02000,2),
785 ERASEINFO(0x04000,1)
786 }
787 }, {
788 .mfr_id = MANUFACTURER_FUJITSU,
789 .dev_id = MBM29LV160BE,
790 .name = "Fujitsu MBM29LV160BE",
791 .uaddr = {
792 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
793 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
794 },
795 .DevSize = SIZE_2MiB,
796 .CmdSet = P_ID_AMD_STD,
797 .NumEraseRegions= 4,
798 .regions = {
799 ERASEINFO(0x04000,1),
800 ERASEINFO(0x02000,2),
801 ERASEINFO(0x08000,1),
802 ERASEINFO(0x10000,31)
803 }
804 }, {
805 .mfr_id = MANUFACTURER_FUJITSU,
806 .dev_id = MBM29LV800BA,
807 .name = "Fujitsu MBM29LV800BA",
808 .uaddr = {
809 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
810 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
811 },
812 .DevSize = SIZE_1MiB,
813 .CmdSet = P_ID_AMD_STD,
814 .NumEraseRegions= 4,
815 .regions = {
816 ERASEINFO(0x04000,1),
817 ERASEINFO(0x02000,2),
818 ERASEINFO(0x08000,1),
819 ERASEINFO(0x10000,15)
820 }
821 }, {
822 .mfr_id = MANUFACTURER_FUJITSU,
823 .dev_id = MBM29LV800TA,
824 .name = "Fujitsu MBM29LV800TA",
825 .uaddr = {
826 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
827 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
828 },
829 .DevSize = SIZE_1MiB,
830 .CmdSet = P_ID_AMD_STD,
831 .NumEraseRegions= 4,
832 .regions = {
833 ERASEINFO(0x10000,15),
834 ERASEINFO(0x08000,1),
835 ERASEINFO(0x02000,2),
836 ERASEINFO(0x04000,1)
837 }
838 }, {
839 .mfr_id = MANUFACTURER_FUJITSU,
840 .dev_id = MBM29LV400BC,
841 .name = "Fujitsu MBM29LV400BC",
842 .uaddr = {
843 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
844 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
845 },
846 .DevSize = SIZE_512KiB,
847 .CmdSet = P_ID_AMD_STD,
848 .NumEraseRegions= 4,
849 .regions = {
850 ERASEINFO(0x04000,1),
851 ERASEINFO(0x02000,2),
852 ERASEINFO(0x08000,1),
853 ERASEINFO(0x10000,7)
854 }
855 }, {
856 .mfr_id = MANUFACTURER_FUJITSU,
857 .dev_id = MBM29LV400TC,
858 .name = "Fujitsu MBM29LV400TC",
859 .uaddr = {
860 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
861 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
862 },
863 .DevSize = SIZE_512KiB,
864 .CmdSet = P_ID_AMD_STD,
865 .NumEraseRegions= 4,
866 .regions = {
867 ERASEINFO(0x10000,7),
868 ERASEINFO(0x08000,1),
869 ERASEINFO(0x02000,2),
870 ERASEINFO(0x04000,1)
871 }
872 }, {
873 .mfr_id = MANUFACTURER_HYUNDAI,
874 .dev_id = HY29F002T,
875 .name = "Hyundai HY29F002T",
876 .uaddr = {
877 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
878 },
879 .DevSize = SIZE_256KiB,
880 .CmdSet = P_ID_AMD_STD,
881 .NumEraseRegions= 4,
882 .regions = {
883 ERASEINFO(0x10000,3),
884 ERASEINFO(0x08000,1),
885 ERASEINFO(0x02000,2),
886 ERASEINFO(0x04000,1),
887 }
888 }, {
889 .mfr_id = MANUFACTURER_INTEL,
890 .dev_id = I28F004B3B,
891 .name = "Intel 28F004B3B",
892 .uaddr = {
893 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
894 },
895 .DevSize = SIZE_512KiB,
896 .CmdSet = P_ID_INTEL_STD,
897 .NumEraseRegions= 2,
898 .regions = {
899 ERASEINFO(0x02000, 8),
900 ERASEINFO(0x10000, 7),
901 }
902 }, {
903 .mfr_id = MANUFACTURER_INTEL,
904 .dev_id = I28F004B3T,
905 .name = "Intel 28F004B3T",
906 .uaddr = {
907 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
908 },
909 .DevSize = SIZE_512KiB,
910 .CmdSet = P_ID_INTEL_STD,
911 .NumEraseRegions= 2,
912 .regions = {
913 ERASEINFO(0x10000, 7),
914 ERASEINFO(0x02000, 8),
915 }
916 }, {
917 .mfr_id = MANUFACTURER_INTEL,
918 .dev_id = I28F400B3B,
919 .name = "Intel 28F400B3B",
920 .uaddr = {
921 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
922 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
923 },
924 .DevSize = SIZE_512KiB,
925 .CmdSet = P_ID_INTEL_STD,
926 .NumEraseRegions= 2,
927 .regions = {
928 ERASEINFO(0x02000, 8),
929 ERASEINFO(0x10000, 7),
930 }
931 }, {
932 .mfr_id = MANUFACTURER_INTEL,
933 .dev_id = I28F400B3T,
934 .name = "Intel 28F400B3T",
935 .uaddr = {
936 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
937 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
938 },
939 .DevSize = SIZE_512KiB,
940 .CmdSet = P_ID_INTEL_STD,
941 .NumEraseRegions= 2,
942 .regions = {
943 ERASEINFO(0x10000, 7),
944 ERASEINFO(0x02000, 8),
945 }
946 }, {
947 .mfr_id = MANUFACTURER_INTEL,
948 .dev_id = I28F008B3B,
949 .name = "Intel 28F008B3B",
950 .uaddr = {
951 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
952 },
953 .DevSize = SIZE_1MiB,
954 .CmdSet = P_ID_INTEL_STD,
955 .NumEraseRegions= 2,
956 .regions = {
957 ERASEINFO(0x02000, 8),
958 ERASEINFO(0x10000, 15),
959 }
960 }, {
961 .mfr_id = MANUFACTURER_INTEL,
962 .dev_id = I28F008B3T,
963 .name = "Intel 28F008B3T",
964 .uaddr = {
965 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
966 },
967 .DevSize = SIZE_1MiB,
968 .CmdSet = P_ID_INTEL_STD,
969 .NumEraseRegions= 2,
970 .regions = {
971 ERASEINFO(0x10000, 15),
972 ERASEINFO(0x02000, 8),
973 }
974 }, {
975 .mfr_id = MANUFACTURER_INTEL,
976 .dev_id = I28F008S5,
977 .name = "Intel 28F008S5",
978 .uaddr = {
979 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
980 },
981 .DevSize = SIZE_1MiB,
982 .CmdSet = P_ID_INTEL_EXT,
983 .NumEraseRegions= 1,
984 .regions = {
985 ERASEINFO(0x10000,16),
986 }
987 }, {
988 .mfr_id = MANUFACTURER_INTEL,
989 .dev_id = I28F016S5,
990 .name = "Intel 28F016S5",
991 .uaddr = {
992 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
993 },
994 .DevSize = SIZE_2MiB,
995 .CmdSet = P_ID_INTEL_EXT,
996 .NumEraseRegions= 1,
997 .regions = {
998 ERASEINFO(0x10000,32),
999 }
1000 }, {
1001 .mfr_id = MANUFACTURER_INTEL,
1002 .dev_id = I28F008SA,
1003 .name = "Intel 28F008SA",
1004 .uaddr = {
1005 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1006 },
1007 .DevSize = SIZE_1MiB,
1008 .CmdSet = P_ID_INTEL_STD,
1009 .NumEraseRegions= 1,
1010 .regions = {
1011 ERASEINFO(0x10000, 16),
1012 }
1013 }, {
1014 .mfr_id = MANUFACTURER_INTEL,
1015 .dev_id = I28F800B3B,
1016 .name = "Intel 28F800B3B",
1017 .uaddr = {
1018 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1019 },
1020 .DevSize = SIZE_1MiB,
1021 .CmdSet = P_ID_INTEL_STD,
1022 .NumEraseRegions= 2,
1023 .regions = {
1024 ERASEINFO(0x02000, 8),
1025 ERASEINFO(0x10000, 15),
1026 }
1027 }, {
1028 .mfr_id = MANUFACTURER_INTEL,
1029 .dev_id = I28F800B3T,
1030 .name = "Intel 28F800B3T",
1031 .uaddr = {
1032 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1033 },
1034 .DevSize = SIZE_1MiB,
1035 .CmdSet = P_ID_INTEL_STD,
1036 .NumEraseRegions= 2,
1037 .regions = {
1038 ERASEINFO(0x10000, 15),
1039 ERASEINFO(0x02000, 8),
1040 }
1041 }, {
1042 .mfr_id = MANUFACTURER_INTEL,
1043 .dev_id = I28F016B3B,
1044 .name = "Intel 28F016B3B",
1045 .uaddr = {
1046 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1047 },
1048 .DevSize = SIZE_2MiB,
1049 .CmdSet = P_ID_INTEL_STD,
1050 .NumEraseRegions= 2,
1051 .regions = {
1052 ERASEINFO(0x02000, 8),
1053 ERASEINFO(0x10000, 31),
1054 }
1055 }, {
1056 .mfr_id = MANUFACTURER_INTEL,
1057 .dev_id = I28F016S3,
1058 .name = "Intel I28F016S3",
1059 .uaddr = {
1060 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1061 },
1062 .DevSize = SIZE_2MiB,
1063 .CmdSet = P_ID_INTEL_STD,
1064 .NumEraseRegions= 1,
1065 .regions = {
1066 ERASEINFO(0x10000, 32),
1067 }
1068 }, {
1069 .mfr_id = MANUFACTURER_INTEL,
1070 .dev_id = I28F016B3T,
1071 .name = "Intel 28F016B3T",
1072 .uaddr = {
1073 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1074 },
1075 .DevSize = SIZE_2MiB,
1076 .CmdSet = P_ID_INTEL_STD,
1077 .NumEraseRegions= 2,
1078 .regions = {
1079 ERASEINFO(0x10000, 31),
1080 ERASEINFO(0x02000, 8),
1081 }
1082 }, {
1083 .mfr_id = MANUFACTURER_INTEL,
1084 .dev_id = I28F160B3B,
1085 .name = "Intel 28F160B3B",
1086 .uaddr = {
1087 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1088 },
1089 .DevSize = SIZE_2MiB,
1090 .CmdSet = P_ID_INTEL_STD,
1091 .NumEraseRegions= 2,
1092 .regions = {
1093 ERASEINFO(0x02000, 8),
1094 ERASEINFO(0x10000, 31),
1095 }
1096 }, {
1097 .mfr_id = MANUFACTURER_INTEL,
1098 .dev_id = I28F160B3T,
1099 .name = "Intel 28F160B3T",
1100 .uaddr = {
1101 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1102 },
1103 .DevSize = SIZE_2MiB,
1104 .CmdSet = P_ID_INTEL_STD,
1105 .NumEraseRegions= 2,
1106 .regions = {
1107 ERASEINFO(0x10000, 31),
1108 ERASEINFO(0x02000, 8),
1109 }
1110 }, {
1111 .mfr_id = MANUFACTURER_INTEL,
1112 .dev_id = I28F320B3B,
1113 .name = "Intel 28F320B3B",
1114 .uaddr = {
1115 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1116 },
1117 .DevSize = SIZE_4MiB,
1118 .CmdSet = P_ID_INTEL_STD,
1119 .NumEraseRegions= 2,
1120 .regions = {
1121 ERASEINFO(0x02000, 8),
1122 ERASEINFO(0x10000, 63),
1123 }
1124 }, {
1125 .mfr_id = MANUFACTURER_INTEL,
1126 .dev_id = I28F320B3T,
1127 .name = "Intel 28F320B3T",
1128 .uaddr = {
1129 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1130 },
1131 .DevSize = SIZE_4MiB,
1132 .CmdSet = P_ID_INTEL_STD,
1133 .NumEraseRegions= 2,
1134 .regions = {
1135 ERASEINFO(0x10000, 63),
1136 ERASEINFO(0x02000, 8),
1137 }
1138 }, {
1139 .mfr_id = MANUFACTURER_INTEL,
1140 .dev_id = I28F640B3B,
1141 .name = "Intel 28F640B3B",
1142 .uaddr = {
1143 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1144 },
1145 .DevSize = SIZE_8MiB,
1146 .CmdSet = P_ID_INTEL_STD,
1147 .NumEraseRegions= 2,
1148 .regions = {
1149 ERASEINFO(0x02000, 8),
1150 ERASEINFO(0x10000, 127),
1151 }
1152 }, {
1153 .mfr_id = MANUFACTURER_INTEL,
1154 .dev_id = I28F640B3T,
1155 .name = "Intel 28F640B3T",
1156 .uaddr = {
1157 [1] = MTD_UADDR_UNNECESSARY, /* x16 */
1158 },
1159 .DevSize = SIZE_8MiB,
1160 .CmdSet = P_ID_INTEL_STD,
1161 .NumEraseRegions= 2,
1162 .regions = {
1163 ERASEINFO(0x10000, 127),
1164 ERASEINFO(0x02000, 8),
1165 }
1166 }, {
1167 .mfr_id = MANUFACTURER_INTEL,
1168 .dev_id = I82802AB,
1169 .name = "Intel 82802AB",
1170 .uaddr = {
1171 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1172 },
1173 .DevSize = SIZE_512KiB,
1174 .CmdSet = P_ID_INTEL_EXT,
1175 .NumEraseRegions= 1,
1176 .regions = {
1177 ERASEINFO(0x10000,8),
1178 }
1179 }, {
1180 .mfr_id = MANUFACTURER_INTEL,
1181 .dev_id = I82802AC,
1182 .name = "Intel 82802AC",
1183 .uaddr = {
1184 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1185 },
1186 .DevSize = SIZE_1MiB,
1187 .CmdSet = P_ID_INTEL_EXT,
1188 .NumEraseRegions= 1,
1189 .regions = {
1190 ERASEINFO(0x10000,16),
1191 }
1192 }, {
1193 .mfr_id = MANUFACTURER_MACRONIX,
1194 .dev_id = MX29LV040C,
1195 .name = "Macronix MX29LV040C",
1196 .uaddr = {
1197 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
1198 },
1199 .DevSize = SIZE_512KiB,
1200 .CmdSet = P_ID_AMD_STD,
1201 .NumEraseRegions= 1,
1202 .regions = {
1203 ERASEINFO(0x10000,8),
1204 }
1205 }, {
1206 .mfr_id = MANUFACTURER_MACRONIX,
1207 .dev_id = MX29LV160T,
1208 .name = "MXIC MX29LV160T",
1209 .uaddr = {
1210 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1211 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1212 },
1213 .DevSize = SIZE_2MiB,
1214 .CmdSet = P_ID_AMD_STD,
1215 .NumEraseRegions= 4,
1216 .regions = {
1217 ERASEINFO(0x10000,31),
1218 ERASEINFO(0x08000,1),
1219 ERASEINFO(0x02000,2),
1220 ERASEINFO(0x04000,1)
1221 }
1222 }, {
1223 .mfr_id = MANUFACTURER_NEC,
1224 .dev_id = UPD29F064115,
1225 .name = "NEC uPD29F064115",
1226 .uaddr = {
1227 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
1228 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1229 },
1230 .DevSize = SIZE_8MiB,
1231 .CmdSet = P_ID_AMD_STD,
1232 .NumEraseRegions= 3,
1233 .regions = {
1234 ERASEINFO(0x2000,8),
1235 ERASEINFO(0x10000,126),
1236 ERASEINFO(0x2000,8),
1237 }
1238 }, {
1239 .mfr_id = MANUFACTURER_MACRONIX,
1240 .dev_id = MX29LV160B,
1241 .name = "MXIC MX29LV160B",
1242 .uaddr = {
1243 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1244 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1245 },
1246 .DevSize = SIZE_2MiB,
1247 .CmdSet = P_ID_AMD_STD,
1248 .NumEraseRegions= 4,
1249 .regions = {
1250 ERASEINFO(0x04000,1),
1251 ERASEINFO(0x02000,2),
1252 ERASEINFO(0x08000,1),
1253 ERASEINFO(0x10000,31)
1254 }
1255 }, {
1256 .mfr_id = MANUFACTURER_MACRONIX,
1257 .dev_id = MX29F040,
1258 .name = "Macronix MX29F040",
1259 .uaddr = {
1260 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1261 },
1262 .DevSize = SIZE_512KiB,
1263 .CmdSet = P_ID_AMD_STD,
1264 .NumEraseRegions= 1,
1265 .regions = {
1266 ERASEINFO(0x10000,8),
1267 }
1268 }, {
1269 .mfr_id = MANUFACTURER_MACRONIX,
1270 .dev_id = MX29F016,
1271 .name = "Macronix MX29F016",
1272 .uaddr = {
1273 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1274 },
1275 .DevSize = SIZE_2MiB,
1276 .CmdSet = P_ID_AMD_STD,
1277 .NumEraseRegions= 1,
1278 .regions = {
1279 ERASEINFO(0x10000,32),
1280 }
1281 }, {
1282 .mfr_id = MANUFACTURER_MACRONIX,
1283 .dev_id = MX29F004T,
1284 .name = "Macronix MX29F004T",
1285 .uaddr = {
1286 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1287 },
1288 .DevSize = SIZE_512KiB,
1289 .CmdSet = P_ID_AMD_STD,
1290 .NumEraseRegions= 4,
1291 .regions = {
1292 ERASEINFO(0x10000,7),
1293 ERASEINFO(0x08000,1),
1294 ERASEINFO(0x02000,2),
1295 ERASEINFO(0x04000,1),
1296 }
1297 }, {
1298 .mfr_id = MANUFACTURER_MACRONIX,
1299 .dev_id = MX29F004B,
1300 .name = "Macronix MX29F004B",
1301 .uaddr = {
1302 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1303 },
1304 .DevSize = SIZE_512KiB,
1305 .CmdSet = P_ID_AMD_STD,
1306 .NumEraseRegions= 4,
1307 .regions = {
1308 ERASEINFO(0x04000,1),
1309 ERASEINFO(0x02000,2),
1310 ERASEINFO(0x08000,1),
1311 ERASEINFO(0x10000,7),
1312 }
1313 }, {
1314 .mfr_id = MANUFACTURER_MACRONIX,
1315 .dev_id = MX29F002T,
1316 .name = "Macronix MX29F002T",
1317 .uaddr = {
1318 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1319 },
1320 .DevSize = SIZE_256KiB,
1321 .CmdSet = P_ID_AMD_STD,
1322 .NumEraseRegions= 4,
1323 .regions = {
1324 ERASEINFO(0x10000,3),
1325 ERASEINFO(0x08000,1),
1326 ERASEINFO(0x02000,2),
1327 ERASEINFO(0x04000,1),
1328 }
1329 }, {
1330 .mfr_id = MANUFACTURER_PMC,
1331 .dev_id = PM49FL002,
1332 .name = "PMC Pm49FL002",
1333 .uaddr = {
1334 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1335 },
1336 .DevSize = SIZE_256KiB,
1337 .CmdSet = P_ID_AMD_STD,
1338 .NumEraseRegions= 1,
1339 .regions = {
1340 ERASEINFO( 0x01000, 64 )
1341 }
1342 }, {
1343 .mfr_id = MANUFACTURER_PMC,
1344 .dev_id = PM49FL004,
1345 .name = "PMC Pm49FL004",
1346 .uaddr = {
1347 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1348 },
1349 .DevSize = SIZE_512KiB,
1350 .CmdSet = P_ID_AMD_STD,
1351 .NumEraseRegions= 1,
1352 .regions = {
1353 ERASEINFO( 0x01000, 128 )
1354 }
1355 }, {
1356 .mfr_id = MANUFACTURER_PMC,
1357 .dev_id = PM49FL008,
1358 .name = "PMC Pm49FL008",
1359 .uaddr = {
1360 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1361 },
1362 .DevSize = SIZE_1MiB,
1363 .CmdSet = P_ID_AMD_STD,
1364 .NumEraseRegions= 1,
1365 .regions = {
1366 ERASEINFO( 0x01000, 256 )
1367 }
1368 }, {
1369 .mfr_id = MANUFACTURER_SHARP,
1370 .dev_id = LH28F640BF,
1371 .name = "LH28F640BF",
1372 .uaddr = {
1373 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1374 },
1375 .DevSize = SIZE_4MiB,
1376 .CmdSet = P_ID_INTEL_STD,
1377 .NumEraseRegions= 1,
1378 .regions = {
1379 ERASEINFO(0x40000,16),
1380 }
1381 }, {
1382 .mfr_id = MANUFACTURER_SST,
1383 .dev_id = SST39LF512,
1384 .name = "SST 39LF512",
1385 .uaddr = {
1386 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1387 },
1388 .DevSize = SIZE_64KiB,
1389 .CmdSet = P_ID_AMD_STD,
1390 .NumEraseRegions= 1,
1391 .regions = {
1392 ERASEINFO(0x01000,16),
1393 }
1394 }, {
1395 .mfr_id = MANUFACTURER_SST,
1396 .dev_id = SST39LF010,
1397 .name = "SST 39LF010",
1398 .uaddr = {
1399 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1400 },
1401 .DevSize = SIZE_128KiB,
1402 .CmdSet = P_ID_AMD_STD,
1403 .NumEraseRegions= 1,
1404 .regions = {
1405 ERASEINFO(0x01000,32),
1406 }
1407 }, {
1408 .mfr_id = MANUFACTURER_SST,
1409 .dev_id = SST29EE020,
1410 .name = "SST 29EE020",
1411 .uaddr = {
1412 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1413 },
1414 .DevSize = SIZE_256KiB,
1415 .CmdSet = P_ID_SST_PAGE,
1416 .NumEraseRegions= 1,
1417 .regions = {ERASEINFO(0x01000,64),
1418 }
1419 }, {
1420 .mfr_id = MANUFACTURER_SST,
1421 .dev_id = SST29LE020,
1422 .name = "SST 29LE020",
1423 .uaddr = {
1424 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1425 },
1426 .DevSize = SIZE_256KiB,
1427 .CmdSet = P_ID_SST_PAGE,
1428 .NumEraseRegions= 1,
1429 .regions = {ERASEINFO(0x01000,64),
1430 }
1431 }, {
1432 .mfr_id = MANUFACTURER_SST,
1433 .dev_id = SST39LF020,
1434 .name = "SST 39LF020",
1435 .uaddr = {
1436 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1437 },
1438 .DevSize = SIZE_256KiB,
1439 .CmdSet = P_ID_AMD_STD,
1440 .NumEraseRegions= 1,
1441 .regions = {
1442 ERASEINFO(0x01000,64),
1443 }
1444 }, {
1445 .mfr_id = MANUFACTURER_SST,
1446 .dev_id = SST39LF040,
1447 .name = "SST 39LF040",
1448 .uaddr = {
1449 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1450 },
1451 .DevSize = SIZE_512KiB,
1452 .CmdSet = P_ID_AMD_STD,
1453 .NumEraseRegions= 1,
1454 .regions = {
1455 ERASEINFO(0x01000,128),
1456 }
1457 }, {
1458 .mfr_id = MANUFACTURER_SST,
1459 .dev_id = SST39SF010A,
1460 .name = "SST 39SF010A",
1461 .uaddr = {
1462 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1463 },
1464 .DevSize = SIZE_128KiB,
1465 .CmdSet = P_ID_AMD_STD,
1466 .NumEraseRegions= 1,
1467 .regions = {
1468 ERASEINFO(0x01000,32),
1469 }
1470 }, {
1471 .mfr_id = MANUFACTURER_SST,
1472 .dev_id = SST39SF020A,
1473 .name = "SST 39SF020A",
1474 .uaddr = {
1475 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1476 },
1477 .DevSize = SIZE_256KiB,
1478 .CmdSet = P_ID_AMD_STD,
1479 .NumEraseRegions= 1,
1480 .regions = {
1481 ERASEINFO(0x01000,64),
1482 }
1483 }, {
1484 .mfr_id = MANUFACTURER_SST,
1485 .dev_id = SST49LF004B,
1486 .name = "SST 49LF004B",
1487 .uaddr = {
1488 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1489 },
1490 .DevSize = SIZE_512KiB,
1491 .CmdSet = P_ID_AMD_STD,
1492 .NumEraseRegions= 1,
1493 .regions = {
1494 ERASEINFO(0x01000,128),
1495 }
1496 }, {
1497 .mfr_id = MANUFACTURER_SST,
1498 .dev_id = SST49LF008A,
1499 .name = "SST 49LF008A",
1500 .uaddr = {
1501 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1502 },
1503 .DevSize = SIZE_1MiB,
1504 .CmdSet = P_ID_AMD_STD,
1505 .NumEraseRegions= 1,
1506 .regions = {
1507 ERASEINFO(0x01000,256),
1508 }
1509 }, {
1510 .mfr_id = MANUFACTURER_SST,
1511 .dev_id = SST49LF030A,
1512 .name = "SST 49LF030A",
1513 .uaddr = {
1514 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1515 },
1516 .DevSize = SIZE_512KiB,
1517 .CmdSet = P_ID_AMD_STD,
1518 .NumEraseRegions= 1,
1519 .regions = {
1520 ERASEINFO(0x01000,96),
1521 }
1522 }, {
1523 .mfr_id = MANUFACTURER_SST,
1524 .dev_id = SST49LF040A,
1525 .name = "SST 49LF040A",
1526 .uaddr = {
1527 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1528 },
1529 .DevSize = SIZE_512KiB,
1530 .CmdSet = P_ID_AMD_STD,
1531 .NumEraseRegions= 1,
1532 .regions = {
1533 ERASEINFO(0x01000,128),
1534 }
1535 }, {
1536 .mfr_id = MANUFACTURER_SST,
1537 .dev_id = SST49LF080A,
1538 .name = "SST 49LF080A",
1539 .uaddr = {
1540 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1541 },
1542 .DevSize = SIZE_1MiB,
1543 .CmdSet = P_ID_AMD_STD,
1544 .NumEraseRegions= 1,
1545 .regions = {
1546 ERASEINFO(0x01000,256),
1547 }
1548 }, {
1549 .mfr_id = MANUFACTURER_SST, /* should be CFI */
1550 .dev_id = SST39LF160,
1551 .name = "SST 39LF160",
1552 .uaddr = {
1553 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
1554 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
1555 },
1556 .DevSize = SIZE_2MiB,
1557 .CmdSet = P_ID_AMD_STD,
1558 .NumEraseRegions= 2,
1559 .regions = {
1560 ERASEINFO(0x1000,256),
1561 ERASEINFO(0x1000,256)
1562 }
1563 }, {
1564 .mfr_id = MANUFACTURER_SST, /* should be CFI */
1565 .dev_id = SST39VF1601,
1566 .name = "SST 39VF1601",
1567 .uaddr = {
1568 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
1569 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
1570 },
1571 .DevSize = SIZE_2MiB,
1572 .CmdSet = P_ID_AMD_STD,
1573 .NumEraseRegions= 2,
1574 .regions = {
1575 ERASEINFO(0x1000,256),
1576 ERASEINFO(0x1000,256)
1577 }
1578
1579 }, {
1580 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1581 .dev_id = M29W800DT,
1582 .name = "ST M29W800DT",
1583 .uaddr = {
1584 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
1585 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
1586 },
1587 .DevSize = SIZE_1MiB,
1588 .CmdSet = P_ID_AMD_STD,
1589 .NumEraseRegions= 4,
1590 .regions = {
1591 ERASEINFO(0x10000,15),
1592 ERASEINFO(0x08000,1),
1593 ERASEINFO(0x02000,2),
1594 ERASEINFO(0x04000,1)
1595 }
1596 }, {
1597 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1598 .dev_id = M29W800DB,
1599 .name = "ST M29W800DB",
1600 .uaddr = {
1601 [0] = MTD_UADDR_0x5555_0x2AAA, /* x8 */
1602 [1] = MTD_UADDR_0x5555_0x2AAA /* x16 */
1603 },
1604 .DevSize = SIZE_1MiB,
1605 .CmdSet = P_ID_AMD_STD,
1606 .NumEraseRegions= 4,
1607 .regions = {
1608 ERASEINFO(0x04000,1),
1609 ERASEINFO(0x02000,2),
1610 ERASEINFO(0x08000,1),
1611 ERASEINFO(0x10000,15)
1612 }
1613 }, {
1614 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1615 .dev_id = M29W160DT,
1616 .name = "ST M29W160DT",
1617 .uaddr = {
1618 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
1619 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1620 },
1621 .DevSize = SIZE_2MiB,
1622 .CmdSet = P_ID_AMD_STD,
1623 .NumEraseRegions= 4,
1624 .regions = {
1625 ERASEINFO(0x10000,31),
1626 ERASEINFO(0x08000,1),
1627 ERASEINFO(0x02000,2),
1628 ERASEINFO(0x04000,1)
1629 }
1630 }, {
1631 .mfr_id = MANUFACTURER_ST, /* FIXME - CFI device? */
1632 .dev_id = M29W160DB,
1633 .name = "ST M29W160DB",
1634 .uaddr = {
1635 [0] = MTD_UADDR_0x0555_0x02AA, /* x8 */
1636 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1637 },
1638 .DevSize = SIZE_2MiB,
1639 .CmdSet = P_ID_AMD_STD,
1640 .NumEraseRegions= 4,
1641 .regions = {
1642 ERASEINFO(0x04000,1),
1643 ERASEINFO(0x02000,2),
1644 ERASEINFO(0x08000,1),
1645 ERASEINFO(0x10000,31)
1646 }
1647 }, {
1648 .mfr_id = MANUFACTURER_ST,
1649 .dev_id = M29W040B,
1650 .name = "ST M29W040B",
1651 .uaddr = {
1652 [0] = MTD_UADDR_0x0555_0x02AA /* x8 */
1653 },
1654 .DevSize = SIZE_512KiB,
1655 .CmdSet = P_ID_AMD_STD,
1656 .NumEraseRegions= 1,
1657 .regions = {
1658 ERASEINFO(0x10000,8),
1659 }
1660 }, {
1661 .mfr_id = MANUFACTURER_ST,
1662 .dev_id = M50FW040,
1663 .name = "ST M50FW040",
1664 .uaddr = {
1665 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1666 },
1667 .DevSize = SIZE_512KiB,
1668 .CmdSet = P_ID_INTEL_EXT,
1669 .NumEraseRegions= 1,
1670 .regions = {
1671 ERASEINFO(0x10000,8),
1672 }
1673 }, {
1674 .mfr_id = MANUFACTURER_ST,
1675 .dev_id = M50FW080,
1676 .name = "ST M50FW080",
1677 .uaddr = {
1678 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1679 },
1680 .DevSize = SIZE_1MiB,
1681 .CmdSet = P_ID_INTEL_EXT,
1682 .NumEraseRegions= 1,
1683 .regions = {
1684 ERASEINFO(0x10000,16),
1685 }
1686 }, {
1687 .mfr_id = MANUFACTURER_ST,
1688 .dev_id = M50FW016,
1689 .name = "ST M50FW016",
1690 .uaddr = {
1691 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1692 },
1693 .DevSize = SIZE_2MiB,
1694 .CmdSet = P_ID_INTEL_EXT,
1695 .NumEraseRegions= 1,
1696 .regions = {
1697 ERASEINFO(0x10000,32),
1698 }
1699 }, {
1700 .mfr_id = MANUFACTURER_ST,
1701 .dev_id = M50LPW080,
1702 .name = "ST M50LPW080",
1703 .uaddr = {
1704 [0] = MTD_UADDR_UNNECESSARY, /* x8 */
1705 },
1706 .DevSize = SIZE_1MiB,
1707 .CmdSet = P_ID_INTEL_EXT,
1708 .NumEraseRegions= 1,
1709 .regions = {
1710 ERASEINFO(0x10000,16),
1711 }
1712 }, {
1713 .mfr_id = MANUFACTURER_TOSHIBA,
1714 .dev_id = TC58FVT160,
1715 .name = "Toshiba TC58FVT160",
1716 .uaddr = {
1717 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1718 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1719 },
1720 .DevSize = SIZE_2MiB,
1721 .CmdSet = P_ID_AMD_STD,
1722 .NumEraseRegions= 4,
1723 .regions = {
1724 ERASEINFO(0x10000,31),
1725 ERASEINFO(0x08000,1),
1726 ERASEINFO(0x02000,2),
1727 ERASEINFO(0x04000,1)
1728 }
1729 }, {
1730 .mfr_id = MANUFACTURER_TOSHIBA,
1731 .dev_id = TC58FVB160,
1732 .name = "Toshiba TC58FVB160",
1733 .uaddr = {
1734 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1735 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1736 },
1737 .DevSize = SIZE_2MiB,
1738 .CmdSet = P_ID_AMD_STD,
1739 .NumEraseRegions= 4,
1740 .regions = {
1741 ERASEINFO(0x04000,1),
1742 ERASEINFO(0x02000,2),
1743 ERASEINFO(0x08000,1),
1744 ERASEINFO(0x10000,31)
1745 }
1746 }, {
1747 .mfr_id = MANUFACTURER_TOSHIBA,
1748 .dev_id = TC58FVB321,
1749 .name = "Toshiba TC58FVB321",
1750 .uaddr = {
1751 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1752 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1753 },
1754 .DevSize = SIZE_4MiB,
1755 .CmdSet = P_ID_AMD_STD,
1756 .NumEraseRegions= 2,
1757 .regions = {
1758 ERASEINFO(0x02000,8),
1759 ERASEINFO(0x10000,63)
1760 }
1761 }, {
1762 .mfr_id = MANUFACTURER_TOSHIBA,
1763 .dev_id = TC58FVT321,
1764 .name = "Toshiba TC58FVT321",
1765 .uaddr = {
1766 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1767 [1] = MTD_UADDR_0x0555_0x02AA /* x16 */
1768 },
1769 .DevSize = SIZE_4MiB,
1770 .CmdSet = P_ID_AMD_STD,
1771 .NumEraseRegions= 2,
1772 .regions = {
1773 ERASEINFO(0x10000,63),
1774 ERASEINFO(0x02000,8)
1775 }
1776 }, {
1777 .mfr_id = MANUFACTURER_TOSHIBA,
1778 .dev_id = TC58FVB641,
1779 .name = "Toshiba TC58FVB641",
1780 .uaddr = {
1781 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1782 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1783 },
1784 .DevSize = SIZE_8MiB,
1785 .CmdSet = P_ID_AMD_STD,
1786 .NumEraseRegions= 2,
1787 .regions = {
1788 ERASEINFO(0x02000,8),
1789 ERASEINFO(0x10000,127)
1790 }
1791 }, {
1792 .mfr_id = MANUFACTURER_TOSHIBA,
1793 .dev_id = TC58FVT641,
1794 .name = "Toshiba TC58FVT641",
1795 .uaddr = {
1796 [0] = MTD_UADDR_0x0AAA_0x0555, /* x8 */
1797 [1] = MTD_UADDR_0x0555_0x02AA, /* x16 */
1798 },
1799 .DevSize = SIZE_8MiB,
1800 .CmdSet = P_ID_AMD_STD,
1801 .NumEraseRegions= 2,
1802 .regions = {
1803 ERASEINFO(0x10000,127),
1804 ERASEINFO(0x02000,8)
1805 }
1806 }, {
1807 .mfr_id = MANUFACTURER_WINBOND,
1808 .dev_id = W49V002A,
1809 .name = "Winbond W49V002A",
1810 .uaddr = {
1811 [0] = MTD_UADDR_0x5555_0x2AAA /* x8 */
1812 },
1813 .DevSize = SIZE_256KiB,
1814 .CmdSet = P_ID_AMD_STD,
1815 .NumEraseRegions= 4,
1816 .regions = {
1817 ERASEINFO(0x10000, 3),
1818 ERASEINFO(0x08000, 1),
1819 ERASEINFO(0x02000, 2),
1820 ERASEINFO(0x04000, 1),
1821 }
1822 }
1823 };
1824
1825
1826 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index);
1827
1828 static int jedec_probe_chip(struct map_info *map, __u32 base,
1829 unsigned long *chip_map, struct cfi_private *cfi);
1830
1831 static struct mtd_info *jedec_probe(struct map_info *map);
1832
1833 static inline u32 jedec_read_mfr(struct map_info *map, __u32 base,
1834 struct cfi_private *cfi)
1835 {
1836 map_word result;
1837 unsigned long mask;
1838 u32 ofs = cfi_build_cmd_addr(0, cfi_interleave(cfi), cfi->device_type);
1839 mask = (1 << (cfi->device_type * 8)) -1;
1840 result = map_read(map, base + ofs);
1841 return result.x[0] & mask;
1842 }
1843
1844 static inline u32 jedec_read_id(struct map_info *map, __u32 base,
1845 struct cfi_private *cfi)
1846 {
1847 map_word result;
1848 unsigned long mask;
1849 u32 ofs = cfi_build_cmd_addr(1, cfi_interleave(cfi), cfi->device_type);
1850 mask = (1 << (cfi->device_type * 8)) -1;
1851 result = map_read(map, base + ofs);
1852 return result.x[0] & mask;
1853 }
1854
1855 static inline void jedec_reset(u32 base, struct map_info *map,
1856 struct cfi_private *cfi)
1857 {
1858 /* Reset */
1859
1860 /* after checking the datasheets for SST, MACRONIX and ATMEL
1861 * (oh and incidentaly the jedec spec - 3.5.3.3) the reset
1862 * sequence is *supposed* to be 0xaa at 0x5555, 0x55 at
1863 * 0x2aaa, 0xF0 at 0x5555 this will not affect the AMD chips
1864 * as they will ignore the writes and dont care what address
1865 * the F0 is written to */
1866 if(cfi->addr_unlock1) {
1867 DEBUG( MTD_DEBUG_LEVEL3,
1868 "reset unlock called %x %x \n",
1869 cfi->addr_unlock1,cfi->addr_unlock2);
1870 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
1871 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
1872 }
1873
1874 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
1875 /* Some misdesigned intel chips do not respond for 0xF0 for a reset,
1876 * so ensure we're in read mode. Send both the Intel and the AMD command
1877 * for this. Intel uses 0xff for this, AMD uses 0xff for NOP, so
1878 * this should be safe.
1879 */
1880 cfi_send_gen_cmd(0xFF, 0, base, map, cfi, cfi->device_type, NULL);
1881 /* FIXME - should have reset delay before continuing */
1882 }
1883
1884
1885 static inline __u8 finfo_uaddr(const struct amd_flash_info *finfo, int device_type)
1886 {
1887 int uaddr_idx;
1888 __u8 uaddr = MTD_UADDR_NOT_SUPPORTED;
1889
1890 switch ( device_type ) {
1891 case CFI_DEVICETYPE_X8: uaddr_idx = 0; break;
1892 case CFI_DEVICETYPE_X16: uaddr_idx = 1; break;
1893 case CFI_DEVICETYPE_X32: uaddr_idx = 2; break;
1894 default:
1895 printk(KERN_NOTICE "MTD: %s(): unknown device_type %d\n",
1896 __func__, device_type);
1897 goto uaddr_done;
1898 }
1899
1900 uaddr = finfo->uaddr[uaddr_idx];
1901
1902 if (uaddr != MTD_UADDR_NOT_SUPPORTED ) {
1903 /* ASSERT("The unlock addresses for non-8-bit mode
1904 are bollocks. We don't really need an array."); */
1905 uaddr = finfo->uaddr[0];
1906 }
1907
1908 uaddr_done:
1909 return uaddr;
1910 }
1911
1912
1913 static int cfi_jedec_setup(struct cfi_private *p_cfi, int index)
1914 {
1915 int i,num_erase_regions;
1916 __u8 uaddr;
1917
1918 printk("Found: %s\n",jedec_table[index].name);
1919
1920 num_erase_regions = jedec_table[index].NumEraseRegions;
1921
1922 p_cfi->cfiq = kmalloc(sizeof(struct cfi_ident) + num_erase_regions * 4, GFP_KERNEL);
1923 if (!p_cfi->cfiq) {
1924 //xx printk(KERN_WARNING "%s: kmalloc failed for CFI ident structure\n", map->name);
1925 return 0;
1926 }
1927
1928 memset(p_cfi->cfiq,0,sizeof(struct cfi_ident));
1929
1930 p_cfi->cfiq->P_ID = jedec_table[index].CmdSet;
1931 p_cfi->cfiq->NumEraseRegions = jedec_table[index].NumEraseRegions;
1932 p_cfi->cfiq->DevSize = jedec_table[index].DevSize;
1933 p_cfi->cfi_mode = CFI_MODE_JEDEC;
1934
1935 for (i=0; i<num_erase_regions; i++){
1936 p_cfi->cfiq->EraseRegionInfo[i] = jedec_table[index].regions[i];
1937 }
1938 p_cfi->cmdset_priv = NULL;
1939
1940 /* This may be redundant for some cases, but it doesn't hurt */
1941 p_cfi->mfr = jedec_table[index].mfr_id;
1942 p_cfi->id = jedec_table[index].dev_id;
1943
1944 uaddr = finfo_uaddr(&jedec_table[index], p_cfi->device_type);
1945 if ( uaddr == MTD_UADDR_NOT_SUPPORTED ) {
1946 kfree( p_cfi->cfiq );
1947 return 0;
1948 }
1949
1950 p_cfi->addr_unlock1 = unlock_addrs[uaddr].addr1;
1951 p_cfi->addr_unlock2 = unlock_addrs[uaddr].addr2;
1952
1953 return 1; /* ok */
1954 }
1955
1956
1957 /*
1958 * There is a BIG problem properly ID'ing the JEDEC devic and guaranteeing
1959 * the mapped address, unlock addresses, and proper chip ID. This function
1960 * attempts to minimize errors. It is doubtfull that this probe will ever
1961 * be perfect - consequently there should be some module parameters that
1962 * could be manually specified to force the chip info.
1963 */
1964 static inline int jedec_match( __u32 base,
1965 struct map_info *map,
1966 struct cfi_private *cfi,
1967 const struct amd_flash_info *finfo )
1968 {
1969 int rc = 0; /* failure until all tests pass */
1970 u32 mfr, id;
1971 __u8 uaddr;
1972
1973 /*
1974 * The IDs must match. For X16 and X32 devices operating in
1975 * a lower width ( X8 or X16 ), the device ID's are usually just
1976 * the lower byte(s) of the larger device ID for wider mode. If
1977 * a part is found that doesn't fit this assumption (device id for
1978 * smaller width mode is completely unrealated to full-width mode)
1979 * then the jedec_table[] will have to be augmented with the IDs
1980 * for different widths.
1981 */
1982 switch (cfi->device_type) {
1983 case CFI_DEVICETYPE_X8:
1984 mfr = (__u8)finfo->mfr_id;
1985 id = (__u8)finfo->dev_id;
1986
1987 /* bjd: it seems that if we do this, we can end up
1988 * detecting 16bit flashes as an 8bit device, even though
1989 * there aren't.
1990 */
1991 if (finfo->dev_id > 0xff) {
1992 DEBUG( MTD_DEBUG_LEVEL3, "%s(): ID is not 8bit\n",
1993 __func__);
1994 goto match_done;
1995 }
1996 break;
1997 case CFI_DEVICETYPE_X16:
1998 mfr = (__u16)finfo->mfr_id;
1999 id = (__u16)finfo->dev_id;
2000 break;
2001 case CFI_DEVICETYPE_X32:
2002 mfr = (__u16)finfo->mfr_id;
2003 id = (__u32)finfo->dev_id;
2004 break;
2005 default:
2006 printk(KERN_WARNING
2007 "MTD %s(): Unsupported device type %d\n",
2008 __func__, cfi->device_type);
2009 goto match_done;
2010 }
2011 if ( cfi->mfr != mfr || cfi->id != id ) {
2012 goto match_done;
2013 }
2014
2015 /* the part size must fit in the memory window */
2016 DEBUG( MTD_DEBUG_LEVEL3,
2017 "MTD %s(): Check fit 0x%.8x + 0x%.8x = 0x%.8x\n",
2018 __func__, base, 1 << finfo->DevSize, base + (1 << finfo->DevSize) );
2019 if ( base + cfi_interleave(cfi) * ( 1 << finfo->DevSize ) > map->size ) {
2020 DEBUG( MTD_DEBUG_LEVEL3,
2021 "MTD %s(): 0x%.4x 0x%.4x %dKiB doesn't fit\n",
2022 __func__, finfo->mfr_id, finfo->dev_id,
2023 1 << finfo->DevSize );
2024 goto match_done;
2025 }
2026
2027 uaddr = finfo_uaddr(finfo, cfi->device_type);
2028 if ( uaddr == MTD_UADDR_NOT_SUPPORTED ) {
2029 goto match_done;
2030 }
2031
2032 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): check unlock addrs 0x%.4x 0x%.4x\n",
2033 __func__, cfi->addr_unlock1, cfi->addr_unlock2 );
2034 if ( MTD_UADDR_UNNECESSARY != uaddr && MTD_UADDR_DONT_CARE != uaddr
2035 && ( unlock_addrs[uaddr].addr1 != cfi->addr_unlock1 ||
2036 unlock_addrs[uaddr].addr2 != cfi->addr_unlock2 ) ) {
2037 DEBUG( MTD_DEBUG_LEVEL3,
2038 "MTD %s(): 0x%.4x 0x%.4x did not match\n",
2039 __func__,
2040 unlock_addrs[uaddr].addr1,
2041 unlock_addrs[uaddr].addr2);
2042 goto match_done;
2043 }
2044
2045 /*
2046 * Make sure the ID's dissappear when the device is taken out of
2047 * ID mode. The only time this should fail when it should succeed
2048 * is when the ID's are written as data to the same
2049 * addresses. For this rare and unfortunate case the chip
2050 * cannot be probed correctly.
2051 * FIXME - write a driver that takes all of the chip info as
2052 * module parameters, doesn't probe but forces a load.
2053 */
2054 DEBUG( MTD_DEBUG_LEVEL3,
2055 "MTD %s(): check ID's disappear when not in ID mode\n",
2056 __func__ );
2057 jedec_reset( base, map, cfi );
2058 mfr = jedec_read_mfr( map, base, cfi );
2059 id = jedec_read_id( map, base, cfi );
2060 if ( mfr == cfi->mfr && id == cfi->id ) {
2061 DEBUG( MTD_DEBUG_LEVEL3,
2062 "MTD %s(): ID 0x%.2x:0x%.2x did not change after reset:\n"
2063 "You might need to manually specify JEDEC parameters.\n",
2064 __func__, cfi->mfr, cfi->id );
2065 goto match_done;
2066 }
2067
2068 /* all tests passed - mark as success */
2069 rc = 1;
2070
2071 /*
2072 * Put the device back in ID mode - only need to do this if we
2073 * were truly frobbing a real device.
2074 */
2075 DEBUG( MTD_DEBUG_LEVEL3, "MTD %s(): return to ID mode\n", __func__ );
2076 if(cfi->addr_unlock1) {
2077 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2078 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
2079 }
2080 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2081 /* FIXME - should have a delay before continuing */
2082
2083 match_done:
2084 return rc;
2085 }
2086
2087
2088 static int jedec_probe_chip(struct map_info *map, __u32 base,
2089 unsigned long *chip_map, struct cfi_private *cfi)
2090 {
2091 int i;
2092 enum uaddr uaddr_idx = MTD_UADDR_NOT_SUPPORTED;
2093 u32 probe_offset1, probe_offset2;
2094
2095 retry:
2096 if (!cfi->numchips) {
2097 uaddr_idx++;
2098
2099 if (MTD_UADDR_UNNECESSARY == uaddr_idx)
2100 return 0;
2101
2102 cfi->addr_unlock1 = unlock_addrs[uaddr_idx].addr1;
2103 cfi->addr_unlock2 = unlock_addrs[uaddr_idx].addr2;
2104 }
2105
2106 /* Make certain we aren't probing past the end of map */
2107 if (base >= map->size) {
2108 printk(KERN_NOTICE
2109 "Probe at base(0x%08x) past the end of the map(0x%08lx)\n",
2110 base, map->size -1);
2111 return 0;
2112
2113 }
2114 /* Ensure the unlock addresses we try stay inside the map */
2115 probe_offset1 = cfi_build_cmd_addr(
2116 cfi->addr_unlock1,
2117 cfi_interleave(cfi),
2118 cfi->device_type);
2119 probe_offset2 = cfi_build_cmd_addr(
2120 cfi->addr_unlock1,
2121 cfi_interleave(cfi),
2122 cfi->device_type);
2123 if ( ((base + probe_offset1 + map_bankwidth(map)) >= map->size) ||
2124 ((base + probe_offset2 + map_bankwidth(map)) >= map->size))
2125 {
2126 goto retry;
2127 }
2128
2129 /* Reset */
2130 jedec_reset(base, map, cfi);
2131
2132 /* Autoselect Mode */
2133 if(cfi->addr_unlock1) {
2134 cfi_send_gen_cmd(0xaa, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2135 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, base, map, cfi, cfi->device_type, NULL);
2136 }
2137 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, base, map, cfi, cfi->device_type, NULL);
2138 /* FIXME - should have a delay before continuing */
2139
2140 if (!cfi->numchips) {
2141 /* This is the first time we're called. Set up the CFI
2142 stuff accordingly and return */
2143
2144 cfi->mfr = jedec_read_mfr(map, base, cfi);
2145 cfi->id = jedec_read_id(map, base, cfi);
2146 DEBUG(MTD_DEBUG_LEVEL3,
2147 "Search for id:(%02x %02x) interleave(%d) type(%d)\n",
2148 cfi->mfr, cfi->id, cfi_interleave(cfi), cfi->device_type);
2149 for (i = 0; i < ARRAY_SIZE(jedec_table); i++) {
2150 if ( jedec_match( base, map, cfi, &jedec_table[i] ) ) {
2151 DEBUG( MTD_DEBUG_LEVEL3,
2152 "MTD %s(): matched device 0x%x,0x%x unlock_addrs: 0x%.4x 0x%.4x\n",
2153 __func__, cfi->mfr, cfi->id,
2154 cfi->addr_unlock1, cfi->addr_unlock2 );
2155 if (!cfi_jedec_setup(cfi, i))
2156 return 0;
2157 goto ok_out;
2158 }
2159 }
2160 goto retry;
2161 } else {
2162 __u16 mfr;
2163 __u16 id;
2164
2165 /* Make sure it is a chip of the same manufacturer and id */
2166 mfr = jedec_read_mfr(map, base, cfi);
2167 id = jedec_read_id(map, base, cfi);
2168
2169 if ((mfr != cfi->mfr) || (id != cfi->id)) {
2170 printk(KERN_DEBUG "%s: Found different chip or no chip at all (mfr 0x%x, id 0x%x) at 0x%x\n",
2171 map->name, mfr, id, base);
2172 jedec_reset(base, map, cfi);
2173 return 0;
2174 }
2175 }
2176
2177 /* Check each previous chip locations to see if it's an alias */
2178 for (i=0; i < (base >> cfi->chipshift); i++) {
2179 unsigned long start;
2180 if(!test_bit(i, chip_map)) {
2181 continue; /* Skip location; no valid chip at this address */
2182 }
2183 start = i << cfi->chipshift;
2184 if (jedec_read_mfr(map, start, cfi) == cfi->mfr &&
2185 jedec_read_id(map, start, cfi) == cfi->id) {
2186 /* Eep. This chip also looks like it's in autoselect mode.
2187 Is it an alias for the new one? */
2188 jedec_reset(start, map, cfi);
2189
2190 /* If the device IDs go away, it's an alias */
2191 if (jedec_read_mfr(map, base, cfi) != cfi->mfr ||
2192 jedec_read_id(map, base, cfi) != cfi->id) {
2193 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
2194 map->name, base, start);
2195 return 0;
2196 }
2197
2198 /* Yes, it's actually got the device IDs as data. Most
2199 * unfortunate. Stick the new chip in read mode
2200 * too and if it's the same, assume it's an alias. */
2201 /* FIXME: Use other modes to do a proper check */
2202 jedec_reset(base, map, cfi);
2203 if (jedec_read_mfr(map, base, cfi) == cfi->mfr &&
2204 jedec_read_id(map, base, cfi) == cfi->id) {
2205 printk(KERN_DEBUG "%s: Found an alias at 0x%x for the chip at 0x%lx\n",
2206 map->name, base, start);
2207 return 0;
2208 }
2209 }
2210 }
2211
2212 /* OK, if we got to here, then none of the previous chips appear to
2213 be aliases for the current one. */
2214 set_bit((base >> cfi->chipshift), chip_map); /* Update chip map */
2215 cfi->numchips++;
2216
2217 ok_out:
2218 /* Put it back into Read Mode */
2219 jedec_reset(base, map, cfi);
2220
2221 printk(KERN_INFO "%s: Found %d x%d devices at 0x%x in %d-bit bank\n",
2222 map->name, cfi_interleave(cfi), cfi->device_type*8, base,
2223 map->bankwidth*8);
2224
2225 return 1;
2226 }
2227
2228 static struct chip_probe jedec_chip_probe = {
2229 .name = "JEDEC",
2230 .probe_chip = jedec_probe_chip
2231 };
2232
2233 static struct mtd_info *jedec_probe(struct map_info *map)
2234 {
2235 /*
2236 * Just use the generic probe stuff to call our CFI-specific
2237 * chip_probe routine in all the possible permutations, etc.
2238 */
2239 return mtd_do_chip_probe(map, &jedec_chip_probe);
2240 }
2241
2242 static struct mtd_chip_driver jedec_chipdrv = {
2243 .probe = jedec_probe,
2244 .name = "jedec_probe",
2245 .module = THIS_MODULE
2246 };
2247
2248 static int __init jedec_probe_init(void)
2249 {
2250 register_mtd_chip_driver(&jedec_chipdrv);
2251 return 0;
2252 }
2253
2254 static void __exit jedec_probe_exit(void)
2255 {
2256 unregister_mtd_chip_driver(&jedec_chipdrv);
2257 }
2258
2259 module_init(jedec_probe_init);
2260 module_exit(jedec_probe_exit);
2261
2262 MODULE_LICENSE("GPL");
2263 MODULE_AUTHOR("Erwin Authried <eauth@softsys.co.at> et al.");
2264 MODULE_DESCRIPTION("Probe code for JEDEC-compliant flash chips");
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz