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MOXA linux-2.6.x / linux-2.6.19-uc1 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz
[linux-2.6.19-moxart.git] / drivers / net / mtip1000.c
blob42d42e2a49f0772d2b59e47776d9389f14af118c
1 /*----------------------------------------------------------------------
2 . mtip1000.c
3 .
4 . Driver: MoreThanIP 10/100/1000Mbps Emac IP
5 .
6 . Copyright (C) 2004 Microtronix Datacom Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 . Sources:
19 . o MoreThanIP 10/100/1000Mbps Reference Guide V3.2 - May 2003
20 . o MoreThanIP Altera Plugs sources
21 . - mtip_10_100_1000.c
22 . - mtip_10_100_1000_adapter.c
23 . - mac_stream_test.c
24 . o Smc9111 uClinux port(s)
25 .
26 . History:
27 . o Apr2004 DGT Microtronix Datacom - Linux 2.6.5
28 .
29 -----------------------------------------------------------------------*/
30
31 static const char version[] =
32 "MoreThanIP 10/100/1000 Driver"
33 "(v1.0)"
34 ", Linux 2.6.5 Apr2004\n";
35
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/kernel.h>
39 #include <linux/sched.h>
40 #include <linux/types.h>
41 #include <linux/fcntl.h>
42 #include <linux/interrupt.h>
43 #include <linux/ptrace.h>
44 #include <linux/ioport.h>
45 #include <linux/in.h>
46 #include <linux/slab.h>
47 #include <linux/string.h>
48 #include <linux/init.h>
49 #include <asm/bitops.h>
50 #include <asm/system.h>
51
52 #include <asm/io.h>
53
54 #ifdef CONFIG_EXCALIBUR
55 #include <asm/nios.h>
56 #include <asm/ndma.h>
57 #include <asm/cacheflush.h>
58 #endif // CONFIG_EXCALIBUR
59
60 #include <linux/errno.h>
61 #include <linux/delay.h>
62
63 #include <linux/netdevice.h>
64 #include <linux/etherdevice.h>
65 #include <linux/skbuff.h>
66
67 #include "mtip1000.h"
68 #include "stdphy.h"
69
70 #define ANNOUNCEPHY
71 //#undef ANNOUNCEPHY
72
73 //#undef MTIPPHYIRQ_AVAIL
74 #if 1
75 #if defined (na_mii_irq_irq)
76 #define MTIPPHYIRQ_AVAIL
77 #define mtip_mii_control_port ((unsigned int *) (((unsigned int) (na_mii_irq)) | 0x80000000))
78 #endif // na_mii_irq_irq
79 #else
80 #undef na_mii_irq_irq
81 #undef na_mii_irq
82 #endif
83
84 //#define NS83865PHY
85 #define TDK78Q2120PHY
86
87 #ifdef NS83865PHY
88 #include "ns83865phy.h"
89 #define PHYTYPE "NS83865"
90 #else
91 #ifdef TDK78Q2120PHY
92 #include "tdk78phy.h"
93 #define PHYTYPE "TDK78Q2120"
94 #endif
95 #endif
96
97 #ifdef CONFIG_SYSCTL
98 #include <linux/proc_fs.h>
99 #include <linux/sysctl.h>
100 #endif // CONFIG_SYSCTL
101
102 //#undef na_dma // Force "Pio" mode
103 #if defined (na_dma)
104 #define MTIPDMA_AVAIL
105 #define mtip_dma_control_port ((np_dma *) (((unsigned int) (na_dma)) | 0x80000000))
106 #define IOTYPE "DMA"
107
108 #else
109 #undef MTIPDMA_AVAIL
110 #define IOTYPE "PIO"
111 #endif // na_dma
112
113
114 /*----------------------------------------------------------------------
115 . DEBUGGING LEVELS
116 .
117 . 0 for normal operation
118 . 1 for slightly more details
119 . 2 for interrupt tracking, status flags
120 . 3 for packet info
121 . 4 for complete packet dumps
122 -----------------------------------------------------------------------*/
123 //#define MTIP_DEBUG 4
124 //#define MTIP_DEBUG 3
125 //#define MTIP_DEBUG 2
126 //#define MTIP_DEBUG 1
127 #define MTIP_DEBUG 0
128
129 #if (MTIP_DEBUG > 2 )
130 #define PRINTK3(args...) printk(args)
131 #else
132 #define PRINTK3(args...)
133 #endif
134
135 #if MTIP_DEBUG > 1
136 #define PRINTK2(args...) printk(args)
137 #else
138 #define PRINTK2(args...)
139 #endif
140
141 #ifdef MTIP_DEBUG
142 #define PRINTK(args...) printk(args)
143 #else
144 #define PRINTK(args...)
145 #endif
146
147
148 typedef unsigned char byte;
149 typedef unsigned short word;
150 typedef unsigned long int dword;
151
152
153 /*-----------------------------------------------------------
154 Port address(es). Array must end in zero.
155 */
156 #if defined(CONFIG_EXCALIBUR)
157 static unsigned int mtip_portlist[] =
158 { ((int)
159 ((((unsigned int) (na_mtip_mac_control_port)) | 0x80000000)))
160 , 0 };
161 static unsigned int mtip_irqlist[] =
162 { na_mtip_mac_rxFIFO_irq, 0 };
163 #define PIO_port_rxFIFO (((unsigned int) (na_mtip_mac_rxFIFO)) | 0x80000000)
164 #define PIO_port_txFIFO (((unsigned int) (na_mtip_mac_txFIFO)) | 0x80000000)
165 #else
166 #define PIO_port_rxFIFO (((unsigned int) (na_mtip_mac_rxFIFO)))
167 #define PIO_port_txFIFO (((unsigned int) (na_mtip_mac_txFIFO)))
168 ............
169 #endif // CONFIG_EXCALIBUR
170
171
172 struct mtip_local
173 {
174 struct net_device_stats stats;
175
176 #ifdef CONFIG_SYSCTL
177
178 // Root directory /proc/sys/dev
179 // Second entry must be null to terminate the table
180 ctl_table root_table[2];
181
182 // Directory for this device /proc/sys/dev/ethX
183 // Again the second entry must be zero to terminate
184 ctl_table eth_table[2];
185
186 // This is the parameters (file) table
187 ctl_table param_table[CTL_MTIP_LAST_ENTRY];
188
189 // Saves the sysctl header returned by register_sysctl_table()
190 // we send this to unregister_sysctl_table()
191 struct ctl_table_header *sysctl_header;
192
193 // Parameter variables (files) go here
194 char ctl_info[1024]; // ?...?
195
196 /*
197 ....tbd.............
198 int ctl_xxxxxx's;
199 ......................*/
200
201 #endif // CONFIG_SYSCTL
202 };
203
204
205 /*-----------------------------------------------------------
206 | Print out a packet.
207 */
208 #if MTIP_DEBUG > 3
209 static void print_packet( byte * buf, int length )
210 {
211 #if 1
212 #if MTIP_DEBUG > 3
213 int i;
214 int remainder;
215 int lines;
216 #endif
217
218 printk("Packet length %d \n", length );
219
220 #if MTIP_DEBUG > 3
221 lines = length / 16;
222 remainder = length % 16;
223
224 for ( i = 0; i < lines ; i ++ ) {
225 int cur;
226
227 for ( cur = 0; cur < 8; cur ++ ) {
228 byte a, b;
229
230 a = *(buf ++ );
231 b = *(buf ++ );
232 printk("%02x %02x ", a, b );
233 }
234 printk("\n");
235 }
236 for ( i = 0; i < remainder/2 ; i++ ) {
237 byte a, b;
238
239 a = *(buf ++ );
240 b = *(buf ++ );
241 printk("%02x %02x ", a, b );
242 }
243 printk("\n");
244 #endif
245 #endif
246 }
247 #endif
248
249
250 /*-----------------------------------------------------------
251 */
252 #define PRINTSTDPHYREGS(pmac) \
253 \
254 printk(" PhyCtl0: %04X" \
255 " PhySts1: %04X" \
256 " PhyID1: %04X\n", \
257 (pmac->mdio0).CONTROL, \
258 (pmac->mdio0).STATUS, \
259 (pmac->mdio0).PHY_ID1); \
260 printk(" PhyID2: %04X" \
261 " PhyAdv4: %04X" \
262 " PhyRemcap5: %04X\n", \
263 (pmac->mdio0).PHY_ID2, \
264 (pmac->mdio0).ADV, \
265 (pmac->mdio0).REMADV);
266
267
268 #ifdef NS83865PHY
269 #define PRINTNS83PHYREGS(pmac, \
270 nsIntstsReg20, \
271 nsIntieReg21, \
272 nsLnkstsReg17) \
273 \
274 PRINTSTDPHYREGS(pmac); \
275 \
276 printk(" Ns20Ists:%04X" \
277 " Ns21Intie:%04X" \
278 " Ns17Lnksts: %04X\n", \
279 nsIntstsReg20, \
280 nsIntieReg21, \
281 nsLnkstsReg17);
282 #endif
283
284
285 #ifdef TDK78Q2120PHY
286 #define PRINTTDKPHYREGS(pmac, \
287 tdkintCtlStsReg17, \
288 tdkDiagReg18) \
289 \
290 PRINTSTDPHYREGS(pmac); \
291 \
292 printk(" Tdk16: %04X" \
293 " Tdk17Int: %04X" \
294 " Tdk18Diag: %04X\n", \
295 (pmac->mdio0).reg10, \
296 tdkintCtlStsReg17, \
297 tdkDiagReg18);
298 #endif
299
300
301 /*-----------------------------------------------------------
302 */
303 unsigned int gMtipDisabledRxints;
304 unsigned int gMtipDisabledTxints;
305 unsigned long gMtipDiscardSink; // RxFifo discard
306 unsigned int gMtipDmaints;
307 unsigned int gMtipDmaintsBusy;
308 unsigned int gMtipDmaintsBusyDone;
309 unsigned int gMtipDmaintsNoDone;
310 unsigned int gMtipRxints;
311 unsigned int gMtipRxintsRxdmaBusy;
312 unsigned int gMtipRxintsRxdmaQued;
313 unsigned int gMtipRxNoints;
314 int gMtipRxSkbFifoNumL32s;
315 word gMtipRxSkbframelenbyts;
316 unsigned int gMtipTxints;
317 unsigned int gMtipTxintsIncomplete;
318 int gMtipTxSkbFifoNumL32s;
319 word gMtipTxSkbframelenbyts;
320 unsigned int gMtipUnexpDmaints;
321 unsigned int gMtipUnexpRxints;
322 unsigned int gMtipUnexpTxints;
323 byte *gpMtipRxData;
324 struct sk_buff *gpMtipRxSkbInProg;
325 byte *gpMtipTxData;
326 struct sk_buff *gpMtipTxSkbInProg;
327
328 #if defined (MTIPDMA_AVAIL)
329
330 unsigned int gMtipDmaQ;
331 unsigned int gMtipDmaState;
332
333 unsigned char gMtipTmpDmaBuf[MTIP_MAC_MAX_FRAME_SIZE + MTIP_MI_XBUF_BYTS];
334 // Nios alignment requirements...very inconvenient...
335 // for now...but should be in "on chip sram" if any...
336 // (perhaps used as "ring[s]"...
337 // for now...rx and tx share same temporary 1 only "dma buffer"
338
339 enum
340 {
341 Mtip_DmaQ_TxSkb2Tmp = (1 << 0)
342 , Mtip_DmaQ_RxFifo2Tmp = (1 << 1)
343 , Mtip_DmaQ_RxFifo2Trash = (1 << 2)
344 };
345
346 enum
347 {
348 Mtip_DmaState_Idle = 0
349 , Mtip_DmaState_RxFifo2Tmp = 1
350 , Mtip_DmaState_RxTmp2Skb = 2
351 , Mtip_DmaState_TxSkb2Tmp = 3
352 , Mtip_DmaState_TxTmp2Fifo = 4
353 , Mtip_DmaState_RxFifo2Trash = 5
354 };
355
356
357 /*-----------------------------------------------------------
358 */
359 static void dma_start
360 (int bytes_per_transfer,
361 void *source_address,
362 void *destination_address,
363 int transfer_count, // In units of bytes_per_transfer
364 int mode) // wcon, rcon, i_en, ... bit(s)
365 {
366 // Caller must have already flushed any "memory" range
367 // involved in this transfer that stands at risk.
368
369 int control_bits = 0;
370 np_dma *dma = mtip_dma_control_port;
371
372 dma->np_dmacontrol = 0;
373 // | 1. Halt anything that's going on
374
375 dma->np_dmastatus = 0;
376 dma->np_dmareadaddress = (int)source_address;
377 dma->np_dmawriteaddress = (int)destination_address;
378 dma->np_dmalength = transfer_count * bytes_per_transfer;
379
380 control_bits =
381 mode
382 | (bytes_per_transfer & 7) // low three bits of control reg
383 | ((bytes_per_transfer & 8) ? np_dmacontrol_doubleword_mask : 0)
384 | ((bytes_per_transfer & 16) ? np_dmacontrol_quadword_mask : 0)
385 | np_dmacontrol_leen_mask // enable length
386 // | np_dmacontrol_reen_mask //;dgt;tmp;test; Enable read end-of-packet
387 // | np_dmacontrol_ween_mask //;dgt;tmp;test; Enable write end-of-packet
388 | np_dmacontrol_go_mask; // and... go!
389
390 dma->np_dmacontrol = control_bits;
391
392 return;
393 }
394
395 /*-----------------------------------------------------------
396 */
397 void dma_start_RxFifo2Tmp(void)
398 {
399 // Caller must have already set gMtipDmaState
400 // to Mtip_DmaState_RxFifo2Tmp (under semaphore),
401 // and disabled Rx ready interrupts.
402
403 dcache_push (((unsigned long) (gpMtipRxData)),
404 gMtipRxSkbframelenbyts);
405
406 dma_start
407 (4, // Byts per transfer
408 ((void *) (na_mtip_mac_rxFIFO)), // 32 bit source fifo
409 gMtipTmpDmaBuf, // 32 bit aligned dest
410 gMtipRxSkbFifoNumL32s, // # of 4 byte transfers
411 ( np_dmacontrol_rcon_mask // Source is a Fifo
412 | np_dmacontrol_i_en_mask // Dma done:interrupt
413 ));
414 }
415
416 /*-----------------------------------------------------------
417 */
418 void dma_start_TxSkb2Tmp(void)
419 {
420 // Caller must have already set gMtipDmaState
421 // to Mtip_DmaState_TxSkb2Tmp (under semaphore)
422
423 dcache_push (((unsigned long) (gpMtipTxData)),
424 gMtipTxSkbframelenbyts);
425 dma_start
426 (2, // Byts per transfer
427 gpMtipTxData, // 16 bit aligned src,
428 gMtipTmpDmaBuf, // 32 bit aligned dest,
429 (gMtipTxSkbFifoNumL32s << 1), // # of 2 byte transfers
430 ( 0 // Neither end a fifo
431 | np_dmacontrol_i_en_mask // Dma done:interrupt
432 ));
433 // At the risk of possibly incurring twice the copy
434 // time, save some cpu cycles by assuming outbound
435 // data starts on a 16 bit boundary (Have never
436 // empirically observed it on anything but...)...
437 }
438
439 /*-----------------------------------------------------------
440 */
441 void dma_start_RxFifo2Trash(void)
442 {
443 // Caller must have already set gMtipDmaState
444 // to Mtip_DmaState_RxFifo2Trash (under semaphore),
445 // and disabled Rx ready interrupts.
446
447 dma_start
448 (4, // Byts per transfer
449 ((void *) (na_mtip_mac_rxFIFO)), // 32 bit source fifo
450 ((unsigned char *)
451 &(gMtipDiscardSink)), // 32 bit aligned dest
452 gMtipRxSkbFifoNumL32s, // # of 4 byte transfers
453 ( np_dmacontrol_rcon_mask // Source is a Fifo
454 | np_dmacontrol_wcon_mask // Dest is a sinkhole
455 | np_dmacontrol_i_en_mask // Dma done:interrupt
456 ));
457 }
458 #endif // MTIPDMA_AVAIL
459
460 /*-----------------------------------------------------------
461 | Entry condition: Cpu interrupts DISabled.
462 */
463 static void mtip_NuRxReady(struct net_device *dev,
464 unsigned int cmplnstatus)
465 {
466 // Caller must have already verified cmplnstatus's
467 // mmac_rcs_VALID_mask bit is SET.
468
469 struct mtip_local *lp;
470 np_mtip_mac *pmac;
471
472 lp = (struct mtip_local *)dev->priv;
473 pmac = ((np_mtip_mac *) dev->base_addr);
474
475 gMtipRxSkbframelenbyts = ( cmplnstatus & mmac_rcs_FRAME_LENGTH_mask );
476
477 PRINTK3
478 // printk
479 (
480 "mtip_NuRxReady:%s, asts:0x%04X, csts:0x%08X, Len:%d\n",
481 dev->name,
482 pmac->AVL_STATUS,
483 cmplnstatus,
484 gMtipRxSkbframelenbyts);
485
486 if(gMtipRxSkbframelenbyts == 0)
487 {
488 // PRINTK3
489 printk
490 (
491 "mtip_NuRxReady:%s, ZERO len frame,"
492 " asts:0x%04X, csts:0x%08X\n",
493 dev->name,
494 pmac->AVL_STATUS,
495 cmplnstatus);
496 }
497
498 gMtipRxSkbFifoNumL32s = ((gMtipRxSkbframelenbyts + 3) >> 2);
499
500 if( cmplnstatus & mmac_rcs_ERROR_mask )
501 {
502 PRINTK3
503 // printk
504 (
505 "mtip_NuRxReady:%s, Bad frame:0x%08X, Len:%d\n",
506 dev->name,
507 cmplnstatus,
508 gMtipRxSkbframelenbyts);
509
510 lp->stats.rx_errors++;
511
512 //;...can't differentiate...lp->stats.rx_frame_errors++;
513 //;...can't differentiate...lp->stats.rx_length_errors++;
514 //;...can't differentiate...lp->stats.rx_crc_errors++;
515
516 #if defined (MTIPDMA_AVAIL)
517 pmac->IRQ_CONFIG &= (~(mmac_ic_EN_RX_FRAME_AVAILABLE_mask));
518 // disable rx ready interrupt
519
520 if(gMtipDmaState == Mtip_DmaState_Idle)
521 {
522 gMtipDmaState = Mtip_DmaState_RxFifo2Trash;
523
524 dma_start_RxFifo2Trash();
525 }
526 else
527 {
528 gMtipDmaQ |= Mtip_DmaQ_RxFifo2Trash;
529 }
530
531 return;
532 #else
533 {
534 int FifoL32 = 0;
535 pmac->RX_CMD_STAT = mmac_rcs_READ_CMD_mask;
536 while( (pmac->RX_CMD_STAT) & mmac_rcs_READ_CMD_mask )
537 {
538 FifoL32 |= *((volatile unsigned long *) PIO_port_rxFIFO);
539 }
540 gMtipDiscardSink = FifoL32;
541 }
542
543 return;
544 #endif // MTIPDMA_AVAIL
545 }
546
547 //;...?...lp->stats.multicast++;
548
549 if(gMtipRxSkbframelenbyts > MTIP_MAC_MAX_FRAME_SIZE)
550 {
551 // PRINTK3
552 printk
553 (
554 // KERN_NOTICE
555 "mtip_NuRxReady:%s, oversized %d byte packet.\n",
556 dev->name,
557 gMtipRxSkbframelenbyts);
558 goto Dropfrm_label;
559 }
560
561 gpMtipRxSkbInProg =
562 dev_alloc_skb( (gMtipRxSkbFifoNumL32s << 2) +
563 MTIP_SKB_XBUF_BYTS );
564 // Extra bytes: Dma requirements
565
566 if ( gpMtipRxSkbInProg == NULL )
567 {
568 PRINTK3
569 // printk
570 (
571 // KERN_NOTICE
572 "mtip_NuRxReady:%s, Low memory, packet dropped.\n",
573 dev->name);
574 goto Dropfrm_label;
575 }
576
577 skb_reserve( gpMtipRxSkbInProg, 2 ); /* 16 bit alignment */
578
579 gpMtipRxSkbInProg->dev = dev;
580
581 gpMtipRxData = skb_put( gpMtipRxSkbInProg, gMtipRxSkbframelenbyts );
582
583 lp->stats.rx_packets++;
584
585 #if defined (MTIPDMA_AVAIL)
586 pmac->IRQ_CONFIG &= (~(mmac_ic_EN_RX_FRAME_AVAILABLE_mask));
587 // disable rx ready interrupt
588
589 if(gMtipDmaState == Mtip_DmaState_Idle)
590 {
591 gMtipDmaState = Mtip_DmaState_RxFifo2Tmp;
592
593 dma_start_RxFifo2Tmp();
594 }
595 else
596 {
597 gMtipDmaQ |= Mtip_DmaQ_RxFifo2Tmp;
598 }
599
600 return;
601 #else
602 insl(((unsigned long) PIO_port_rxFIFO),
603 gpMtipRxData,
604 gMtipRxSkbFifoNumL32s);
605
606 PRINTK3
607 (
608 "%s:Received %d byte Packet 0x%08X\n",
609 dev->name,
610 gMtipRxSkbframelenbyts,
611 ((unsigned long) gpMtipRxData));
612
613 #if MTIP_DEBUG > 3
614 print_packet( gpMtipRxData, gMtipRxSkbframelenbyts );
615 #endif
616
617 gpMtipRxSkbInProg->protocol =
618 eth_type_trans(gpMtipRxSkbInProg, dev );
619
620 netif_rx(gpMtipRxSkbInProg);
621
622 pmac->RX_CMD_STAT = mmac_rcs_READ_CMD_mask;
623 // acknowledge frame reception
624
625 return;
626 #endif // MTIPDMA_AVAIL
627
628 Dropfrm_label:
629
630 /* Oversized Rx frame, or dev_alloc_skb(...) failure */
631
632 lp->stats.rx_dropped++;
633
634 #if defined (MTIPDMA_AVAIL)
635 pmac->IRQ_CONFIG &= (~(mmac_ic_EN_RX_FRAME_AVAILABLE_mask));
636 // disable rx ready interrupt
637
638 if(gMtipDmaState == Mtip_DmaState_Idle)
639 {
640 gMtipDmaState = Mtip_DmaState_RxFifo2Trash;
641
642 dma_start_RxFifo2Trash();
643 }
644 else
645 {
646 gMtipDmaQ |= Mtip_DmaQ_RxFifo2Trash;
647 }
648
649 return;
650 #else
651 {
652 int FifoL32 = 0;
653 int FifoLoop;
654 for ( FifoLoop = 0; FifoLoop < gMtipRxSkbFifoNumL32s ; FifoLoop++ )
655 {
656 FifoL32 |= *((volatile unsigned long *) PIO_port_rxFIFO);
657 }
658 gMtipDiscardSink = FifoL32;
659 }
660
661 pmac->RX_CMD_STAT = mmac_rcs_READ_CMD_mask;
662 // acknowledge frame reception
663
664 return;
665 #endif // MTIPDMA_AVAIL
666 }
667
668 #if defined (MTIPDMA_AVAIL)
669 /*-----------------------------------------------------------
670 | Driver entry point
671 |
672 | Entry condition: Cpu interrupts DISabled.
673 */
674 static irqreturn_t mtip_DmaInterrupt(int irq,
675 void *dev_id,
676 struct pt_regs *regs)
677 {
678 unsigned int cmplnstatus;
679 struct net_device *dev = dev_id;
680 np_dma *dma = mtip_dma_control_port;
681 int old_dmastatus;
682 np_mtip_mac *pmac;
683
684 ++gMtipDmaints;
685
686 pmac = ((np_mtip_mac *) dev->base_addr);
687 old_dmastatus = dma->np_dmastatus;
688
689 if(old_dmastatus & np_dmastatus_busy_mask)
690 {
691 ++gMtipDmaintsBusy;
692
693 if(old_dmastatus & np_dmastatus_done_mask)
694 {
695 ++gMtipDmaintsBusyDone;
696 }
697
698 return IRQ_HANDLED;
699 // ...This could be interesting...!
700 }
701
702 if(!(old_dmastatus & np_dmastatus_done_mask))
703 {
704 ++gMtipDmaintsNoDone;
705 // presumably gMtipDmaState .eq. Mtip_DmaState_Idle
706 }
707
708 dma->np_dmastatus = 0; // Clear done bit (and ack the interrupt)
709
710 switch (gMtipDmaState)
711 {
712 case Mtip_DmaState_RxFifo2Tmp:
713
714 pmac->RX_CMD_STAT = mmac_rcs_READ_CMD_mask;
715 // acknowledge frame reception
716
717 gMtipDmaState = Mtip_DmaState_RxTmp2Skb;
718 dma_start
719 (2, // Byts per transfer
720 gMtipTmpDmaBuf, // 32 bit aligned src
721 gpMtipRxData, // 16 bit aligned dest
722 (gMtipRxSkbFifoNumL32s << 1), // # of 2 byte transfers
723 ( 0 // Neither end a fifo
724 | np_dmacontrol_i_en_mask // Dma done:interrupt
725 ));
726
727 goto DmaIntExit_label;
728
729 case Mtip_DmaState_RxTmp2Skb:
730
731 //;see state RxFifo2Tmp; pmac->RX_CMD_STAT = mmac_rcs_READ_CMD_mask;
732 // acknowledge frame reception
733
734 PRINTK3
735 (
736 "%s:Received %d byte Packet 0x%08X\n",
737 dev->name,
738 gMtipRxSkbframelenbyts,
739 ((unsigned long) gpMtipRxData));
740
741 #if MTIP_DEBUG > 3
742 print_packet( gpMtipRxData, gMtipRxSkbframelenbyts );
743 #endif
744
745 gpMtipRxSkbInProg->protocol =
746 eth_type_trans(gpMtipRxSkbInProg, dev );
747
748 netif_rx(gpMtipRxSkbInProg);
749
750 pmac->IRQ_CONFIG |= mmac_ic_EN_RX_FRAME_AVAILABLE_mask;
751 // enable rx ready interrupt
752 // Note DmaMaybe2Idle_label will find NEITHER
753 // of gMtipDmaQ's Mtip_DmaQ_RxFifo2Tmp NOR
754 // Mtip_DmaQ_RxFifo2Trash bits set!
755
756 goto DmaMaybe2Idle_label;
757
758 case Mtip_DmaState_TxSkb2Tmp:
759
760 gMtipDmaState = Mtip_DmaState_TxTmp2Fifo;
761 pmac->TX_CMD_STAT = (gMtipTxSkbframelenbyts |
762 mmac_tcs_FRAME_COMPLETE_mask);
763 dma_start
764 (4, // Byts per transfer
765 gMtipTmpDmaBuf, // 32 bit aligned src
766 ((void *) (na_mtip_mac_txFIFO)), // 32 bit dest fifo
767 gMtipTxSkbFifoNumL32s, // # of 4 byte transfers
768 ( np_dmacontrol_wcon_mask // Dest is a Fifo
769 | np_dmacontrol_i_en_mask // Dma done:interrupt
770 ));
771
772 goto DmaIntExit_label;
773
774 case Mtip_DmaState_TxTmp2Fifo:
775
776 pmac->IRQ_CONFIG |= mmac_ic_EN_TX_FIFO_EMPTY_mask;
777 // enable tx done interrupt
778
779 goto DmaMaybe2Idle_label;
780
781 case Mtip_DmaState_RxFifo2Trash:
782
783 pmac->RX_CMD_STAT = mmac_rcs_READ_CMD_mask;
784 // acknowledge frame reception
785
786 pmac->IRQ_CONFIG |= mmac_ic_EN_RX_FRAME_AVAILABLE_mask;
787 // enable rx ready interrupt
788 // Note DmaMaybe2Idle_label will find NEITHER
789 // of gMtipDmaQ's Mtip_DmaQ_RxFifo2Tmp NOR
790 // Mtip_DmaQ_RxFifo2Trash bits set!
791 goto DmaMaybe2Idle_label;
792
793 // case Mtip_DmaState_Idle:
794 default:
795
796 ++gMtipUnexpDmaints;
797
798 PRINTK3
799 // printk
800 (
801 "mtip_DmaInterrupt:%s,"
802 " Unexpected state:0x%02X"
803 " (sts:0x%02X,"
804 " ctl:0x%04X)\n",
805 dev->name,
806 gMtipDmaState,
807 dma->np_dmastatus,
808 dma->np_dmacontrol);
809
810 // fall thru to DmaMaybe2Idle_label
811 }
812
813 DmaMaybe2Idle_label:
814
815 if(gMtipDmaQ & Mtip_DmaQ_TxSkb2Tmp)
816 {
817 gMtipDmaQ &= (~(Mtip_DmaQ_TxSkb2Tmp));
818
819 gMtipDmaState = Mtip_DmaState_TxSkb2Tmp;
820
821 dma_start_TxSkb2Tmp();
822 }
823 else if (gMtipDmaQ & Mtip_DmaQ_RxFifo2Tmp)
824 {
825 gMtipDmaQ &= (~(Mtip_DmaQ_RxFifo2Tmp));
826
827 gMtipDmaState = Mtip_DmaState_RxFifo2Tmp;
828
829 dma_start_RxFifo2Tmp();
830 }
831 else if (gMtipDmaQ & Mtip_DmaQ_RxFifo2Trash)
832 {
833 gMtipDmaQ &= (~(Mtip_DmaQ_RxFifo2Trash));
834
835 gMtipDmaState = Mtip_DmaState_RxFifo2Trash;
836
837 dma_start_RxFifo2Trash();
838 }
839 else
840 {
841 gMtipDmaState = Mtip_DmaState_Idle;
842
843 if(( (pmac->AVL_STATUS) & (mmac_as_RX_FRAME_AVAILABLE_mask) ))
844 {
845 cmplnstatus = pmac->RX_CMD_STAT;
846 if(( cmplnstatus & mmac_rcs_VALID_mask ))
847 {
848 ++gMtipRxNoints;
849
850 mtip_NuRxReady(dev, cmplnstatus);
851 // mtip_NuRxReady (re)disables Rx interrupts...
852 }
853 }
854 }
855
856 DmaIntExit_label:
857
858 return IRQ_HANDLED;
859 }
860 #endif // MTIPDMA_AVAIL
861
862
863 #ifdef CONFIG_SYSCTL
864 /*-----------------------------------------------------------
865 |
866 */
867 static const char mtip_info_string[] =
868 "\n"
869 "info Provides this information blurb\n"
870 ".... Remind author to complete\n"
871 " ... ...\n"
872 ".... Remind author to complete\n"
873 "";
874 #endif /* endif CONFIG_SYSCTL */
875
876
877 #ifdef CONFIG_SYSCTL
878 /*-----------------------------------------------------------
879 | Sysctl handler for all integer parameters
880 */
881 static int mtip_sysctl_handler(ctl_table *ctl,
882 int write,
883 struct file *filp,
884 void *buffer,
885 size_t *lenp)
886 {
887 int ret;
888
889 ret = 0;
890 /*
891 ....tbd.............
892 .....................*/
893
894 return ret;
895 }
896 #endif /* endif CONFIG_SYSCTL */
897
898
899 #ifdef CONFIG_SYSCTL
900 /*-----------------------------------------------------------
901 | Sysctl registration function for all parameters (files)
902 |
903 | Initilizes device's sysctl proc filesystem
904 |
905 | Entry condition: Cpu interrupts ENabled.
906 */
907 static void mtip_sysctl_register(struct net_device *dev)
908 {
909 struct mtip_local *lp = (struct mtip_local *)dev->priv;
910 static int ctl_name = CTL_MTIP1000;
911 ctl_table* ct;
912 int i;
913
914 // Make sure the ctl_tables start out as all zeros
915 memset(lp->root_table, 0, sizeof lp->root_table);
916 memset(lp->eth_table, 0, sizeof lp->eth_table);
917 memset(lp->param_table, 0, sizeof lp->param_table);
918
919 // Initialize the root table
920 ct = lp->root_table;
921 ct->ctl_name = CTL_DEV;
922 ct->procname = "dev";
923 ct->maxlen = 0;
924 ct->mode = 0555;
925 ct->child = lp->eth_table;
926 // remaining fields are zero
927
928 // Initialize the ethX table (this device's table)
929 ct = lp->eth_table;
930 ct->ctl_name = ctl_name++; // Must be unique
931 ct->procname = dev->name;
932 ct->maxlen = 0;
933 ct->mode = 0555;
934 ct->child = lp->param_table;
935 // remaining fields are zero
936
937 // Initialize the parameter (files) table
938 // Make sure the last entry remains null
939 ct = lp->param_table;
940 for (i = 0; i < (CTL_MTIP_LAST_ENTRY-1); ++i)
941 {
942 // Initialize fields common to all table entries
943 ct[i].proc_handler = mtip_sysctl_handler;
944 ct[i].extra1 = (void*)dev; // Save our device pointer
945 ct[i].extra2 = (void*)lp; // Save our mtip_local data pointer
946 }
947
948 // INFO - this is our only string parameter
949 i = 0;
950 ct[i].proc_handler = proc_dostring; // use default handler
951 ct[i].ctl_name = CTL_MTIP_INFO;
952 ct[i].procname = "info";
953 ct[i].data = (void*)mtip_info_string;
954 ct[i].maxlen = sizeof mtip_info_string;
955 ct[i].mode = 0444; // Read only
956
957 // SWVER
958 ++i;
959 ct[i].proc_handler = proc_dostring; // use default handler
960 ct[i].ctl_name = CTL_MTIP_SWVER;
961 ct[i].procname = "swver";
962 ct[i].data = (void*)version;
963 ct[i].maxlen = sizeof version;
964 ct[i].mode = 0444; // Read only
965
966 /*
967 ....tbd.............
968 .....................*/
969 #ifdef MTIP_DEBUG
970 /*
971 ....tbd.............
972 .....................*/
973 #endif // MTIP_DEBUG
974
975 // Register /proc/sys/dev/ethX
976 lp->sysctl_header = register_sysctl_table(lp->root_table, 1);
977 }
978 #endif /* endif CONFIG_SYSCTL */
979
980
981 #ifdef CONFIG_SYSCTL
982 /*-----------------------------------------------------------
983 | Sysctl unregistration when driver closed
984 */
985 static void mtip_sysctl_unregister(struct net_device *dev)
986 {
987 struct mtip_local *lp = (struct mtip_local *)dev->priv;
988
989 unregister_sysctl_table(lp->sysctl_header);
990 }
991 #endif /* endif CONFIG_SYSCTL */
992
993
994 void mtip_phymac_synch (struct net_device *dev, int callerflg)
995 {
996 unsigned long cmdcfg;
997 unsigned long phy100mbitflg;
998 unsigned long phyfulldupflg;
999 unsigned long phymr1sts;
1000 unsigned long phyanegfailedflg;
1001 np_mtip_mac *pmac;
1002
1003 pmac = ((np_mtip_mac *) dev->base_addr);
1004
1005 phymr1sts = (pmac->mdio0).STATUS;
1006 /* Read twice to get CURRENT status...?... */
1007 phymr1sts = (pmac->mdio0).STATUS;
1008
1009 cmdcfg = pmac->COMMAND_CONFIG;
1010
1011 #ifdef NS83865PHY
1012 unsigned long phymr17linkan;
1013
1014 phymr17linkan = (pmac->mdio0).reg11;
1015
1016 phy100mbitflg = (phymr17linkan & 0x0008);
1017 phyfulldupflg = (phymr17linkan & 0x0002);
1018
1019 phyanegfailedflg = (((pmac->mdio0).reg14) & 0x0100);
1020 #else
1021 #if defined(TDK78Q2120PHY)
1022 {
1023 unsigned long phymr18diag;
1024
1025 phymr18diag = (pmac->mdio0).reg12;
1026
1027 phy100mbitflg = (phymr18diag & 0x0400);
1028 phyanegfailedflg = (phymr18diag & 0x1000);
1029 phyfulldupflg = (phymr18diag & 0x0800);
1030 }
1031 #else
1032 ...?...
1033 ...?...
1034 #endif // TDK78Q2120PHY
1035 #endif // NS83865PHY
1036
1037 if(callerflg == 0)
1038 {
1039 // Caller = NOT Phy interrupt handler
1040
1041 if((phymr1sts & 0x00000004) != 0)
1042 {
1043 // Link is ostensibly OK
1044
1045 if((((pmac->mdio0).CONTROL) & 0x00001000) != 0)
1046 {
1047 // Auto negotiation ostensibly enabled
1048
1049 if((phymr1sts & 0x00000020) != 0)
1050 {
1051 // Auto negotiation ostensibly has completed
1052
1053 if(phyanegfailedflg)
1054 {
1055 // Auto negotiation ostensibly has failed
1056
1057 if(phy100mbitflg | phyfulldupflg)
1058 {
1059 // Auto negotiation failure expected to
1060 // have fallen back to 10 mbit half
1061 // duplex - perhaps phy registers aren't
1062 // actually available, and we've been
1063 // reading 0xFFFF's...
1064
1065 // A 10 mbit, 1/2 duplex remote partner
1066 // mandates a 1/2 duplex Emac (else any
1067 // amount of traffic at all will almost
1068 // certainly collide up a storm...)
1069 // 100 mbit remote partners seem to allow
1070 // duplex mismatches without severe
1071 // loss, at least at the low end of
1072 // their nominal capacity.
1073 // A 10 mbit, full duplex remote partner
1074 // probably also requires a matched Emac,
1075 // but hasn't been confirmed...
1076
1077 printk("\nmtip_phymac_synch:%s"
1078 " No phyregs?-assuming HalfD\n",
1079 dev->name);
1080
1081 pmac->COMMAND_CONFIG |= mmac_cc_HD_ENA_mask;
1082
1083 if((pmac->COMMAND_CONFIG &
1084 mmac_cc_HD_ENA_mask) == 0)
1085 {
1086 printk("\nmtip_phymac_synch:%s"
1087 " HalfD phy, but FullD emac\n",
1088 dev->name);
1089 }
1090
1091 return;
1092 }
1093 }
1094 }
1095 }
1096 }
1097 }
1098 // else
1099 // {
1100 // // Caller = Phy interrupt handler
1101 // // If we've got a phy interrupt, then we're so likely
1102 // // to also have actual phy registers that we won't
1103 // // bother trying to confirm...
1104 // }
1105
1106 #if defined(ANNOUNCEPHY)
1107 printk("\nmtip_phymac_synch:%s MR1: 0x%08lX\n",
1108 dev->name,
1109 phymr1sts);
1110 if((phymr1sts & 0x00000002) != 0)
1111 {
1112 printk(" Jabber\n");
1113 }
1114 if((phymr1sts & 0x00000010) != 0)
1115 {
1116 printk(" Remote Fault\n");
1117 }
1118 if((phymr1sts & 0x00000020) != 0)
1119 {
1120 printk(" Autoneg'd\n");
1121 }
1122 #endif
1123
1124 if((phymr1sts & 0x00000004) != 0)
1125 {
1126 /* Phy MR1 (status register) indicates link is (now) OK. */
1127
1128 #if defined(ANNOUNCEPHY)
1129 printk(" Link OK:\n");
1130 #endif
1131
1132 if(phyfulldupflg)
1133 {
1134 /* Link is (now) running full duplex. */
1135
1136 pmac->COMMAND_CONFIG = (cmdcfg &
1137 (~(mmac_cc_HD_ENA_mask)));
1138
1139 #if defined(ANNOUNCEPHY)
1140 printk(" FullD\n");
1141 #endif
1142 }
1143 else
1144 {
1145 /* Link is (now) running half duplex. */
1146
1147 pmac->COMMAND_CONFIG = (cmdcfg | mmac_cc_HD_ENA_mask);
1148
1149 if((pmac->COMMAND_CONFIG & mmac_cc_HD_ENA_mask) == 0)
1150 {
1151 printk("\nmtip_phymac_synch:%s"
1152 " HalfD phy, but FullD emac\n",
1153 dev->name);
1154 }
1155
1156 #if defined(ANNOUNCEPHY)
1157 printk(" HalfD\n");
1158 #endif
1159 }
1160
1161 #if defined(ANNOUNCEPHY)
1162 printk(" %s\n",
1163 (phy100mbitflg) ? "100BASE-TX" : "10BASE-T");
1164 #endif
1165 }
1166 #if defined(ANNOUNCEPHY)
1167 else
1168 {
1169 printk(" Link Down\n");
1170
1171 // ...what if link comes up without a phy interrupt
1172 // ... and the emac/phy duplexs don't match...?...
1173 }
1174 #endif
1175
1176 #if defined(ANNOUNCEPHY)
1177 printk(" CMDCF: 0x%08X\n",
1178 pmac->COMMAND_CONFIG);
1179 printk("\n");
1180 #endif
1181
1182 return;
1183 }
1184
1185
1186 /*-----------------------------------------------------------
1187 | Entry condition: Cpu interrupts ENabled.
1188 */
1189 static void mtip_phy_configure(struct net_device* dev)
1190 {
1191 /* No need to (re)configure advertisement register or (re)start */
1192 /* auto negotiation after the reset that our caller has probably */
1193 /* recently performed if auto negotiation is enabled by default */
1194 /* and all capabilities are to be advertised. Advertisement */
1195 /* register has already defaulted to our capabilities on last */
1196 /* reset, and phy automatically renegotiates when reset, and/or */
1197 /* when link comes (back) up, etc. */
1198
1199 /* If phy interrupts are required, DO need to reconfigure the */
1200 /* phy's interrupt control register after the reset our caller */
1201 /* has probably recently performed. */
1202
1203 unsigned int msecswaited;
1204 unsigned int my_ad_caps; // My Advertised capabilities
1205 unsigned int my_phy_caps; // My PHY capabilities
1206 np_mtip_mac *pmac;
1207
1208 pmac = ((np_mtip_mac *) dev->base_addr);
1209
1210 my_ad_caps = PHY_ADV_CSMA;
1211 my_phy_caps = (pmac->mdio0).STATUS;
1212
1213 /* Note Mx TDK phy board's (9) switches control its inherrent */
1214 /* capabilibles (at the moment, prototype:all off = */
1215 /* all capabilities available).. */
1216
1217 if(my_phy_caps & (PHY_STS_CAP_TXF_MASK))
1218 {
1219 // if(..we're allowing 100mbit full duplex...)
1220 {
1221 my_ad_caps |= PHY_ADV_TX_FDX;
1222 }
1223 }
1224
1225 if(my_phy_caps & (PHY_STS_CAP_TXH_MASK))
1226 {
1227 // if(..we're allowing 100mbit half duplex...)
1228 {
1229 my_ad_caps |= PHY_ADV_TX_HDX;
1230 }
1231 }
1232
1233 if(my_phy_caps & (PHY_STS_CAP_TF_MASK))
1234 {
1235 // if(..we're allowing 10mbit full duplex...)
1236 {
1237 my_ad_caps |= PHY_ADV_10_FDX;
1238 }
1239 }
1240
1241 if(my_phy_caps & (PHY_STS_CAP_TH_MASK))
1242 {
1243 // if(..we're allowing 10mbit half duplex...)
1244 {
1245 my_ad_caps |= PHY_ADV_10_HDX;
1246 }
1247 }
1248
1249 (pmac->mdio0).ADV = my_ad_caps;
1250
1251 #if defined (MTIPPHYIRQ_AVAIL)
1252 #ifdef NS83865PHY
1253 (pmac->mdio0).reg15 =
1254 ( 0
1255 | NS883865_INTIE_ANEGDONE_MASK
1256 | NS883865_INTIE_LSCHG_MASK
1257 );
1258 #else
1259 #ifdef TDK78Q2120PHY
1260 (pmac->mdio0).reg11 =
1261 ( 0
1262 | TDK78_INTIE_ANEGDONE_MASK
1263 | TDK78_INTIE_LSCHG_MASK
1264 // | TDK78_INTIE_RXER_MASK
1265 );
1266 #else
1267 ......
1268 #endif // TDK78Q2120PHY
1269 #endif // NS83865PHY
1270 #endif // MTIPPHYIRQ_AVAIL
1271
1272 (pmac->mdio0).CONTROL =
1273 ( 0
1274 | PHY_CTL_ANEG_EN_MASK
1275 | PHY_CTL_ANEG_RST_MASK
1276 );
1277
1278 msecswaited = 0;
1279 while(((((pmac->mdio0).STATUS) & 0x00000020) == 0) &
1280 (msecswaited < 15000))
1281 {
1282 mdelay(100);
1283 msecswaited += 100;
1284 }
1285
1286 #if 1
1287 if((((pmac->mdio0).STATUS) & 0x00000020) != 0)
1288 {
1289 printk("mtip_phy_configure:%s, autoneg complete\n",
1290 dev->name);
1291 }
1292 else
1293 {
1294 printk("mtip_phy_configure:%s, autoneg started\n",
1295 dev->name);
1296 }
1297
1298 #ifdef NS83865PHY
1299 PRINTNS83PHYREGS(pmac,
1300 ((unsigned int) ((pmac->mdio0).reg14)),
1301 ((unsigned int) ((pmac->mdio0).reg15)),
1302 ((unsigned int) ((pmac->mdio0).reg11)));
1303 #else
1304 #ifdef TDK78Q2120PHY
1305 PRINTTDKPHYREGS(pmac,
1306 ((unsigned int) ((pmac->mdio0).reg11)),
1307 ((unsigned int) ((pmac->mdio0).reg12)));
1308 #else
1309 ......
1310 #endif
1311 #endif
1312 #endif
1313 }
1314
1315
1316 /*-----------------------------------------------------------
1317 | Enable Receive and Transmit, and Rx Interrupts
1318 |
1319 | Entry condition: Cpu interrupts ENabled.
1320 */
1321 static void mtip_enable( struct net_device *dev )
1322 {
1323 np_mtip_mac *pmac;
1324
1325 pmac = ((np_mtip_mac *) dev->base_addr);
1326
1327 PRINTK2("%s:mtip_enable\n", dev->name);
1328
1329 pmac->COMMAND_CONFIG =
1330 ( mmac_cc_TX_ENA_mask // enable transmit
1331 | mmac_cc_RX_ENA_mask // enable receive
1332 | mmac_cc_TX_ADDR_INS_mask // always overwrite source MAC addr
1333 );
1334
1335 pmac->IRQ_CONFIG = mmac_ic_EN_RX_FRAME_AVAILABLE_mask;
1336 // enable rx ready interrupt
1337
1338 #if defined (MTIPPHYIRQ_AVAIL)
1339 #if defined (na_mii_irq)
1340 (*(volatile unsigned long *)
1341 (((unsigned long *)
1342 ((((char *)
1343 (((int) (mtip_mii_control_port)) +
1344 0x0008))))))) =
1345 ((unsigned long) (0x0001));
1346 // Enable phy interrupt pass thru to na_mii_irq
1347 #endif // na_mii_irq
1348 #endif // MTIPPHYIRQ_AVAIL
1349 }
1350
1351
1352 /*-----------------------------------------------------------
1353 | Perform a software Reset.
1354 | Takes some time so we need to wait until it is finshed.
1355 |
1356 | Entry condition: Cpu interrupts ENabled.
1357 */
1358 static void mtip_mac_SwReset( struct net_device* dev )
1359 {
1360 //// struct mtip_local *lp = (struct mtip_local *)dev->priv;
1361 np_mtip_mac *pmac;
1362 int timeout;
1363
1364 pmac = ((np_mtip_mac *) dev->base_addr);
1365
1366 (pmac->mdio0).CONTROL = PHY_CTL_RST_MASK; // Reset the phy
1367
1368 // set reset and Gig-Speed bits to make sure we have an
1369 // incoming clock on tx side.
1370 // If there is a 10/100 PHY, we will still have a valid clock on
1371 // tx_clk no matter what setting we have here, but on a Gig phy the
1372 // MII clock may be missing.
1373
1374 pmac->COMMAND_CONFIG = mmac_cc_SW_RESET_mask | mmac_cc_ETH_SPEED_mask;
1375
1376 // wait for completion with fallback in case there is no PHY or it is
1377 // not connected and hence might not provide any clocks at all.
1378 timeout=0;
1379 while( (pmac->COMMAND_CONFIG & mmac_cc_SW_RESET_mask) != 0 &&
1380 timeout < 10000) timeout++;
1381
1382 pmac->COMMAND_CONFIG = 0;
1383
1384 // Cleanup pending "forgotten" DMAs
1385
1386 #if defined (MTIPDMA_AVAIL)
1387 ((np_dma *) (na_dma))->np_dmacontrol = 0;
1388 ((np_dma *) (na_dma))->np_dmastatus = 0;
1389 gMtipDmaState = Mtip_DmaState_Idle;
1390 #endif // MTIPDMA_AVAIL
1391
1392 // flush RX FIFO
1393
1394 /*
1395 ....?...tbd....?............
1396 ............................*/
1397 }
1398
1399
1400 /*-----------------------------------------------------------
1401 | soft reset the device
1402 |
1403 | Sets the Emac to its normal state.
1404 |
1405 | Entry condition: Cpu interrupts ENabled.
1406 */
1407 static void mtip_reset( struct net_device* dev )
1408 {
1409 np_mtip_mac *pmac;
1410
1411 pmac = ((np_mtip_mac *) dev->base_addr);
1412
1413 PRINTK2("%s:mtip_reset\n", dev->name);
1414
1415 mtip_mac_SwReset( dev );
1416
1417 // disable all IRQs
1418 //
1419 pmac->IRQ_CONFIG = 0;
1420 //
1421 #ifdef NS83865PHY
1422 (pmac->mdio0).reg15 = 0;
1423 #else
1424 #ifdef TDK78Q2120PHY
1425 (pmac->mdio0).reg11 = 0;
1426 #else
1427 ......
1428 #endif
1429 #endif
1430 //
1431 #if defined (MTIPPHYIRQ_AVAIL)
1432 #if defined (na_mii_irq)
1433 (*(volatile unsigned long *)
1434 (((unsigned long *)
1435 ((((char *)
1436 (((int) (mtip_mii_control_port)) +
1437 0x0008))))))) =
1438 ((unsigned long) (0x0000));
1439 // Disable phy interrupt pass thru to na_mii_irq
1440 #endif // na_mii_irq
1441 #endif // MTIPPHYIRQ_AVAIL
1442 }
1443
1444
1445 /*-----------------------------------------------------------
1446 */
1447 static void mtip_reset_config(struct net_device *dev)
1448 {
1449 np_mtip_mac *pmac;
1450
1451 pmac = ((np_mtip_mac *) dev->base_addr);
1452
1453 mtip_reset( dev );
1454
1455 pmac->MAC_0 =
1456 ((unsigned int)
1457 (*((unsigned long *)
1458 (&(((unsigned char *)
1459 (dev->dev_addr))[0])))));
1460 pmac->MAC_1 =
1461 ((unsigned int)
1462 (*((unsigned short *)
1463 (&(((unsigned char *)
1464 (dev->dev_addr))[4])))));
1465
1466 pmac->FRM_LENGTH = MTIP_MAC_MAX_FRAME_SIZE;
1467 pmac->PAUSE_QUANT = 0xff00;
1468
1469 pmac->RX_SECTION_EMPTY = 0; // Auto tx pause DISabled
1470 // pmac->RX_SECTION_EMPTY = 1900/4;
1471 // If RX FIFO fills to this level, PAUSE frame is sent
1472
1473 pmac->RX_SECTION_FULL = 0; // Store&forward (must be zero)
1474 pmac->TX_SECTION_EMPTY = (256-16)/4;
1475
1476 pmac->TX_SECTION_FULL = 0; // NO Early start tx
1477 // pmac->TX_SECTION_FULL = 128/4; // Early start tx: 128 bytes in FIFO
1478 // If TxFifo smaller than outbound packet, early start Tx
1479 // MUST be enabled.
1480 // Slow memory feeding TxFifo must NOT enable early start Tx.
1481
1482 pmac->RX_ALMOST_EMPTY = 8; //
1483 pmac->RX_ALMOST_FULL = 10; //
1484 pmac->TX_ALMOST_EMPTY = 8; //
1485 pmac->TX_ALMOST_FULL = 16; // Need at least 14 to cope
1486 // with Avalon/DMA latency
1487 return;
1488 }
1489
1490
1491 /*-----------------------------------------------------------
1492 | Driver entry point
1493 |
1494 | Entry condition: Cpu interrupts ENabled
1495 */
1496 static void mtip_timeout (struct net_device *dev)
1497 {
1498 // PRINTK3
1499 printk
1500 (
1501 // KERN_WARNING
1502 "%s:mtip_timeout\n",
1503 dev->name);
1504
1505 /* If we get here, some higher level has decided we are broken. */
1506
1507 #if 0
1508 ....FIXME:...preemption sensitive stuff to be accessed with
1509 .... cpu interrupts DISabled...
1510 ....If Dma state one of the TX states, must stop the
1511 .... Dma and change to idle state or handle gMtipDmaQ
1512 .... Mtip_DmaQ_RxFifo2Tmp/Mtip_DmaQ_RxFifo2Trash flag(s)
1513 ....Ensure Tx "done" interrupt is DISabled
1514 ....
1515 ....Empirical observation: we are toast no matter
1516 .... what we do [not]do...........
1517 if(gpMtipTxSkbInProg)
1518 {
1519 #if 0
1520 printk("%s:mtip_timeout, txSkb 0x%08X freed\n",
1521 dev->name,
1522 ((unsigned int) (gpMtipTxSkbInProg)));
1523 #endif
1524
1525 dev_kfree_skb_any (gpMtipTxSkbInProg);
1526 gpMtipTxSkbInProg = NULL;
1527
1528 #if defined (MTIPDMA_AVAIL)
1529 gMtipDmaQ &= (~(Mtip_DmaQ_TxSkb2Tmp));
1530 #endif
1531 }
1532
1533 mtip_reset_config( dev );
1534 mtip_enable( dev );
1535 mtip_phy_configure(dev);
1536
1537 mtip_phymac_synch(dev,
1538 0); // Caller = NOT Phy interrupt handler
1539
1540 netif_wake_queue(dev);
1541 #endif
1542 }
1543
1544
1545 /*-----------------------------------------------------------
1546 | Driver entry point
1547 |
1548 | Entry condition: Cpu interrupts ENabled.
1549 */
1550 static int mtip_hard_start_xmit( struct sk_buff * skb,
1551 struct net_device * dev )
1552 {
1553 unsigned long flags;
1554 struct mtip_local *lp = (struct mtip_local *)dev->priv;
1555 np_mtip_mac *pmac;
1556
1557 pmac = ((np_mtip_mac *) dev->base_addr);
1558
1559 dev->trans_start = jiffies;
1560 netif_stop_queue(dev);
1561
1562 PRINTK3("%s:mtip_hard_start_xmit\n", dev->name);
1563
1564 if ( gpMtipTxSkbInProg ) {
1565 lp->stats.tx_aborted_errors++;
1566 printk("mtip_hard_start_xmit:%s, - tx request while busy.\n",
1567 dev->name);
1568 return 1; // Tell caller to retry "later" (if/after someone
1569 // invokes netif_wake_queue(...))...
1570 }
1571
1572 gMtipTxSkbframelenbyts = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
1573
1574 if(gMtipTxSkbframelenbyts > MTIP_MAC_MAX_FRAME_SIZE)
1575 {
1576 printk("mtip_hard_start_xmit:%s, oversized %d byte packet.\n",
1577 dev->name,
1578 gMtipTxSkbframelenbyts);
1579 dev_kfree_skb (skb);
1580 netif_wake_queue(dev);
1581 return 0;
1582 }
1583
1584 gpMtipTxData = skb->data;
1585
1586 PRINTK3
1587 (
1588 "%s:Transmitting %d byte Packet 0x%08X\n",
1589 dev->name,
1590 gMtipTxSkbframelenbyts,
1591 ((unsigned long) (gpMtipTxData)));
1592 #if MTIP_DEBUG > 3
1593 print_packet( gpMtipTxData, gMtipTxSkbframelenbyts );
1594 #endif
1595
1596 gMtipTxSkbFifoNumL32s = ((gMtipTxSkbframelenbyts + 3) >> 2);
1597
1598 ++(lp->stats.tx_packets);
1599
1600 local_irq_save(flags);
1601
1602 gpMtipTxSkbInProg = skb;
1603
1604 #if defined (MTIPDMA_AVAIL)
1605
1606 if(gMtipDmaState == Mtip_DmaState_Idle)
1607 {
1608 gMtipDmaState = Mtip_DmaState_TxSkb2Tmp;
1609 local_irq_restore(flags);
1610
1611 dma_start_TxSkb2Tmp();
1612 }
1613 else
1614 {
1615 gMtipDmaQ |= Mtip_DmaQ_TxSkb2Tmp;
1616
1617 local_irq_restore(flags);
1618 }
1619 #else
1620 pmac->TX_CMD_STAT = (gMtipTxSkbframelenbyts |
1621 mmac_tcs_FRAME_COMPLETE_mask);
1622
1623 outsl(((unsigned long) PIO_port_txFIFO),
1624 gpMtipTxData,
1625 gMtipTxSkbFifoNumL32s );
1626 // If TxFifo smaller than outbound packet, early start Tx
1627 // must be enabled, else we'll overrun the TxFifo (which
1628 // "could" happen anyway with a "fast" cpu).
1629 // If early start Tx enabled, preemption must be disabled,
1630 // else we might underrun the TxFifo.
1631
1632 local_irq_restore(flags);
1633
1634 pmac->IRQ_CONFIG |= mmac_ic_EN_TX_FIFO_EMPTY_mask;
1635 // enable tx done interrupt
1636 #endif // MTIPDMA_AVAIL
1637
1638 return 0;
1639 }
1640
1641
1642 /*-----------------------------------------------------------
1643 | Driver entry point
1644 |
1645 | Entry condition: Cpu interrupts DISabled.
1646 */
1647 static irqreturn_t mtip_RxInterrupt(int irq,
1648 void *dev_id,
1649 struct pt_regs *regs)
1650 {
1651 unsigned int cmplnstatus;
1652 struct net_device *dev = dev_id;
1653 np_mtip_mac *pmac;
1654
1655 /* RxInterrupt condition self clears if/when RxFifo accessed. */
1656
1657 pmac = ((np_mtip_mac *) dev->base_addr);
1658
1659 ++gMtipRxints;
1660
1661 if(!((pmac->IRQ_CONFIG) & (mmac_ic_EN_RX_FRAME_AVAILABLE_mask)))
1662 {
1663 ++gMtipDisabledRxints;
1664 }
1665
1666 #if defined (MTIPDMA_AVAIL)
1667
1668 switch (gMtipDmaState)
1669 {
1670 case Mtip_DmaState_RxFifo2Tmp:
1671 case Mtip_DmaState_RxTmp2Skb:
1672 case Mtip_DmaState_RxFifo2Trash:
1673
1674 ++gMtipRxintsRxdmaBusy;
1675
1676 return IRQ_HANDLED;
1677 // ...This could be interesting...!
1678
1679 // case Mtip_DmaState_TxSkb2Tmp:
1680 // case Mtip_DmaState_TxTmp2Fifo:
1681 // case Mtip_DmaState_Idle:
1682 // default:
1683 }
1684
1685 if (gMtipDmaQ & (Mtip_DmaQ_TxSkb2Tmp |
1686 Mtip_DmaQ_RxFifo2Tmp |
1687 Mtip_DmaQ_RxFifo2Trash))
1688 {
1689 ++gMtipRxintsRxdmaQued;
1690
1691 return IRQ_HANDLED;
1692 // ...This could be interesting...!
1693
1694 }
1695 #endif // MTIPDMA_AVAIL
1696
1697 cmplnstatus = pmac->RX_CMD_STAT;
1698
1699 if(!( cmplnstatus & mmac_rcs_VALID_mask ))
1700 {
1701 ++gMtipUnexpRxints;
1702
1703 PRINTK3
1704 // printk
1705 (
1706 "mtip_RxInterrupt:%s, but RxStatus:0x%08X INvalid\n",
1707 dev->name,
1708 cmplnstatus);
1709
1710 /* ?...RxInterrupt condition...? */
1711 }
1712 else
1713 {
1714 mtip_NuRxReady(dev, cmplnstatus);
1715 }
1716
1717 return IRQ_HANDLED;
1718 }
1719
1720
1721 /*-----------------------------------------------------------
1722 | Driver entry point
1723 |
1724 | Entry condition: Cpu interrupts DISabled.
1725 */
1726 static irqreturn_t mtip_TxInterrupt(int irq,
1727 void *dev_id,
1728 struct pt_regs *regs)
1729 {
1730 unsigned long cmdcfg;
1731 struct net_device *dev = dev_id;
1732 struct mtip_local *lp;
1733 int old_txcmdstat;
1734 np_mtip_mac *pmac;
1735
1736 // Mtip's Tx fifo supposedly could alternatively
1737 // "flow control" the Dma adequately enough to let
1738 // us save this interrupt (if we don't need tx done
1739 // error tallying).
1740 //...Jun2004...NOT the case?...perhaps early tx start
1741 //... plays a part therein...?...
1742
1743 lp = (struct mtip_local *)dev->priv;
1744 pmac = ((np_mtip_mac *) dev->base_addr);
1745
1746 ++gMtipTxints;
1747
1748 if(!((pmac->IRQ_CONFIG) & (mmac_ic_EN_TX_FIFO_EMPTY_mask)))
1749 {
1750 ++gMtipDisabledTxints;
1751 }
1752
1753 cmdcfg = pmac->COMMAND_CONFIG;
1754 if((cmdcfg & mmac_cc_EXCESS_COL_mask) != 0)
1755 {
1756 ++(lp->stats.collisions);
1757 }
1758 if((cmdcfg & mmac_cc_LATE_COL_mask) != 0)
1759 {
1760 lp->stats.tx_window_errors++;
1761 // ifconfig displays as "carrier" errors.
1762
1763 PRINTK3
1764 // printk
1765 (
1766 // KERN_NOTICE
1767 "mtip_TxInterrupt:%s, Late collision on last xmit.\n",
1768 dev->name);
1769 }
1770
1771 old_txcmdstat = pmac->TX_CMD_STAT;
1772
1773 if(gpMtipTxSkbInProg)
1774 {
1775 if(!(old_txcmdstat & mmac_tcs_FRAME_COMPLETE_mask))
1776 {
1777 dev_kfree_skb_any (gpMtipTxSkbInProg);
1778 gpMtipTxSkbInProg = NULL;
1779 }
1780 else
1781 {
1782 ++gMtipTxintsIncomplete;
1783
1784 return IRQ_HANDLED;
1785 // ...This could be interesting...!
1786 }
1787 }
1788 else
1789 {
1790 ++gMtipUnexpTxints;
1791 }
1792
1793 pmac->IRQ_CONFIG &= (~(mmac_ic_EN_TX_FIFO_EMPTY_mask));
1794
1795 netif_wake_queue(dev);
1796
1797 return IRQ_HANDLED;
1798 }
1799
1800
1801 #if defined (MTIPPHYIRQ_AVAIL)
1802 /*-----------------------------------------------------------
1803 | Driver entry point
1804 |
1805 | Entry condition: Cpu interrupts DISabled.
1806 */
1807 static irqreturn_t mtip_PhyInterrupt(int irq,
1808 void *dev_id,
1809 struct pt_regs *regs)
1810 {
1811 struct net_device *dev = dev_id;
1812 np_mtip_mac *pmac;
1813 #ifdef NS83865PHY
1814 unsigned int nsIntstsReg20;
1815 unsigned int nsIntieReg21;
1816 unsigned int nsLnkstsReg17;
1817 #else
1818 #ifdef TDK78Q2120PHY
1819 unsigned int tdkDiagReg18;
1820 unsigned int tdkintCtlStsReg17;
1821 #endif
1822 #endif
1823
1824 pmac = ((np_mtip_mac *) dev->base_addr);
1825
1826 #if defined(ANNOUNCEPHY)
1827 printk
1828 (
1829 "mtip_PhyInterrupt:%s\n",
1830 dev->name);
1831 #endif
1832
1833 #ifdef NS83865PHY
1834 nsIntstsReg20 = (pmac->mdio0).reg14;
1835 nsIntieReg21 = (pmac->mdio0).reg15;
1836 nsLnkstsReg17 = (pmac->mdio0).reg11;
1837
1838 #if 0
1839 PRINTNS83PHYREGS(pmac,
1840 nsIntstsReg20,
1841 nsIntieReg21,
1842 nsLnkstsReg17);
1843 #endif
1844
1845 (pmac->mdio0).reg17 = nsIntstsReg20;
1846 // Ack (all) interrupt condition(s)
1847 #else
1848 #ifdef TDK78Q2120PHY
1849 tdkintCtlStsReg17 = (pmac->mdio0).reg11;
1850 // Read TDK 78Q2120 interrupt control/status register
1851 // Also acks the interrupt condition(s)
1852
1853 tdkDiagReg18 = (pmac->mdio0).reg12;
1854 // Read TDK 78Q2120 diagnostic register
1855 // Also clears auto-negotiation failed bit
1856
1857 #if 0
1858 PRINTTDKPHYREGS(pmac, tdkintCtlStsReg17, tdkDiagReg18);
1859 #endif
1860 #else
1861 ......
1862 #endif
1863 #endif
1864
1865 mtip_phymac_synch((struct net_device *) dev_id,
1866 1); // Caller = Phy interrupt handler
1867
1868 return IRQ_HANDLED;
1869 }
1870 #endif // MTIPPHYIRQ_AVAIL
1871
1872
1873 /*-----------------------------------------------------------
1874 | Driver entry point (eg: ifconfig ethX up).
1875 | (eg: ifattach ...)
1876 |
1877 | Open and Initialize the board
1878 |
1879 | Set up everything, reset the card, etc ..
1880 |
1881 | Entry condition: Cpu interrupts ENabled.
1882 */
1883 static int mtip_open(struct net_device *dev)
1884 {
1885 np_mtip_mac *pmac;
1886
1887 pmac = ((np_mtip_mac *) dev->base_addr);
1888
1889 PRINTK2("%s:mtip_open\n", dev->name);
1890
1891 memset(dev->priv, 0, sizeof(struct mtip_local));
1892
1893
1894 #ifdef CONFIG_SYSCTL
1895 // Set default parameters (files)
1896 /*
1897 ....tbd.............
1898 .....................*/
1899 #endif
1900
1901 mtip_reset_config( dev );
1902 mtip_enable( dev );
1903 mtip_phy_configure(dev);
1904
1905 mtip_phymac_synch(dev,
1906 0); // Caller = NOT Phy interrupt handler
1907
1908 #ifdef CONFIG_SYSCTL
1909 mtip_sysctl_register(dev);
1910 #endif /* CONFIG_SYSCTL */
1911
1912 netif_start_queue(dev);
1913
1914 return 0;
1915 }
1916
1917
1918 /*-----------------------------------------------------------
1919 | close down the Emac
1920 |
1921 | put the device in an inactive state
1922 |
1923 */
1924 static void mtip_shutdown( struct net_device *dev )
1925 {
1926 PRINTK2("%s:mtip_shutdown\n", dev->name);
1927
1928 /*
1929 ....tbd.............
1930 ...........................*/
1931 }
1932
1933
1934 /*-----------------------------------------------------------
1935 | Driver entry point (eg: ifconfig ethX down).
1936 |
1937 | Clean up everything from the open routine
1938 */
1939 static int mtip_close(struct net_device *dev)
1940 {
1941 PRINTK2("%s:mtip_close\n", dev->name);
1942
1943 netif_stop_queue(dev);
1944
1945 if(gpMtipTxSkbInProg)
1946 {
1947 dev_kfree_skb_any (gpMtipTxSkbInProg);
1948 gpMtipTxSkbInProg = NULL;
1949
1950 #if defined (MTIPDMA_AVAIL)
1951 gMtipDmaQ &= (~(Mtip_DmaQ_TxSkb2Tmp));
1952 #endif
1953 }
1954
1955 #if defined (MTIPDMA_AVAIL)
1956 gMtipDmaQ = 0;
1957 gMtipDmaState = Mtip_DmaState_Idle;
1958 #endif // MTIPDMA_AVAIL
1959
1960 #ifdef CONFIG_SYSCTL
1961 mtip_sysctl_unregister(dev);
1962 #endif /* CONFIG_SYSCTL */
1963
1964 /* clear everything */
1965 mtip_shutdown( dev );
1966
1967 /* Update the statistics here. */
1968
1969 return 0;
1970 }
1971
1972
1973 /*-----------------------------------------------------------
1974 | Driver entry point (re unregister_netdev()).
1975 |
1976 | Cleaning up before driver finally unregistered and discarded.
1977 |
1978 | Input parameters:
1979 | dev, pointer to the device structure
1980 |
1981 | Output:
1982 | None.
1983 |
1984 ---------------------------------------------------------------------------
1985 */
1986 void mtip_destructor(struct net_device *dev)
1987 {
1988 PRINTK2("%s:mtip_destructor\n", dev->name);
1989 }
1990
1991
1992 /*-----------------------------------------------------------
1993 | Driver entry point.
1994 |
1995 | Get the current statistics.
1996 |
1997 | Allows proc file system to query the driver's statistics.
1998 |
1999 | May be called with the card open or closed.
2000 |
2001 | Entry condition: Cpu interrupts ENabled.
2002 */
2003 static struct net_device_stats* mtip_query_statistics(struct net_device *dev)
2004 {
2005 struct mtip_local *lp = (struct mtip_local *)dev->priv;
2006
2007 PRINTK2("%s:mtip_query_statistics\n", dev->name);
2008
2009 return &lp->stats;
2010 }
2011
2012
2013 /*-----------------------------------------------------------
2014 | Clear the multicast table to disable multicast reception.
2015 |
2016 | Entry condition: Cpu interrupts ENabled.
2017 */
2018 static void mtip_mac_clearMulticast(struct net_device *dev)
2019 {
2020 int i;
2021 np_mtip_mac *pmac;
2022
2023 pmac = ((np_mtip_mac *) dev->base_addr);
2024
2025 for(i=0; i < 64; i++ )
2026 {
2027 (pmac->hashtable)[i] = 0;
2028 }
2029 }
2030
2031
2032 /*-----------------------------------------------------------
2033 | Fill the multicast table to enable reception of all multicast frames.
2034 |
2035 | Entry condition: Cpu interrupts ENabled.
2036 */
2037 static void mtip_mac_promiscuousMulticast(struct net_device *dev)
2038 {
2039 int i;
2040 np_mtip_mac *pmac;
2041
2042 pmac = ((np_mtip_mac *) dev->base_addr);
2043
2044 for(i=0; i < 64; i++ )
2045 {
2046 (pmac->hashtable)[i] = 1;
2047 }
2048 }
2049
2050
2051 /*-----------------------------------------------------------
2052 | Reprogram multicast mac addresses into hardware multicast table
2053 |
2054 | Caller has already cleared existing hash entries as appropriate
2055 |
2056 | Entry condition: Cpu interrupts ENabled.
2057 */
2058 static void mtip_setmulticast( struct net_device *dev,
2059 int count,
2060 struct dev_mc_list *addrs )
2061 {
2062 int a;
2063 int bit;
2064 int bitidx;
2065 int hash;
2066 int i;
2067 char ch;
2068 struct dev_mc_list *cur_addr;
2069 np_mtip_mac *pmac;
2070
2071 pmac = ((np_mtip_mac *) dev->base_addr);
2072
2073 PRINTK2
2074 (
2075 "mtip_setmulticast:%s\n",
2076 dev->name);
2077
2078 cur_addr = addrs;
2079
2080 for ( i = 0; i < count ; i ++, cur_addr = cur_addr->next )
2081 {
2082 /* do we have a pointer here? */
2083 if ( !cur_addr )
2084 break;
2085
2086 /* make sure this is a multicast address */
2087 if ( !( *cur_addr->dmi_addr & 1 ) )
2088 continue;
2089
2090 hash = 0; // the hash value
2091
2092 for(a=5; a >= 0; a--)
2093 {
2094 // loop through all 6 bytes of this mac address
2095
2096 bit = 0; // the bit calculated from the byte
2097 ch = (cur_addr->dmi_addr)[a];
2098
2099 for(bitidx=0;bitidx < 8;bitidx++)
2100 {
2101 bit ^= (int)((ch >> bitidx) & 0x01);
2102 }
2103
2104 hash = (hash << 1) | bit;
2105 }
2106
2107 #if (MTIP_DEBUG > 2 )
2108 // printk(" ");
2109 printk("mtip_setmulticast: ");
2110 for(a=0; a < 6; a++)
2111 {
2112 ch = (cur_addr->dmi_addr)[a];
2113
2114 printk(" %02X",ch);
2115 }
2116 printk(" hash(%d)\n",hash);
2117 #endif
2118
2119 (pmac->hashtable)[ hash ] = 1;
2120 }
2121 }
2122
2123
2124 /*-----------------------------------------------------------
2125 | Driver entry point.
2126 |
2127 | This routine will, depending on the values passed to it,
2128 | either make it accept multicast packets, go into
2129 | promiscuous mode ( for TCPDUMP and cousins ) or accept
2130 | a select set of multicast packets
2131 |
2132 | Entry condition: Cpu interrupts ENabled.
2133 */
2134 static void mtip_set_multicast_list(struct net_device *dev)
2135 {
2136 np_mtip_mac *pmac;
2137
2138 pmac = ((np_mtip_mac *) dev->base_addr);
2139
2140 PRINTK2
2141 (
2142 "%s:mtip_set_multicast_list\n",
2143 dev->name);
2144
2145 if ( dev->flags & IFF_PROMISC )
2146 {
2147 PRINTK2
2148 // printk
2149 (
2150 "%s:mtip_set_multicast_list:RCR_PRMS\n", dev->name);
2151
2152 mtip_mac_setPromiscuous(pmac);
2153 }
2154 else
2155 {
2156 PRINTK2
2157 // printk
2158 (
2159 "%s:mtip_set_multicast_list:~RCR_PRMS\n", dev->name);
2160
2161 mtip_mac_clearPromiscuous(pmac);
2162 }
2163
2164 if (dev->flags & IFF_ALLMULTI)
2165 {
2166 PRINTK2
2167 // printk
2168 (
2169 "%s:mtip_set_multicast_list:RCR_ALMUL\n", dev->name);
2170
2171 mtip_mac_promiscuousMulticast(dev);
2172 }
2173 else
2174 {
2175 PRINTK2
2176 (
2177 "%s:mtip_set_multicast_list:~RCR_ALMUL\n", dev->name);
2178
2179 mtip_mac_clearMulticast(dev); // Clear any existing hash entries
2180
2181 if(dev->mc_count)
2182 {
2183 mtip_setmulticast( dev,
2184 dev->mc_count,
2185 dev->mc_list );
2186 }
2187 }
2188 }
2189
2190
2191 /*-----------------------------------------------------------
2192 | Entry condition: Cpu interrupts ENabled
2193 | (in SPITE of claims disabled...).
2194 */
2195 static int __init mtip_probe(struct net_device *dev, unsigned int ioaddr )
2196 {
2197 int i;
2198 np_mtip_mac *pmac;
2199 int retval;
2200 static unsigned version_printed = 0;
2201
2202
2203 pmac = ((np_mtip_mac *) ioaddr);
2204
2205 PRINTK2("%s:mtip_probe\n", dev->name);
2206
2207 SET_MODULE_OWNER (dev);
2208
2209 #if 1
2210 #ifdef CONFIG_EXCALIBUR
2211 printk("mtip_probe:%s, %d Khz Nios (%s) (%s)\n",
2212 dev->name,
2213 nasys_clock_freq_1000,
2214 PHYTYPE,
2215 IOTYPE);
2216 #endif
2217 #endif
2218
2219 /* Grab the region so that no one else tries to probe our ioports. */
2220 if (!request_region(ioaddr,
2221 MTIP1000_IO_EXTENT,
2222 dev->name)) return -EBUSY;
2223
2224 if (version_printed++ == 0) printk("%s", version);
2225
2226 dev->base_addr = ioaddr;
2227
2228 #ifdef NS83865PHY
2229 {
2230 int oldmdioaddr0;
2231 int phyaddr = -1;
2232
2233 // Empirical observation: expect NS83865PHY's phy address = 2
2234
2235 oldmdioaddr0 = pmac->MDIO_ADDR0;
2236
2237 for (i = 0; i <= 31; i++)
2238 {
2239 pmac->MDIO_ADDR0 = i;
2240
2241 if(((pmac->mdio0).PHY_ID1) == 0x2000)
2242 {
2243 phyaddr = i;
2244
2245 break;
2246 }
2247 }
2248
2249 if(phyaddr >= 0)
2250 {
2251 pmac->MDIO_ADDR0 = phyaddr;
2252 }
2253 else
2254 {
2255 pmac->MDIO_ADDR0 = oldmdioaddr0;
2256
2257 printk("mtip_probe:%s, (%s) phy not found"
2258 ", defaulting to addr:0x%02X\n",
2259 dev->name,
2260 PHYTYPE,
2261 pmac->MDIO_ADDR0);
2262 }
2263 }
2264 #else
2265 #ifdef TDK78Q2120PHY
2266 // TDK78Q2120PHY's respond to the "broadcast" phy address 0,
2267 // so leave pmac->MDIO_ADDR0 at its default value 0
2268 #else
2269 ......
2270 #endif
2271 #endif // NS83865PHY
2272
2273 mtip_reset( dev );
2274
2275 printk("mtip_probe:%s, REV=0x%08x, (%s) Phyaddr:0x%02X\n",
2276 dev->name,
2277 pmac->REV,
2278 PHYTYPE,
2279 pmac->MDIO_ADDR0);
2280
2281 #if 0
2282 #ifdef NS83865PHY
2283 PRINTNS83PHYREGS(pmac,
2284 ((unsigned int) ((pmac->mdio0).reg14)),
2285 ((unsigned int) ((pmac->mdio0).reg15)),
2286 ((unsigned int) ((pmac->mdio0).reg11)));
2287 #else
2288 #ifdef TDK78Q2120PHY
2289 PRINTTDKPHYREGS(pmac,
2290 ((unsigned int) ((pmac->mdio0).reg11)),
2291 ((unsigned int) ((pmac->mdio0).reg12)));
2292 #else
2293 ......
2294 #endif
2295 #endif
2296 #endif
2297
2298 #ifdef CONFIG_EXCALIBUR
2299 {
2300 extern unsigned char *excalibur_enet_hwaddr;
2301
2302 memcpy(dev->dev_addr, excalibur_enet_hwaddr, 6);
2303 }
2304 #else
2305 .........
2306 #endif
2307
2308 /*
2309 . Print the Ethernet address
2310 */
2311 printk(" ADDR: ");
2312 for (i = 0; i < 5; i++)
2313 printk("%2.2x:", dev->dev_addr[i] );
2314 printk("%2.2x \n", dev->dev_addr[5] );
2315
2316 /* set the private data to zero by default */
2317 memset(dev->priv, 0, sizeof(struct mtip_local));
2318
2319 /* Fill in the fields of the device structure with ethernet values. */
2320 ether_setup(dev);
2321
2322 /* Grab the RxIRQ */
2323 retval = request_irq(dev->irq,
2324 mtip_RxInterrupt,
2325 0,
2326 dev->name,
2327 dev);
2328 if (retval) {
2329 printk("mtip_probe:%s unable to hook RxIRQ %d (retval=%d).\n",
2330 dev->name,
2331 dev->irq,
2332 retval);
2333
2334 goto frepriv_err_out;
2335 }
2336
2337 retval = request_irq(na_mtip_mac_txFIFO_irq,
2338 mtip_TxInterrupt,
2339 0,
2340 dev->name,
2341 dev);
2342 if (retval) {
2343 printk("mtip_probe:%s unable to hook TxIRQ %d (retval=%d).\n",
2344 dev->name,
2345 na_mtip_mac_txFIFO_irq,
2346 retval);
2347
2348 goto freRxIrq_err_out;
2349 }
2350
2351 #if defined (MTIPPHYIRQ_AVAIL)
2352 /* Grab the PhyIRQ */
2353 retval = request_irq(na_mii_irq_irq,
2354 mtip_PhyInterrupt,
2355 0,
2356 dev->name,
2357 dev);
2358 if (retval)
2359 {
2360 printk("mtip_probe:%s unable to hook PhyIRQ %d (retval=%d).\n",
2361 dev->name,
2362 na_mii_irq_irq,
2363 retval);
2364
2365 goto freTxIrq_err_out;
2366 }
2367 #endif // MTIPPHYIRQ_AVAIL
2368
2369 gMtipDisabledRxints = 0;
2370 gMtipDisabledTxints = 0;
2371 gMtipDmaints = 0;
2372 gMtipDmaintsBusy = 0;
2373 gMtipDmaintsBusyDone = 0;
2374 gMtipDmaintsNoDone = 0;
2375 gMtipRxints = 0;
2376 gMtipRxintsRxdmaBusy = 0;
2377 gMtipRxintsRxdmaQued = 0;
2378 gMtipRxNoints = 0;
2379 gMtipTxints = 0;
2380 gMtipTxintsIncomplete = 0;
2381 gMtipUnexpDmaints = 0;
2382 gMtipUnexpRxints = 0;
2383 gMtipUnexpTxints = 0;
2384 gpMtipTxSkbInProg = NULL;
2385
2386 #if defined (MTIPDMA_AVAIL)
2387 gMtipDmaQ = 0;
2388 gMtipDmaState = Mtip_DmaState_Idle;
2389
2390 /* Grab the DmaIRQ */
2391 retval = request_irq(na_dma_irq,
2392 mtip_DmaInterrupt,
2393 0,
2394 dev->name,
2395 dev);
2396 if (retval) {
2397 printk("mtip_probe:%s unable to hook DmaIRQ %d (retval=%d).\n",
2398 dev->name,
2399 na_dma_irq,
2400 retval);
2401
2402 goto frePhyIrq_err_out;
2403 }
2404 #endif // MTIPDMA_AVAIL
2405
2406 // see mtip_phymac_synch for full/half duplex coordination
2407
2408 dev->open = mtip_open;
2409 dev->stop = mtip_close;
2410 dev->hard_start_xmit = mtip_hard_start_xmit;
2411 dev->tx_timeout = mtip_timeout;
2412 dev->get_stats = mtip_query_statistics;
2413 #ifdef HAVE_MULTICAST
2414 dev->set_multicast_list = &mtip_set_multicast_list;
2415 #endif
2416
2417 return 0;
2418
2419 #if defined (MTIPPHYIRQ_AVAIL)
2420 #if defined (MTIPDMA_AVAIL)
2421 frePhyIrq_err_out:
2422 #endif // MTIPDMA_AVAIL
2423
2424 free_irq(na_mii_irq_irq, dev);
2425
2426 freTxIrq_err_out:
2427 #endif // MTIPPHYIRQ_AVAIL
2428
2429 free_irq(na_mtip_mac_txFIFO_irq,
2430 dev);
2431
2432 freRxIrq_err_out:
2433
2434 free_irq(na_mtip_mac_rxFIFO_irq,
2435 dev);
2436
2437 frepriv_err_out:
2438
2439 kfree (dev->priv);
2440 dev->priv = NULL;
2441
2442 //err_out:
2443 release_region (ioaddr, MTIP1000_IO_EXTENT);
2444 return retval;
2445 }
2446
2447
2448 /*-----------------------------------------------------------
2449 | Driver entry point (called by ethif_probe2()).
2450 |
2451 | Return: 0 success.
2452 |
2453 | Entry condition: Cpu interrupts ENabled
2454 | (in SPITE of claims disabled...).
2455 */
2456 struct net_device * __init mtip1000_init(int unit)
2457 {
2458 struct net_device *dev = alloc_etherdev(sizeof(struct mtip_local));
2459 int err = 0;
2460 int i;
2461
2462 if (!dev) return ERR_PTR(-ENODEV);
2463
2464 sprintf(dev->name, "eth%d", unit);
2465 netdev_boot_setup_check(dev);
2466
2467 PRINTK2("%s:mtip1000_init\n", dev->name);
2468
2469 for (i = 0; mtip_portlist[i]; i++) {
2470 dev->irq = mtip_irqlist[i];
2471
2472 if (mtip_probe(dev, mtip_portlist[i]) == 0) break;
2473 }
2474
2475 if (!mtip_portlist[i]) err = -ENODEV;
2476 if (err) goto out;
2477
2478 err = register_netdev(dev);
2479 if (err) goto out;
2480 return dev;
2481 out:
2482 free_netdev(dev);
2483 // printk(KERN_WARNING "mtip1000: no emac unit %d detected.\n",unit);
2484 return ERR_PTR(err);
2485 }
MOXA 2.6.19 from UC-7110-LX-BOOTLOADER-1.9_VERSION-4.2.tgz