2 * include/asm-arm/arch-s3c24a0/ide.h
5 * Originally based upon linux/include/asm-arm/arch-sa1100/ide.h
9 * 2004/06/10 <heechul.yun@samsung.com> SPJ CPLD IDE support
10 * 2004/06/13 <heechul.yun@samsung.com> CPLD IDE and USB csupport for SPJ
15 #include <asm/hardware.h>
16 #include <asm/mach-types.h>
26 #define CPLD_IDE_DEBUG // hcyun
29 * Set up a hw structure for a specified data port, control port and IRQ.
30 * This should follow whatever the default interface uses.
32 static __inline__
void
33 ide_init_hwif_ports(hw_regs_t
*hw
, int data_port
, int ctrl_port
, int *irq
)
37 memset(hw
, 0, sizeof(*hw
));
39 reg
= (ide_ioreg_t
)data_port
;
42 hw
->io_ports
[IDE_DATA_OFFSET
] = reg
+ 0;
43 hw
->io_ports
[IDE_ERROR_OFFSET
] = reg
+ (1 << 3);
44 hw
->io_ports
[IDE_NSECTOR_OFFSET
] = reg
+ (2 << 3);
45 hw
->io_ports
[IDE_SECTOR_OFFSET
] = reg
+ (3 << 3);
46 hw
->io_ports
[IDE_LCYL_OFFSET
] = reg
+ (4 << 3);
47 hw
->io_ports
[IDE_HCYL_OFFSET
] = reg
+ (5 << 3);
48 hw
->io_ports
[IDE_SELECT_OFFSET
] = reg
+ (6 << 3);
49 hw
->io_ports
[IDE_STATUS_OFFSET
] = reg
+ (7 << 3);
51 hw
->io_ports
[IDE_CONTROL_OFFSET
] = (ide_ioreg_t
) ctrl_port
;
59 * CPLD IDE reset. to reset first assert 0 and then assert 1
62 static __inline__
void ide_set_reset(int on
)
64 volatile unsigned char *usb_reset
= (unsigned char *)(SMDK_CPLD_USB_VIO
+0x00800000);
65 volatile unsigned char *ide_reset
= (unsigned char *)(SMDK_CPLD_IDE_VIO
+0x00800000);
68 /* turn CPLD to IDE mode */
91 * Register the standard ports for this architecture with the IDE driver.
93 static __inline__
void
94 ide_init_default_hwifs(void)
97 A7 A6 A5 A4 A3 <-- CPLD address line used
99 CE2 CE1 A2 A1 A0 IORD IOWR
100 ---------------------------------
105 0 1 1 1 0 control port
107 data port = SMDK_CPLD_IDE_VIO + 0x80
108 control port = SMDK_CPLD_IDE_VIO + 0x70
112 /* Nothing to declare... */
118 ide_init_hwif_ports(&hw
, SMDK_CPLD_IDE_VIO
+ 0x80, SMDK_CPLD_IDE_VIO
+ 0x70, NULL
);
120 hw
.irq
= SMDK_CPLD_IDE_IRQ
;
122 ide_register_hw(&hw
, NULL
);
125 #ifdef CPLD_IDE_DEBUG
126 printk("SMDK24A0 : IDE initialize - hcyun \n");
127 printk("!!FIXME!! IDE and cs8900 are controlled by SROM bank1 and need different timing and bus width\n");
130 bank1_set_state(B1_IDE_PIO4
);
139 mdelay(500); // wait 250ms see ATA spec
141 printk("riging edge interrupt\n");
142 ret
= set_external_irq(SMDK_CPLD_IDE_IRQ
, EINT_RISING_EDGE
, EINT_PULLUP_EN
);
145 printk("ERROR: irq set failed\n");