include/asm-arm/arch-s3c24a0/smdk.h

   1 /*
   2  * include/asm-arm/arch-s3c24a0/smdk.h
   3  *
   4  * Changes
   5  *
   6  * 2004/06/10 <heechul.yun@samsung.com>  CPLD IDE code added
   7  *
   8  */
   9
  10 #ifndef _SMDK24A0_H_
  11 #define _SMDK24A0_H_
  12
  13 /* Externl clock frequency used by CPU */
  14 #define FIN     12000000
  15
  16 /*
  17  * on SMDK24A0,
  18  * there are so many cross-interference jumpers (h/w switch).
  19  */
  20
  21 /*
  22  * This is for SPJ Board - hcyun
  23
  24  XgpIO0  <------ EINT0
  25  XgpIO1  <------ EINT1
  26  XgpIO2  <------ SD_INT
  27  XgpIO3  ------> XGPIO_nSS              <-- not used
  28  XgpIO4  ------> LED0
  29  XgpIO5  ------> LED1
  30  XgpIO6  ------> LED2
  31  XgpIO7  ------> LED3
  32  XgpIO8  <----->
  33  XgpIO9  ------>
  34  XgpIO10 <------ EINT10                 <-- not used
  35  XgpIO11 <------ EINT11                 <-- not used
  36  XgpIO12 <------ MODEM_INT              <-- not used
  37  XgpIO13 <------ ETHER_INT
  38  XgpIO14 <------ SMC_INT                <-- not used
  39  XgpIO15 ------> SMC_WP                 <-- l3-bit-elfin.c I2C??? l3 bus
  40  XgpIO16 <------ SPJ IDE                <-- IDE & l3-bit-elfin.c I2C??? l3 bus
  41  XgpIO17 <------ SPJ USB                <-- USB
  42  XgpIO18 <-----> KP_ROW0
  43  XgpIO19 <-----> KP_ROW1                <-- s3c24a0_keyif.c
  44  XgpIO20 <-----> KP_ROW2                <-- s3c24a0_keyif.c
  45  XgpIO21 <-----> KP_ROW3
  46  XgpIO22 <-----> KP_ROW4
  47  XgpIO23 <-----> KP_COL0
  48  XgpIO24 <-----> KP_COL1
  49  XgpIO25 <-----> KP_COL2
  50  XgpIO26 <-----> KP_COL3
  51  XgpIO27 <-----> KP_COL4
  52  XgpIO28 <----->
  53  XgpIO29 <----->
  54  XgpIO30 <----->
  55  XgpIO31 <----->
  56
  57  *
  58  */
  59
  60 #define SMDK_SMC_WP      GPIO_15    /* O   : SMC Write-Protect */
  61
  62 #define SMDK_CAM_SCL     GPIO_9     /* O   : Camera I2C/SCCB clock */
  63 #define SMDK_CAM_SDA     GPIO_8     /* I/O : Camera I2C/SCCB data */
  64 #define SMDK_LED7        GPIO_7     /* O   : LED3, Low-Active */
  65 #define SMDK_LED6        GPIO_6     /* O   : LED2, LOw-Active */
  66 #define SMDK_LED5        GPIO_5     /* O   : LED1, LOw-Active */
  67 #define SMDK_LED4        GPIO_4     /* O   : LED0, Low-Active */
  68
  69 /* GPIO buttons. EINT 0,1,10,11 */
  70 #define SMDK_EINT0_IRQ  IRQ_EINT0
  71 #define SMDK_EINT1_IRQ  IRQ_EINT1
  72 #define SMDK_EINT10_IRQ IRQ_EINT10
  73 #define SMDK_EINT11_IRQ IRQ_EINT11
  74 #define SMDK_EINT0_GPIO GPIO_0
  75 #define SMDK_EINT1_GPIO GPIO_1
  76 #define SMDK_EINT10_GPIO GPIO_10
  77 #define SMDK_EINT11_GPIO GPIO_11
  78
  79 #ifdef CONFIG_MMU
  80   #define SROM_BANK1_PBASE                        0x04000000
  81   #define SROM_BANK1_VBASE                        0xf0000000
  82 #else /* UCLINUX */
  83   #define SROM_BANK1_PBASE                        0x04000000
  84   #define SROM_BANK1_VBASE                        0x04000000
  85 #endif /* CONFIG_MMU */
  86
  87 #ifndef __ASSEMBLY__
  88 /*
  89  * BANK1 control for cs89x0, IDE, USB2.0 - hcyun
  90  */
  91 typedef struct {
  92         unsigned long bw;
  93         unsigned long bc;
  94 } bank_param_t;
  95
  96 #define B1_STATE_NONE -1
  97 #define B1_IDE_PIO0 0
  98 #define B1_IDE_PIO4 1
  99 #define B1_CS89x0       2
 100 #define B1_USB2         3
 101 #define B1_STATE_LIMIT 3
 102
 103 #endif
 104
 105
 106 /* CPLD IDE - hcyun
 107  * 0x07000000   [0] : IDE reset
 108  *                              [1] : 0 - USB, 1 - IDE
 109  */
 110
 111 #define SMDK_CPLD_IDE_IRQ_GPIO          GPIO_4
 112 #define SMDK_CPLD_IDE_IRQ               IRQ_EINT4
 113 #define SMDK_CPLD_IDE_VIO               (SROM_BANK1_VBASE + 0x03000000) // 0xf3000000
 114 #define SMDK_CPLD_IDE_PIO               (SROM_BANK1_PBASE + 0x03000000) // 0x04000000
 115
 116
 117 /* CPLD USB - hcyun
 118  * 0x06000000   [0] : USB reset
 119  */
 120 /*seo 20040616 */
 121 #define SMDK_CPLD_USB_IRQ_GPIO          GPIO_5
 122 #define SMDK_CPLD_USB_IRQ               IRQ_EINT5
 123 #define SMDK_CPLD_USB_VIO               (SROM_BANK1_VBASE + 0x02000000)
 124 #define SMDK_CPLD_USB_PIO               (SROM_BANK1_PBASE + 0x02000000)
 125
 126
 127 /* CS8900A */
 128 #define SMDK_CS8900_IRQ_GPIO   GPIO_13
 129 #define SMDK_CS8900_IRQ        IRQ_EINT13
 130 #define SMDK_CS8900_VIO        SROM_BANK1_VBASE
 131 #define SMDK_CS8900_PIO        (SROM_BANK1_PBASE | (1<<24))
 132
 133 /* IRDA */
 134 #define SMDK_IRDA_SDBW          (GPIO_MODE_IrDA_SDBW | GPIO_16 | GPIO_PULLUP_DIS)
 135 #define SMDK_IRDA_TXD           (GPIO_MODE_IrDA_TXD | GPIO_17 | GPIO_PULLUP_DIS)
 136 #define SMDK_IRDA_RXD           (GPIO_MODE_IrDA_RXD | GPIO_18 | GPIO_PULLUP_DIS)
 137
 138 /* UART */
 139 #define SMDK_UART1_nCTS         (GPIO_MODE_UART | GPIO_28 | GPIO_PULLUP_DIS)
 140 #define SMDK_UART1_nRTS         (GPIO_MODE_UART | GPIO_29 | GPIO_PULLUP_DIS)
 141 #define SMDK_UART1_TXD          (GPIO_MODE_UART | GPIO_30 | GPIO_PULLUP_DIS)
 142 #define SMDK_UART1_RXD          (GPIO_MODE_UART | GPIO_31 | GPIO_PULLUP_DIS)
 143
 144 #endif /* _SMDK24A0_H_ */