| blob | 61b3a336e28d47e25ce5738b63d0e9fdf8b8beb9 |
1 /*
2 * linux/arch/arm/boot/compressed/head.S
3 *
4 * Copyright (C) 1996-2002 Russell King
5 * Copyright (C) 2004 Hyok S. Choi (MPU support)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/linkage.h>
13 /*
14 * Debugging stuff
15 *
16 * Note that these macros must not contain any code which is not
17 * 100% relocatable. Any attempt to do so will result in a crash.
18 * Please select one of the following when turning on debugging.
19 */
20 #ifdef DEBUG
22 #if defined(CONFIG_DEBUG_ICEDCC)
24 #ifdef CONFIG_CPU_V6
25 .macro loadsp, rb
26 .endm
27 .macro writeb, ch, rb
28 mcr p14, 0, \ch, c0, c5, 0
29 .endm
30 #elif defined(CONFIG_CPU_XSCALE)
31 .macro loadsp, rb
32 .endm
33 .macro writeb, ch, rb
34 mcr p14, 0, \ch, c8, c0, 0
35 .endm
36 #else
37 .macro loadsp, rb
38 .endm
39 .macro writeb, ch, rb
40 mcr p14, 0, \ch, c1, c0, 0
41 .endm
42 #endif
44 #else
46 #include <mach/debug-macro.S>
48 .macro writeb, ch, rb
49 senduart \ch, \rb
50 .endm
52 #if defined(CONFIG_ARCH_SA1100)
53 .macro loadsp, rb
54 mov \rb, #0x80000000 @ physical base address
55 #ifdef CONFIG_DEBUG_LL_SER3
56 add \rb, \rb, #0x00050000 @ Ser3
57 #else
58 add \rb, \rb, #0x00010000 @ Ser1
59 #endif
60 .endm
61 #elif defined(CONFIG_ARCH_S3C2410)
62 .macro loadsp, rb
63 mov \rb, #0x50000000
64 add \rb, \rb, #0x4000 * CONFIG_S3C_LOWLEVEL_UART_PORT
65 .endm
66 #else
67 .macro loadsp, rb
68 addruart \rb
69 .endm
70 #endif
71 #endif
72 #endif
74 .macro kputc,val
75 mov r0, \val
76 bl putc
77 .endm
79 .macro kphex,val,len
80 mov r0, \val
81 mov r1, #\len
82 bl phex
83 .endm
85 .macro debug_reloc_start
86 #ifdef DEBUG
87 kputc #'\n'
88 kphex r6, 8 /* processor id */
89 kputc #':'
90 kphex r7, 8 /* architecture id */
91 #ifdef CONFIG_CPU_CP15
92 kputc #':'
93 mrc p15, 0, r0, c1, c0
94 kphex r0, 8 /* control reg */
95 #endif
96 kputc #'\n'
97 kphex r5, 8 /* decompressed kernel start */
98 kputc #'-'
99 kphex r9, 8 /* decompressed kernel end */
100 kputc #'>'
101 kphex r4, 8 /* kernel execution address */
102 kputc #'\n'
103 #endif
104 .endm
106 .macro debug_reloc_end
107 #ifdef DEBUG
108 kphex r5, 8 /* end of kernel */
109 kputc #'\n'
110 mov r0, r4
111 bl memdump /* dump 256 bytes at start of kernel */
112 #endif
113 .endm
115 .section ".start", #alloc, #execinstr
116 /*
117 * sort out different calling conventions
118 */
119 .align
120 start:
121 .type start,#function
122 .rept 8
123 mov r0, r0
124 .endr
126 b 1f
127 .word 0x016f2818 @ Magic numbers to help the loader
128 .word start @ absolute load/run zImage address
129 .word _edata @ zImage end address
130 1: mov r7, r1 @ save architecture ID
131 mov r8, r2 @ save atags pointer
133 #ifndef __ARM_ARCH_2__
134 /*
135 * Booting from Angel - need to enter SVC mode and disable
136 * FIQs/IRQs (numeric definitions from angel arm.h source).
137 * We only do this if we were in user mode on entry.
138 */
139 mrs r2, cpsr @ get current mode
140 tst r2, #3 @ not user?
141 bne not_angel
142 mov r0, #0x17 @ angel_SWIreason_EnterSVC
143 ARM( swi 0x123456 ) @ angel_SWI_ARM
144 THUMB( svc 0xab ) @ angel_SWI_THUMB
145 not_angel:
146 mrs r2, cpsr @ turn off interrupts to
147 orr r2, r2, #0xc0 @ prevent angel from running
148 msr cpsr_c, r2
149 #else
150 teqp pc, #0x0c000003 @ turn off interrupts
151 #endif
153 /*
154 * Note that some cache flushing and other stuff may
155 * be needed here - is there an Angel SWI call for this?
156 */
158 /*
159 * some architecture specific code can be inserted
160 * by the linker here, but it should preserve r7, r8, and r9.
161 */
163 .text
164 adr r0, LC0
165 ARM( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip, sp})
166 THUMB( ldmia r0, {r1, r2, r3, r4, r5, r6, r11, ip} )
167 THUMB( ldr sp, [r0, #32] )
168 subs r0, r0, r1 @ calculate the delta offset
170 @ if delta is zero, we are
171 beq not_relocated @ running at the address we
172 @ were linked at.
174 /*
175 * We're running at a different address. We need to fix
176 * up various pointers:
177 * r5 - zImage base address (_start)
178 * r6 - size of decompressed image
179 * r11 - GOT start
180 * ip - GOT end
181 */
182 add r5, r5, r0
183 add r11, r11, r0
184 add ip, ip, r0
186 #ifndef CONFIG_ZBOOT_ROM
187 /*
188 * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
189 * we need to fix up pointers into the BSS region.
190 * r2 - BSS start
191 * r3 - BSS end
192 * sp - stack pointer
193 */
194 add r2, r2, r0
195 add r3, r3, r0
196 add sp, sp, r0
198 /*
199 * Relocate all entries in the GOT table.
200 */
201 1: ldr r1, [r11, #0] @ relocate entries in the GOT
202 add r1, r1, r0 @ table. This fixes up the
203 str r1, [r11], #4 @ C references.
204 cmp r11, ip
205 blo 1b
206 #else
208 /*
209 * Relocate entries in the GOT table. We only relocate
210 * the entries that are outside the (relocated) BSS region.
211 */
212 1: ldr r1, [r11, #0] @ relocate entries in the GOT
213 cmp r1, r2 @ entry < bss_start ||
214 cmphs r3, r1 @ _end < entry
215 addlo r1, r1, r0 @ table. This fixes up the
216 str r1, [r11], #4 @ C references.
217 cmp r11, ip
218 blo 1b
219 #endif
221 not_relocated: mov r0, #0
222 1: str r0, [r2], #4 @ clear bss
223 str r0, [r2], #4
224 str r0, [r2], #4
225 str r0, [r2], #4
226 cmp r2, r3
227 blo 1b
229 /*
230 * The C runtime environment should now be setup
231 * sufficiently. Turn the cache on, set up some
232 * pointers, and start decompressing.
233 */
234 bl cache_on
236 mov r1, sp @ malloc space above stack
237 add r2, sp, #0x10000 @ 64k max
239 /*
240 * Check to see if we will overwrite ourselves.
241 * r4 = final kernel address
242 * r5 = start of this image
243 * r6 = size of decompressed image
244 * r2 = end of malloc space (and therefore this image)
245 * We basically want:
246 * r4 >= r2 -> OK
247 * r4 + image length <= r5 -> OK
248 */
249 cmp r4, r2
250 bhs wont_overwrite
251 add r0, r4, r6
252 cmp r0, r5
253 bls wont_overwrite
255 mov r5, r2 @ decompress after malloc space
256 mov r0, r5
257 mov r3, r7
258 bl decompress_kernel
260 add r0, r0, #127 + 128 @ alignment + stack
261 bic r0, r0, #127 @ align the kernel length
262 /*
263 * r0 = decompressed kernel length
264 * r1-r3 = unused
265 * r4 = kernel execution address
266 * r5 = decompressed kernel start
267 * r7 = architecture ID
268 * r8 = atags pointer
269 * r9-r12,r14 = corrupted
270 */
271 add r1, r5, r0 @ end of decompressed kernel
272 adr r2, reloc_start
273 ldr r3, LC1
274 add r3, r2, r3
275 1: ldmia r2!, {r9 - r12, r14} @ copy relocation code
276 stmia r1!, {r9 - r12, r14}
277 ldmia r2!, {r9 - r12, r14}
278 stmia r1!, {r9 - r12, r14}
279 cmp r2, r3
280 blo 1b
281 mov sp, r1
282 add sp, sp, #128 @ relocate the stack
284 bl cache_clean_flush
285 ARM( add pc, r5, r0 ) @ call relocation code
286 THUMB( add r12, r5, r0 )
287 THUMB( mov pc, r12 ) @ call relocation code
289 /*
290 * We're not in danger of overwriting ourselves. Do this the simple way.
291 *
292 * r4 = kernel execution address
293 * r7 = architecture ID
294 */
295 wont_overwrite: mov r0, r4
296 mov r3, r7
297 bl decompress_kernel
298 b call_kernel
300 .align 2
301 .type LC0, #object
302 LC0: .word LC0 @ r1
303 .word __bss_start @ r2
304 .word _end @ r3
305 .word zreladdr @ r4
306 .word _start @ r5
307 .word _image_size @ r6
308 .word _got_start @ r11
309 .word _got_end @ ip
310 .word user_stack+4096 @ sp
311 LC1: .word reloc_end - reloc_start
312 .size LC0, . - LC0
314 #ifdef CONFIG_ARCH_RPC
315 .globl params
316 params: ldr r0, =params_phys
317 mov pc, lr
318 .ltorg
319 .align
320 #endif
322 /*
323 * Turn on the cache. We need to setup some page tables so that we
324 * can have both the I and D caches on.
325 *
326 * We place the page tables 16k down from the kernel execution address,
327 * and we hope that nothing else is using it. If we're using it, we
328 * will go pop!
329 *
330 * On entry,
331 * r4 = kernel execution address
332 * r7 = architecture number
333 * r8 = atags pointer
334 * r9 = run-time address of "start" (???)
335 * On exit,
336 * r1, r2, r3, r9, r10, r12 corrupted
337 * This routine must preserve:
338 * r4, r5, r6, r7, r8
339 */
340 .align 5
341 cache_on: mov r3, #8 @ cache_on function
342 b call_cache_fn
344 /*
345 * Initialize the highest priority protection region, PR7
346 * to cover all 32bit address and cacheable and bufferable.
347 */
348 __armv4_mpu_cache_on:
349 mov r0, #0x3f @ 4G, the whole
350 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
351 mcr p15, 0, r0, c6, c7, 1
353 mov r0, #0x80 @ PR7
354 mcr p15, 0, r0, c2, c0, 0 @ D-cache on
355 mcr p15, 0, r0, c2, c0, 1 @ I-cache on
356 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
358 mov r0, #0xc000
359 mcr p15, 0, r0, c5, c0, 1 @ I-access permission
360 mcr p15, 0, r0, c5, c0, 0 @ D-access permission
362 mov r0, #0
363 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
364 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
365 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
366 mrc p15, 0, r0, c1, c0, 0 @ read control reg
367 @ ...I .... ..D. WC.M
368 orr r0, r0, #0x002d @ .... .... ..1. 11.1
369 orr r0, r0, #0x1000 @ ...1 .... .... ....
371 mcr p15, 0, r0, c1, c0, 0 @ write control reg
373 mov r0, #0
374 mcr p15, 0, r0, c7, c5, 0 @ flush(inval) I-Cache
375 mcr p15, 0, r0, c7, c6, 0 @ flush(inval) D-Cache
376 mov pc, lr
378 __armv3_mpu_cache_on:
379 mov r0, #0x3f @ 4G, the whole
380 mcr p15, 0, r0, c6, c7, 0 @ PR7 Area Setting
382 mov r0, #0x80 @ PR7
383 mcr p15, 0, r0, c2, c0, 0 @ cache on
384 mcr p15, 0, r0, c3, c0, 0 @ write-buffer on
386 mov r0, #0xc000
387 mcr p15, 0, r0, c5, c0, 0 @ access permission
389 mov r0, #0
390 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
391 mrc p15, 0, r0, c1, c0, 0 @ read control reg
392 @ .... .... .... WC.M
393 orr r0, r0, #0x000d @ .... .... .... 11.1
394 mov r0, #0
395 mcr p15, 0, r0, c1, c0, 0 @ write control reg
397 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
398 mov pc, lr
400 __setup_mmu: sub r3, r4, #16384 @ Page directory size
401 bic r3, r3, #0xff @ Align the pointer
402 bic r3, r3, #0x3f00
403 /*
404 * Initialise the page tables, turning on the cacheable and bufferable
405 * bits for the RAM area only.
406 */
407 mov r0, r3
408 mov r9, r0, lsr #18
409 mov r9, r9, lsl #18 @ start of RAM
410 add r10, r9, #0x10000000 @ a reasonable RAM size
411 mov r1, #0x12
412 orr r1, r1, #3 << 10
413 add r2, r3, #16384
414 1: cmp r1, r9 @ if virt > start of RAM
415 orrhs r1, r1, #0x0c @ set cacheable, bufferable
416 cmp r1, r10 @ if virt > end of RAM
417 bichs r1, r1, #0x0c @ clear cacheable, bufferable
418 str r1, [r0], #4 @ 1:1 mapping
419 add r1, r1, #1048576
420 teq r0, r2
421 bne 1b
422 /*
423 * If ever we are running from Flash, then we surely want the cache
424 * to be enabled also for our execution instance... We map 2MB of it
425 * so there is no map overlap problem for up to 1 MB compressed kernel.
426 * If the execution is in RAM then we would only be duplicating the above.
427 */
428 mov r1, #0x1e
429 orr r1, r1, #3 << 10
430 mov r2, pc, lsr #20
431 orr r1, r1, r2, lsl #20
432 add r0, r3, r2, lsl #2
433 str r1, [r0], #4
434 add r1, r1, #1048576
435 str r1, [r0]
436 mov pc, lr
437 ENDPROC(__setup_mmu)
439 __armv4_mmu_cache_on:
440 mov r12, lr
441 #ifdef CONFIG_MMU
442 bl __setup_mmu
443 mov r0, #0
444 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
445 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
446 mrc p15, 0, r0, c1, c0, 0 @ read control reg
447 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
448 orr r0, r0, #0x0030
449 #ifdef CONFIG_CPU_ENDIAN_BE8
450 orr r0, r0, #1 << 25 @ big-endian page tables
451 #endif
452 bl __common_mmu_cache_on
453 mov r0, #0
454 mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
455 #endif
456 mov pc, r12
458 __armv7_mmu_cache_on:
459 mov r12, lr
460 #ifdef CONFIG_MMU
461 mrc p15, 0, r11, c0, c1, 4 @ read ID_MMFR0
462 tst r11, #0xf @ VMSA
463 blne __setup_mmu
464 mov r0, #0
465 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
466 tst r11, #0xf @ VMSA
467 mcrne p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
468 #endif
469 mrc p15, 0, r0, c1, c0, 0 @ read control reg
470 orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
471 orr r0, r0, #0x003c @ write buffer
472 #ifdef CONFIG_MMU
473 #ifdef CONFIG_CPU_ENDIAN_BE8
474 orr r0, r0, #1 << 25 @ big-endian page tables
475 #endif
476 orrne r0, r0, #1 @ MMU enabled
477 movne r1, #-1
478 mcrne p15, 0, r3, c2, c0, 0 @ load page table pointer
479 mcrne p15, 0, r1, c3, c0, 0 @ load domain access control
480 #endif
481 mcr p15, 0, r0, c1, c0, 0 @ load control register
482 mrc p15, 0, r0, c1, c0, 0 @ and read it back
483 mov r0, #0
484 mcr p15, 0, r0, c7, c5, 4 @ ISB
485 mov pc, r12
487 __fa526_cache_on:
488 mov r12, lr
489 bl __setup_mmu
490 mov r0, #0
491 mcr p15, 0, r0, c7, c7, 0 @ Invalidate whole cache
492 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
493 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
494 mrc p15, 0, r0, c1, c0, 0 @ read control reg
495 orr r0, r0, #0x1000 @ I-cache enable
496 bl __common_mmu_cache_on
497 mov r0, #0
498 mcr p15, 0, r0, c8, c7, 0 @ flush UTLB
499 mov pc, r12
501 __arm6_mmu_cache_on:
502 mov r12, lr
503 bl __setup_mmu
504 mov r0, #0
505 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
506 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
507 mov r0, #0x30
508 bl __common_mmu_cache_on
509 mov r0, #0
510 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
511 mov pc, r12
513 __common_mmu_cache_on:
514 #ifndef CONFIG_THUMB2_KERNEL
515 #ifndef DEBUG
516 orr r0, r0, #0x000d @ Write buffer, mmu
517 #endif
518 mov r1, #-1
519 mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
520 mcr p15, 0, r1, c3, c0, 0 @ load domain access control
521 b 1f
522 .align 5 @ cache line aligned
523 1: mcr p15, 0, r0, c1, c0, 0 @ load control register
524 mrc p15, 0, r0, c1, c0, 0 @ and read it back to
525 sub pc, lr, r0, lsr #32 @ properly flush pipeline
526 #endif
528 /*
529 * All code following this line is relocatable. It is relocated by
530 * the above code to the end of the decompressed kernel image and
531 * executed there. During this time, we have no stacks.
532 *
533 * r0 = decompressed kernel length
534 * r1-r3 = unused
535 * r4 = kernel execution address
536 * r5 = decompressed kernel start
537 * r7 = architecture ID
538 * r8 = atags pointer
539 * r9-r12,r14 = corrupted
540 */
541 .align 5
542 reloc_start: add r9, r5, r0
543 sub r9, r9, #128 @ do not copy the stack
544 debug_reloc_start
545 mov r1, r4
546 1:
547 .rept 4
548 ldmia r5!, {r0, r2, r3, r10 - r12, r14} @ relocate kernel
549 stmia r1!, {r0, r2, r3, r10 - r12, r14}
550 .endr
552 cmp r5, r9
553 blo 1b
554 mov sp, r1
555 add sp, sp, #128 @ relocate the stack
556 debug_reloc_end
558 call_kernel: bl cache_clean_flush
559 bl cache_off
560 mov r0, #0 @ must be zero
561 mov r1, r7 @ restore architecture number
562 mov r2, r8 @ restore atags pointer
563 mov pc, r4 @ call kernel
565 /*
566 * Here follow the relocatable cache support functions for the
567 * various processors. This is a generic hook for locating an
568 * entry and jumping to an instruction at the specified offset
569 * from the start of the block. Please note this is all position
570 * independent code.
571 *
572 * r1 = corrupted
573 * r2 = corrupted
574 * r3 = block offset
575 * r9 = corrupted
576 * r12 = corrupted
577 */
579 call_cache_fn: adr r12, proc_types
580 #ifdef CONFIG_CPU_CP15
581 mrc p15, 0, r9, c0, c0 @ get processor ID
582 #else
583 ldr r9, =CONFIG_PROCESSOR_ID
584 #endif
585 1: ldr r1, [r12, #0] @ get value
586 ldr r2, [r12, #4] @ get mask
587 eor r1, r1, r9 @ (real ^ match)
588 tst r1, r2 @ & mask
589 ARM( addeq pc, r12, r3 ) @ call cache function
590 THUMB( addeq r12, r3 )
591 THUMB( moveq pc, r12 ) @ call cache function
592 add r12, r12, #4*5
593 b 1b
595 /*
596 * Table for cache operations. This is basically:
597 * - CPU ID match
598 * - CPU ID mask
599 * - 'cache on' method instruction
600 * - 'cache off' method instruction
601 * - 'cache flush' method instruction
602 *
603 * We match an entry using: ((real_id ^ match) & mask) == 0
604 *
605 * Writethrough caches generally only need 'on' and 'off'
606 * methods. Writeback caches _must_ have the flush method
607 * defined.
608 */
609 .align 2
610 .type proc_types,#object
611 proc_types:
612 .word 0x41560600 @ ARM6/610
613 .word 0xffffffe0
614 W(b) __arm6_mmu_cache_off @ works, but slow
615 W(b) __arm6_mmu_cache_off
616 mov pc, lr
617 THUMB( nop )
618 @ b __arm6_mmu_cache_on @ untested
619 @ b __arm6_mmu_cache_off
620 @ b __armv3_mmu_cache_flush
622 .word 0x00000000 @ old ARM ID
623 .word 0x0000f000
624 mov pc, lr
625 THUMB( nop )
626 mov pc, lr
627 THUMB( nop )
628 mov pc, lr
629 THUMB( nop )
631 .word 0x41007000 @ ARM7/710
632 .word 0xfff8fe00
633 W(b) __arm7_mmu_cache_off
634 W(b) __arm7_mmu_cache_off
635 mov pc, lr
636 THUMB( nop )
638 .word 0x41807200 @ ARM720T (writethrough)
639 .word 0xffffff00
640 W(b) __armv4_mmu_cache_on
641 W(b) __armv4_mmu_cache_off
642 mov pc, lr
643 THUMB( nop )
645 .word 0x41007400 @ ARM74x
646 .word 0xff00ff00
647 W(b) __armv3_mpu_cache_on
648 W(b) __armv3_mpu_cache_off
649 W(b) __armv3_mpu_cache_flush
651 .word 0x41009400 @ ARM94x
652 .word 0xff00ff00
653 W(b) __armv4_mpu_cache_on
654 W(b) __armv4_mpu_cache_off
655 W(b) __armv4_mpu_cache_flush
657 .word 0x00007000 @ ARM7 IDs
658 .word 0x0000f000
659 mov pc, lr
660 THUMB( nop )
661 mov pc, lr
662 THUMB( nop )
663 mov pc, lr
664 THUMB( nop )
666 @ Everything from here on will be the new ID system.
668 .word 0x4401a100 @ sa110 / sa1100
669 .word 0xffffffe0
670 W(b) __armv4_mmu_cache_on
671 W(b) __armv4_mmu_cache_off
672 W(b) __armv4_mmu_cache_flush
674 .word 0x6901b110 @ sa1110
675 .word 0xfffffff0
676 W(b) __armv4_mmu_cache_on
677 W(b) __armv4_mmu_cache_off
678 W(b) __armv4_mmu_cache_flush
680 .word 0x56056930
681 .word 0xff0ffff0 @ PXA935
682 W(b) __armv4_mmu_cache_on
683 W(b) __armv4_mmu_cache_off
684 W(b) __armv4_mmu_cache_flush
686 .word 0x56158000 @ PXA168
687 .word 0xfffff000
688 W(b) __armv4_mmu_cache_on
689 W(b) __armv4_mmu_cache_off
690 W(b) __armv5tej_mmu_cache_flush
692 .word 0x56056930
693 .word 0xff0ffff0 @ PXA935
694 W(b) __armv4_mmu_cache_on
695 W(b) __armv4_mmu_cache_off
696 W(b) __armv4_mmu_cache_flush
698 .word 0x56050000 @ Feroceon
699 .word 0xff0f0000
700 W(b) __armv4_mmu_cache_on
701 W(b) __armv4_mmu_cache_off
702 W(b) __armv5tej_mmu_cache_flush
704 #ifdef CONFIG_CPU_FEROCEON_OLD_ID
705 /* this conflicts with the standard ARMv5TE entry */
706 .long 0x41009260 @ Old Feroceon
707 .long 0xff00fff0
708 b __armv4_mmu_cache_on
709 b __armv4_mmu_cache_off
710 b __armv5tej_mmu_cache_flush
711 #endif
713 .word 0x66015261 @ FA526
714 .word 0xff01fff1
715 W(b) __fa526_cache_on
716 W(b) __armv4_mmu_cache_off
717 W(b) __fa526_cache_flush
719 @ These match on the architecture ID
721 .word 0x00020000 @ ARMv4T
722 .word 0x000f0000
723 W(b) __armv4_mmu_cache_on
724 W(b) __armv4_mmu_cache_off
725 W(b) __armv4_mmu_cache_flush
727 .word 0x00050000 @ ARMv5TE
728 .word 0x000f0000
729 W(b) __armv4_mmu_cache_on
730 W(b) __armv4_mmu_cache_off
731 W(b) __armv4_mmu_cache_flush
733 .word 0x00060000 @ ARMv5TEJ
734 .word 0x000f0000
735 W(b) __armv4_mmu_cache_on
736 W(b) __armv4_mmu_cache_off
737 W(b) __armv4_mmu_cache_flush
739 .word 0x0007b000 @ ARMv6
740 .word 0x000ff000
741 W(b) __armv4_mmu_cache_on
742 W(b) __armv4_mmu_cache_off
743 W(b) __armv6_mmu_cache_flush
745 .word 0x000f0000 @ new CPU Id
746 .word 0x000f0000
747 W(b) __armv7_mmu_cache_on
748 W(b) __armv7_mmu_cache_off
749 W(b) __armv7_mmu_cache_flush
751 .word 0 @ unrecognised type
752 .word 0
753 mov pc, lr
754 THUMB( nop )
755 mov pc, lr
756 THUMB( nop )
757 mov pc, lr
758 THUMB( nop )
760 .size proc_types, . - proc_types
762 /*
763 * Turn off the Cache and MMU. ARMv3 does not support
764 * reading the control register, but ARMv4 does.
765 *
766 * On exit, r0, r1, r2, r3, r9, r12 corrupted
767 * This routine must preserve: r4, r6, r7
768 */
769 .align 5
770 cache_off: mov r3, #12 @ cache_off function
771 b call_cache_fn
773 __armv4_mpu_cache_off:
774 mrc p15, 0, r0, c1, c0
775 bic r0, r0, #0x000d
776 mcr p15, 0, r0, c1, c0 @ turn MPU and cache off
777 mov r0, #0
778 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
779 mcr p15, 0, r0, c7, c6, 0 @ flush D-Cache
780 mcr p15, 0, r0, c7, c5, 0 @ flush I-Cache
781 mov pc, lr
783 __armv3_mpu_cache_off:
784 mrc p15, 0, r0, c1, c0
785 bic r0, r0, #0x000d
786 mcr p15, 0, r0, c1, c0, 0 @ turn MPU and cache off
787 mov r0, #0
788 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
789 mov pc, lr
791 __armv4_mmu_cache_off:
792 #ifdef CONFIG_MMU
793 mrc p15, 0, r0, c1, c0
794 bic r0, r0, #0x000d
795 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
796 mov r0, #0
797 mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
798 mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
799 #endif
800 mov pc, lr
802 __armv7_mmu_cache_off:
803 mrc p15, 0, r0, c1, c0
804 #ifdef CONFIG_MMU
805 bic r0, r0, #0x000d
806 #else
807 bic r0, r0, #0x000c
808 #endif
809 mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
810 mov r12, lr
811 bl __armv7_mmu_cache_flush
812 mov r0, #0
813 #ifdef CONFIG_MMU
814 mcr p15, 0, r0, c8, c7, 0 @ invalidate whole TLB
815 #endif
816 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTC
817 mcr p15, 0, r0, c7, c10, 4 @ DSB
818 mcr p15, 0, r0, c7, c5, 4 @ ISB
819 mov pc, r12
821 __arm6_mmu_cache_off:
822 mov r0, #0x00000030 @ ARM6 control reg.
823 b __armv3_mmu_cache_off
825 __arm7_mmu_cache_off:
826 mov r0, #0x00000070 @ ARM7 control reg.
827 b __armv3_mmu_cache_off
829 __armv3_mmu_cache_off:
830 mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
831 mov r0, #0
832 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
833 mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
834 mov pc, lr
836 /*
837 * Clean and flush the cache to maintain consistency.
838 *
839 * On exit,
840 * r1, r2, r3, r9, r11, r12 corrupted
841 * This routine must preserve:
842 * r0, r4, r5, r6, r7
843 */
844 .align 5
845 cache_clean_flush:
846 mov r3, #16
847 b call_cache_fn
849 __armv4_mpu_cache_flush:
850 mov r2, #1
851 mov r3, #0
852 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
853 mov r1, #7 << 5 @ 8 segments
854 1: orr r3, r1, #63 << 26 @ 64 entries
855 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index
856 subs r3, r3, #1 << 26
857 bcs 2b @ entries 63 to 0
858 subs r1, r1, #1 << 5
859 bcs 1b @ segments 7 to 0
861 teq r2, #0
862 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
863 mcr p15, 0, ip, c7, c10, 4 @ drain WB
864 mov pc, lr
866 __fa526_cache_flush:
867 mov r1, #0
868 mcr p15, 0, r1, c7, c14, 0 @ clean and invalidate D cache
869 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
870 mcr p15, 0, r1, c7, c10, 4 @ drain WB
871 mov pc, lr
873 __armv6_mmu_cache_flush:
874 mov r1, #0
875 mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
876 mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
877 mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
878 mcr p15, 0, r1, c7, c10, 4 @ drain WB
879 mov pc, lr
881 __armv7_mmu_cache_flush:
882 mrc p15, 0, r10, c0, c1, 5 @ read ID_MMFR1
883 tst r10, #0xf << 16 @ hierarchical cache (ARMv7)
884 mov r10, #0
885 beq hierarchical
886 mcr p15, 0, r10, c7, c14, 0 @ clean+invalidate D
887 b iflush
888 hierarchical:
889 mcr p15, 0, r10, c7, c10, 5 @ DMB
890 stmfd sp!, {r0-r7, r9-r11}
891 mrc p15, 1, r0, c0, c0, 1 @ read clidr
892 ands r3, r0, #0x7000000 @ extract loc from clidr
893 mov r3, r3, lsr #23 @ left align loc bit field
894 beq finished @ if loc is 0, then no need to clean
895 mov r10, #0 @ start clean at cache level 0
896 loop1:
897 add r2, r10, r10, lsr #1 @ work out 3x current cache level
898 mov r1, r0, lsr r2 @ extract cache type bits from clidr
899 and r1, r1, #7 @ mask of the bits for current cache only
900 cmp r1, #2 @ see what cache we have at this level
901 blt skip @ skip if no cache, or just i-cache
902 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
903 mcr p15, 0, r10, c7, c5, 4 @ isb to sych the new cssr&csidr
904 mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
905 and r2, r1, #7 @ extract the length of the cache lines
906 add r2, r2, #4 @ add 4 (line length offset)
907 ldr r4, =0x3ff
908 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
909 clz r5, r4 @ find bit position of way size increment
910 ldr r7, =0x7fff
911 ands r7, r7, r1, lsr #13 @ extract max number of the index size
912 loop2:
913 mov r9, r4 @ create working copy of max way size
914 loop3:
915 ARM( orr r11, r10, r9, lsl r5 ) @ factor way and cache number into r11
916 ARM( orr r11, r11, r7, lsl r2 ) @ factor index number into r11
917 THUMB( lsl r6, r9, r5 )
918 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
919 THUMB( lsl r6, r7, r2 )
920 THUMB( orr r11, r11, r6 ) @ factor index number into r11
921 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
922 subs r9, r9, #1 @ decrement the way
923 bge loop3
924 subs r7, r7, #1 @ decrement the index
925 bge loop2
926 skip:
927 add r10, r10, #2 @ increment cache number
928 cmp r3, r10
929 bgt loop1
930 finished:
931 ldmfd sp!, {r0-r7, r9-r11}
932 mov r10, #0 @ swith back to cache level 0
933 mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
934 iflush:
935 mcr p15, 0, r10, c7, c10, 4 @ DSB
936 mcr p15, 0, r10, c7, c5, 0 @ invalidate I+BTB
937 mcr p15, 0, r10, c7, c10, 4 @ DSB
938 mcr p15, 0, r10, c7, c5, 4 @ ISB
939 mov pc, lr
941 __armv5tej_mmu_cache_flush:
942 1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate D cache
943 bne 1b
944 mcr p15, 0, r0, c7, c5, 0 @ flush I cache
945 mcr p15, 0, r0, c7, c10, 4 @ drain WB
946 mov pc, lr
948 __armv4_mmu_cache_flush:
949 mov r2, #64*1024 @ default: 32K dcache size (*2)
950 mov r11, #32 @ default: 32 byte line size
951 mrc p15, 0, r3, c0, c0, 1 @ read cache type
952 teq r3, r9 @ cache ID register present?
953 beq no_cache_id
954 mov r1, r3, lsr #18
955 and r1, r1, #7
956 mov r2, #1024
957 mov r2, r2, lsl r1 @ base dcache size *2
958 tst r3, #1 << 14 @ test M bit
959 addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
960 mov r3, r3, lsr #12
961 and r3, r3, #3
962 mov r11, #8
963 mov r11, r11, lsl r3 @ cache line size in bytes
964 no_cache_id:
965 mov r1, pc
966 bic r1, r1, #63 @ align to longest cache line
967 add r2, r1, r2
968 1:
969 ARM( ldr r3, [r1], r11 ) @ s/w flush D cache
970 THUMB( ldr r3, [r1] ) @ s/w flush D cache
971 THUMB( add r1, r1, r11 )
972 teq r1, r2
973 bne 1b
975 mcr p15, 0, r1, c7, c5, 0 @ flush I cache
976 mcr p15, 0, r1, c7, c6, 0 @ flush D cache
977 mcr p15, 0, r1, c7, c10, 4 @ drain WB
978 mov pc, lr
980 __armv3_mmu_cache_flush:
981 __armv3_mpu_cache_flush:
982 mov r1, #0
983 mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
984 mov pc, lr
986 /*
987 * Various debugging routines for printing hex characters and
988 * memory, which again must be relocatable.
989 */
990 #ifdef DEBUG
991 .align 2
992 .type phexbuf,#object
993 phexbuf: .space 12
994 .size phexbuf, . - phexbuf
996 phex: adr r3, phexbuf
997 mov r2, #0
998 strb r2, [r3, r1]
999 1: subs r1, r1, #1
1000 movmi r0, r3
1001 bmi puts
1002 and r2, r0, #15
1003 mov r0, r0, lsr #4
1004 cmp r2, #10
1005 addge r2, r2, #7
1006 add r2, r2, #'0'
1007 strb r2, [r3, r1]
1008 b 1b
1010 puts: loadsp r3
1011 1: ldrb r2, [r0], #1
1012 teq r2, #0
1013 moveq pc, lr
1014 2: writeb r2, r3
1015 mov r1, #0x00020000
1016 3: subs r1, r1, #1
1017 bne 3b
1018 teq r2, #'\n'
1019 moveq r2, #'\r'
1020 beq 2b
1021 teq r0, #0
1022 bne 1b
1023 mov pc, lr
1024 putc:
1025 mov r2, r0
1026 mov r0, #0
1027 loadsp r3
1028 b 2b
1030 memdump: mov r12, r0
1031 mov r10, lr
1032 mov r11, #0
1033 2: mov r0, r11, lsl #2
1034 add r0, r0, r12
1035 mov r1, #8
1036 bl phex
1037 mov r0, #':'
1038 bl putc
1039 1: mov r0, #' '
1040 bl putc
1041 ldr r0, [r12, r11, lsl #2]
1042 mov r1, #8
1043 bl phex
1044 and r0, r11, #7
1045 teq r0, #3
1046 moveq r0, #' '
1047 bleq putc
1048 and r0, r11, #7
1049 add r11, r11, #1
1050 teq r0, #7
1051 bne 1b
1052 mov r0, #'\n'
1053 bl putc
1054 cmp r11, #64
1055 blt 2b
1056 mov pc, r10
1057 #endif
1059 .ltorg
1060 reloc_end:
1062 .align
1063 .section ".stack", "w"
1064 user_stack: .space 4096