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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / arch / x86 / kernel / amd_iommu_init.c
blobfc5d470f2786ef3782e97cdeb4181294c756e866
1 /*
2 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/gfp.h>
23 #include <linux/list.h>
24 #include <linux/sysdev.h>
25 #include <linux/interrupt.h>
26 #include <linux/msi.h>
27 #include <asm/pci-direct.h>
28 #include <asm/amd_iommu_types.h>
29 #include <asm/amd_iommu.h>
30 #include <asm/iommu.h>
31 #include <asm/gart.h>
32
33 /*
34 * definitions for the ACPI scanning code
35 */
36 #define IVRS_HEADER_LENGTH 48
37
38 #define ACPI_IVHD_TYPE 0x10
39 #define ACPI_IVMD_TYPE_ALL 0x20
40 #define ACPI_IVMD_TYPE 0x21
41 #define ACPI_IVMD_TYPE_RANGE 0x22
42
43 #define IVHD_DEV_ALL 0x01
44 #define IVHD_DEV_SELECT 0x02
45 #define IVHD_DEV_SELECT_RANGE_START 0x03
46 #define IVHD_DEV_RANGE_END 0x04
47 #define IVHD_DEV_ALIAS 0x42
48 #define IVHD_DEV_ALIAS_RANGE 0x43
49 #define IVHD_DEV_EXT_SELECT 0x46
50 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
51
52 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
53 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
54 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
55 #define IVHD_FLAG_ISOC_EN_MASK 0x08
56
57 #define IVMD_FLAG_EXCL_RANGE 0x08
58 #define IVMD_FLAG_UNITY_MAP 0x01
59
60 #define ACPI_DEVFLAG_INITPASS 0x01
61 #define ACPI_DEVFLAG_EXTINT 0x02
62 #define ACPI_DEVFLAG_NMI 0x04
63 #define ACPI_DEVFLAG_SYSMGT1 0x10
64 #define ACPI_DEVFLAG_SYSMGT2 0x20
65 #define ACPI_DEVFLAG_LINT0 0x40
66 #define ACPI_DEVFLAG_LINT1 0x80
67 #define ACPI_DEVFLAG_ATSDIS 0x10000000
68
69 /*
70 * ACPI table definitions
71 *
72 * These data structures are laid over the table to parse the important values
73 * out of it.
74 */
75
76 /*
77 * structure describing one IOMMU in the ACPI table. Typically followed by one
78 * or more ivhd_entrys.
79 */
80 struct ivhd_header {
81 u8 type;
82 u8 flags;
83 u16 length;
84 u16 devid;
85 u16 cap_ptr;
86 u64 mmio_phys;
87 u16 pci_seg;
88 u16 info;
89 u32 reserved;
90 } __attribute__((packed));
91
92 /*
93 * A device entry describing which devices a specific IOMMU translates and
94 * which requestor ids they use.
95 */
96 struct ivhd_entry {
97 u8 type;
98 u16 devid;
99 u8 flags;
100 u32 ext;
101 } __attribute__((packed));
102
103 /*
104 * An AMD IOMMU memory definition structure. It defines things like exclusion
105 * ranges for devices and regions that should be unity mapped.
106 */
107 struct ivmd_header {
108 u8 type;
109 u8 flags;
110 u16 length;
111 u16 devid;
112 u16 aux;
113 u64 resv;
114 u64 range_start;
115 u64 range_length;
116 } __attribute__((packed));
117
118 bool amd_iommu_dump;
119
120 static int __initdata amd_iommu_detected;
121
122 u16 amd_iommu_last_bdf; /* largest PCI device id we have
123 to handle */
124 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
125 we find in ACPI */
126 #ifdef CONFIG_IOMMU_STRESS
127 bool amd_iommu_isolate = false;
128 #else
129 bool amd_iommu_isolate = true; /* if true, device isolation is
130 enabled */
131 #endif
132
133 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
134
135 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
136 system */
137
138 /*
139 * Set to true if ACPI table parsing and hardware intialization went properly
140 */
141 static bool amd_iommu_initialized;
142
143 /*
144 * Pointer to the device table which is shared by all AMD IOMMUs
145 * it is indexed by the PCI device id or the HT unit id and contains
146 * information about the domain the device belongs to as well as the
147 * page table root pointer.
148 */
149 struct dev_table_entry *amd_iommu_dev_table;
150
151 /*
152 * The alias table is a driver specific data structure which contains the
153 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
154 * More than one device can share the same requestor id.
155 */
156 u16 *amd_iommu_alias_table;
157
158 /*
159 * The rlookup table is used to find the IOMMU which is responsible
160 * for a specific device. It is also indexed by the PCI device id.
161 */
162 struct amd_iommu **amd_iommu_rlookup_table;
163
164 /*
165 * The pd table (protection domain table) is used to find the protection domain
166 * data structure a device belongs to. Indexed with the PCI device id too.
167 */
168 struct protection_domain **amd_iommu_pd_table;
169
170 /*
171 * AMD IOMMU allows up to 2^16 differend protection domains. This is a bitmap
172 * to know which ones are already in use.
173 */
174 unsigned long *amd_iommu_pd_alloc_bitmap;
175
176 static u32 dev_table_size; /* size of the device table */
177 static u32 alias_table_size; /* size of the alias table */
178 static u32 rlookup_table_size; /* size if the rlookup table */
179
180 static inline void update_last_devid(u16 devid)
181 {
182 if (devid > amd_iommu_last_bdf)
183 amd_iommu_last_bdf = devid;
184 }
185
186 static inline unsigned long tbl_size(int entry_size)
187 {
188 unsigned shift = PAGE_SHIFT +
189 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
190
191 return 1UL << shift;
192 }
193
194 /****************************************************************************
195 *
196 * AMD IOMMU MMIO register space handling functions
197 *
198 * These functions are used to program the IOMMU device registers in
199 * MMIO space required for that driver.
200 *
201 ****************************************************************************/
202
203 /*
204 * This function set the exclusion range in the IOMMU. DMA accesses to the
205 * exclusion range are passed through untranslated
206 */
207 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
208 {
209 u64 start = iommu->exclusion_start & PAGE_MASK;
210 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
211 u64 entry;
212
213 if (!iommu->exclusion_start)
214 return;
215
216 entry = start | MMIO_EXCL_ENABLE_MASK;
217 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
218 &entry, sizeof(entry));
219
220 entry = limit;
221 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
222 &entry, sizeof(entry));
223 }
224
225 /* Programs the physical address of the device table into the IOMMU hardware */
226 static void __init iommu_set_device_table(struct amd_iommu *iommu)
227 {
228 u64 entry;
229
230 BUG_ON(iommu->mmio_base == NULL);
231
232 entry = virt_to_phys(amd_iommu_dev_table);
233 entry |= (dev_table_size >> 12) - 1;
234 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
235 &entry, sizeof(entry));
236 }
237
238 /* Generic functions to enable/disable certain features of the IOMMU. */
239 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
240 {
241 u32 ctrl;
242
243 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
244 ctrl |= (1 << bit);
245 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
246 }
247
248 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
249 {
250 u32 ctrl;
251
252 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
253 ctrl &= ~(1 << bit);
254 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
255 }
256
257 /* Function to enable the hardware */
258 static void iommu_enable(struct amd_iommu *iommu)
259 {
260 printk(KERN_INFO "AMD-Vi: Enabling IOMMU at %s cap 0x%hx\n",
261 dev_name(&iommu->dev->dev), iommu->cap_ptr);
262
263 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
264 }
265
266 static void iommu_disable(struct amd_iommu *iommu)
267 {
268 /* Disable command buffer */
269 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
270
271 /* Disable event logging and event interrupts */
272 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
273 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
274
275 /* Disable IOMMU hardware itself */
276 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
277 }
278
279 /*
280 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
281 * the system has one.
282 */
283 static u8 * __init iommu_map_mmio_space(u64 address)
284 {
285 u8 *ret;
286
287 if (!request_mem_region(address, MMIO_REGION_LENGTH, "amd_iommu"))
288 return NULL;
289
290 ret = ioremap_nocache(address, MMIO_REGION_LENGTH);
291 if (ret != NULL)
292 return ret;
293
294 release_mem_region(address, MMIO_REGION_LENGTH);
295
296 return NULL;
297 }
298
299 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
300 {
301 if (iommu->mmio_base)
302 iounmap(iommu->mmio_base);
303 release_mem_region(iommu->mmio_phys, MMIO_REGION_LENGTH);
304 }
305
306 /****************************************************************************
307 *
308 * The functions below belong to the first pass of AMD IOMMU ACPI table
309 * parsing. In this pass we try to find out the highest device id this
310 * code has to handle. Upon this information the size of the shared data
311 * structures is determined later.
312 *
313 ****************************************************************************/
314
315 /*
316 * This function calculates the length of a given IVHD entry
317 */
318 static inline int ivhd_entry_length(u8 *ivhd)
319 {
320 return 0x04 << (*ivhd >> 6);
321 }
322
323 /*
324 * This function reads the last device id the IOMMU has to handle from the PCI
325 * capability header for this IOMMU
326 */
327 static int __init find_last_devid_on_pci(int bus, int dev, int fn, int cap_ptr)
328 {
329 u32 cap;
330
331 cap = read_pci_config(bus, dev, fn, cap_ptr+MMIO_RANGE_OFFSET);
332 update_last_devid(calc_devid(MMIO_GET_BUS(cap), MMIO_GET_LD(cap)));
333
334 return 0;
335 }
336
337 /*
338 * After reading the highest device id from the IOMMU PCI capability header
339 * this function looks if there is a higher device id defined in the ACPI table
340 */
341 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
342 {
343 u8 *p = (void *)h, *end = (void *)h;
344 struct ivhd_entry *dev;
345
346 p += sizeof(*h);
347 end += h->length;
348
349 find_last_devid_on_pci(PCI_BUS(h->devid),
350 PCI_SLOT(h->devid),
351 PCI_FUNC(h->devid),
352 h->cap_ptr);
353
354 while (p < end) {
355 dev = (struct ivhd_entry *)p;
356 switch (dev->type) {
357 case IVHD_DEV_SELECT:
358 case IVHD_DEV_RANGE_END:
359 case IVHD_DEV_ALIAS:
360 case IVHD_DEV_EXT_SELECT:
361 /* all the above subfield types refer to device ids */
362 update_last_devid(dev->devid);
363 break;
364 default:
365 break;
366 }
367 p += ivhd_entry_length(p);
368 }
369
370 WARN_ON(p != end);
371
372 return 0;
373 }
374
375 /*
376 * Iterate over all IVHD entries in the ACPI table and find the highest device
377 * id which we need to handle. This is the first of three functions which parse
378 * the ACPI table. So we check the checksum here.
379 */
380 static int __init find_last_devid_acpi(struct acpi_table_header *table)
381 {
382 int i;
383 u8 checksum = 0, *p = (u8 *)table, *end = (u8 *)table;
384 struct ivhd_header *h;
385
386 /*
387 * Validate checksum here so we don't need to do it when
388 * we actually parse the table
389 */
390 for (i = 0; i < table->length; ++i)
391 checksum += p[i];
392 if (checksum != 0)
393 /* ACPI table corrupt */
394 return -ENODEV;
395
396 p += IVRS_HEADER_LENGTH;
397
398 end += table->length;
399 while (p < end) {
400 h = (struct ivhd_header *)p;
401 switch (h->type) {
402 case ACPI_IVHD_TYPE:
403 find_last_devid_from_ivhd(h);
404 break;
405 default:
406 break;
407 }
408 p += h->length;
409 }
410 WARN_ON(p != end);
411
412 return 0;
413 }
414
415 /****************************************************************************
416 *
417 * The following functions belong the the code path which parses the ACPI table
418 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
419 * data structures, initialize the device/alias/rlookup table and also
420 * basically initialize the hardware.
421 *
422 ****************************************************************************/
423
424 /*
425 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
426 * write commands to that buffer later and the IOMMU will execute them
427 * asynchronously
428 */
429 static u8 * __init alloc_command_buffer(struct amd_iommu *iommu)
430 {
431 u8 *cmd_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
432 get_order(CMD_BUFFER_SIZE));
433
434 if (cmd_buf == NULL)
435 return NULL;
436
437 iommu->cmd_buf_size = CMD_BUFFER_SIZE;
438
439 return cmd_buf;
440 }
441
442 /*
443 * This function resets the command buffer if the IOMMU stopped fetching
444 * commands from it.
445 */
446 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
447 {
448 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
449
450 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
451 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
452
453 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
454 }
455
456 /*
457 * This function writes the command buffer address to the hardware and
458 * enables it.
459 */
460 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
461 {
462 u64 entry;
463
464 BUG_ON(iommu->cmd_buf == NULL);
465
466 entry = (u64)virt_to_phys(iommu->cmd_buf);
467 entry |= MMIO_CMD_SIZE_512;
468
469 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
470 &entry, sizeof(entry));
471
472 amd_iommu_reset_cmd_buffer(iommu);
473 }
474
475 static void __init free_command_buffer(struct amd_iommu *iommu)
476 {
477 free_pages((unsigned long)iommu->cmd_buf,
478 get_order(iommu->cmd_buf_size));
479 }
480
481 /* allocates the memory where the IOMMU will log its events to */
482 static u8 * __init alloc_event_buffer(struct amd_iommu *iommu)
483 {
484 iommu->evt_buf = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
485 get_order(EVT_BUFFER_SIZE));
486
487 if (iommu->evt_buf == NULL)
488 return NULL;
489
490 iommu->evt_buf_size = EVT_BUFFER_SIZE;
491
492 return iommu->evt_buf;
493 }
494
495 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
496 {
497 u64 entry;
498
499 BUG_ON(iommu->evt_buf == NULL);
500
501 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
502
503 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
504 &entry, sizeof(entry));
505
506 /* set head and tail to zero manually */
507 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
508 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
509
510 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
511 }
512
513 static void __init free_event_buffer(struct amd_iommu *iommu)
514 {
515 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
516 }
517
518 /* sets a specific bit in the device table entry. */
519 static void set_dev_entry_bit(u16 devid, u8 bit)
520 {
521 int i = (bit >> 5) & 0x07;
522 int _bit = bit & 0x1f;
523
524 amd_iommu_dev_table[devid].data[i] |= (1 << _bit);
525 }
526
527 static int get_dev_entry_bit(u16 devid, u8 bit)
528 {
529 int i = (bit >> 5) & 0x07;
530 int _bit = bit & 0x1f;
531
532 return (amd_iommu_dev_table[devid].data[i] & (1 << _bit)) >> _bit;
533 }
534
535
536 void amd_iommu_apply_erratum_63(u16 devid)
537 {
538 int sysmgt;
539
540 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
541 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
542
543 if (sysmgt == 0x01)
544 set_dev_entry_bit(devid, DEV_ENTRY_IW);
545 }
546
547 /* Writes the specific IOMMU for a device into the rlookup table */
548 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
549 {
550 amd_iommu_rlookup_table[devid] = iommu;
551 }
552
553 /*
554 * This function takes the device specific flags read from the ACPI
555 * table and sets up the device table entry with that information
556 */
557 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
558 u16 devid, u32 flags, u32 ext_flags)
559 {
560 if (flags & ACPI_DEVFLAG_INITPASS)
561 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
562 if (flags & ACPI_DEVFLAG_EXTINT)
563 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
564 if (flags & ACPI_DEVFLAG_NMI)
565 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
566 if (flags & ACPI_DEVFLAG_SYSMGT1)
567 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
568 if (flags & ACPI_DEVFLAG_SYSMGT2)
569 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
570 if (flags & ACPI_DEVFLAG_LINT0)
571 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
572 if (flags & ACPI_DEVFLAG_LINT1)
573 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
574
575 amd_iommu_apply_erratum_63(devid);
576
577 set_iommu_for_device(iommu, devid);
578 }
579
580 /*
581 * Reads the device exclusion range from ACPI and initialize IOMMU with
582 * it
583 */
584 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
585 {
586 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
587
588 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
589 return;
590
591 if (iommu) {
592 /*
593 * We only can configure exclusion ranges per IOMMU, not
594 * per device. But we can enable the exclusion range per
595 * device. This is done here
596 */
597 set_dev_entry_bit(m->devid, DEV_ENTRY_EX);
598 iommu->exclusion_start = m->range_start;
599 iommu->exclusion_length = m->range_length;
600 }
601 }
602
603 /*
604 * This function reads some important data from the IOMMU PCI space and
605 * initializes the driver data structure with it. It reads the hardware
606 * capabilities and the first/last device entries
607 */
608 static void __init init_iommu_from_pci(struct amd_iommu *iommu)
609 {
610 int cap_ptr = iommu->cap_ptr;
611 u32 range, misc;
612
613 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
614 &iommu->cap);
615 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
616 &range);
617 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
618 &misc);
619
620 iommu->first_device = calc_devid(MMIO_GET_BUS(range),
621 MMIO_GET_FD(range));
622 iommu->last_device = calc_devid(MMIO_GET_BUS(range),
623 MMIO_GET_LD(range));
624 iommu->evt_msi_num = MMIO_MSI_NUM(misc);
625
626 if (is_rd890_iommu(iommu->dev)) {
627 pci_read_config_dword(iommu->dev, 0xf0, &iommu->cache_cfg[0]);
628 pci_read_config_dword(iommu->dev, 0xf4, &iommu->cache_cfg[1]);
629 pci_read_config_dword(iommu->dev, 0xf8, &iommu->cache_cfg[2]);
630 pci_read_config_dword(iommu->dev, 0xfc, &iommu->cache_cfg[3]);
631 }
632 }
633
634 /*
635 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
636 * initializes the hardware and our data structures with it.
637 */
638 static void __init init_iommu_from_acpi(struct amd_iommu *iommu,
639 struct ivhd_header *h)
640 {
641 u8 *p = (u8 *)h;
642 u8 *end = p, flags = 0;
643 u16 devid = 0, devid_start = 0, devid_to = 0;
644 u32 dev_i, ext_flags = 0;
645 bool alias = false;
646 struct ivhd_entry *e;
647
648 /*
649 * First save the recommended feature enable bits from ACPI
650 */
651 iommu->acpi_flags = h->flags;
652
653 /*
654 * Done. Now parse the device entries
655 */
656 p += sizeof(struct ivhd_header);
657 end += h->length;
658
659
660 while (p < end) {
661 e = (struct ivhd_entry *)p;
662 switch (e->type) {
663 case IVHD_DEV_ALL:
664
665 DUMP_printk(" DEV_ALL\t\t\t first devid: %02x:%02x.%x"
666 " last device %02x:%02x.%x flags: %02x\n",
667 PCI_BUS(iommu->first_device),
668 PCI_SLOT(iommu->first_device),
669 PCI_FUNC(iommu->first_device),
670 PCI_BUS(iommu->last_device),
671 PCI_SLOT(iommu->last_device),
672 PCI_FUNC(iommu->last_device),
673 e->flags);
674
675 for (dev_i = iommu->first_device;
676 dev_i <= iommu->last_device; ++dev_i)
677 set_dev_entry_from_acpi(iommu, dev_i,
678 e->flags, 0);
679 break;
680 case IVHD_DEV_SELECT:
681
682 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
683 "flags: %02x\n",
684 PCI_BUS(e->devid),
685 PCI_SLOT(e->devid),
686 PCI_FUNC(e->devid),
687 e->flags);
688
689 devid = e->devid;
690 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
691 break;
692 case IVHD_DEV_SELECT_RANGE_START:
693
694 DUMP_printk(" DEV_SELECT_RANGE_START\t "
695 "devid: %02x:%02x.%x flags: %02x\n",
696 PCI_BUS(e->devid),
697 PCI_SLOT(e->devid),
698 PCI_FUNC(e->devid),
699 e->flags);
700
701 devid_start = e->devid;
702 flags = e->flags;
703 ext_flags = 0;
704 alias = false;
705 break;
706 case IVHD_DEV_ALIAS:
707
708 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
709 "flags: %02x devid_to: %02x:%02x.%x\n",
710 PCI_BUS(e->devid),
711 PCI_SLOT(e->devid),
712 PCI_FUNC(e->devid),
713 e->flags,
714 PCI_BUS(e->ext >> 8),
715 PCI_SLOT(e->ext >> 8),
716 PCI_FUNC(e->ext >> 8));
717
718 devid = e->devid;
719 devid_to = e->ext >> 8;
720 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
721 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
722 amd_iommu_alias_table[devid] = devid_to;
723 break;
724 case IVHD_DEV_ALIAS_RANGE:
725
726 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
727 "devid: %02x:%02x.%x flags: %02x "
728 "devid_to: %02x:%02x.%x\n",
729 PCI_BUS(e->devid),
730 PCI_SLOT(e->devid),
731 PCI_FUNC(e->devid),
732 e->flags,
733 PCI_BUS(e->ext >> 8),
734 PCI_SLOT(e->ext >> 8),
735 PCI_FUNC(e->ext >> 8));
736
737 devid_start = e->devid;
738 flags = e->flags;
739 devid_to = e->ext >> 8;
740 ext_flags = 0;
741 alias = true;
742 break;
743 case IVHD_DEV_EXT_SELECT:
744
745 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
746 "flags: %02x ext: %08x\n",
747 PCI_BUS(e->devid),
748 PCI_SLOT(e->devid),
749 PCI_FUNC(e->devid),
750 e->flags, e->ext);
751
752 devid = e->devid;
753 set_dev_entry_from_acpi(iommu, devid, e->flags,
754 e->ext);
755 break;
756 case IVHD_DEV_EXT_SELECT_RANGE:
757
758 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
759 "%02x:%02x.%x flags: %02x ext: %08x\n",
760 PCI_BUS(e->devid),
761 PCI_SLOT(e->devid),
762 PCI_FUNC(e->devid),
763 e->flags, e->ext);
764
765 devid_start = e->devid;
766 flags = e->flags;
767 ext_flags = e->ext;
768 alias = false;
769 break;
770 case IVHD_DEV_RANGE_END:
771
772 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
773 PCI_BUS(e->devid),
774 PCI_SLOT(e->devid),
775 PCI_FUNC(e->devid));
776
777 devid = e->devid;
778 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
779 if (alias) {
780 amd_iommu_alias_table[dev_i] = devid_to;
781 set_dev_entry_from_acpi(iommu,
782 devid_to, flags, ext_flags);
783 }
784 set_dev_entry_from_acpi(iommu, dev_i,
785 flags, ext_flags);
786 }
787 break;
788 default:
789 break;
790 }
791
792 p += ivhd_entry_length(p);
793 }
794 }
795
796 /* Initializes the device->iommu mapping for the driver */
797 static int __init init_iommu_devices(struct amd_iommu *iommu)
798 {
799 u32 i;
800
801 for (i = iommu->first_device; i <= iommu->last_device; ++i)
802 set_iommu_for_device(iommu, i);
803
804 return 0;
805 }
806
807 static void __init free_iommu_one(struct amd_iommu *iommu)
808 {
809 free_command_buffer(iommu);
810 free_event_buffer(iommu);
811 iommu_unmap_mmio_space(iommu);
812 }
813
814 static void __init free_iommu_all(void)
815 {
816 struct amd_iommu *iommu, *next;
817
818 for_each_iommu_safe(iommu, next) {
819 list_del(&iommu->list);
820 free_iommu_one(iommu);
821 kfree(iommu);
822 }
823 }
824
825 /*
826 * This function clues the initialization function for one IOMMU
827 * together and also allocates the command buffer and programs the
828 * hardware. It does NOT enable the IOMMU. This is done afterwards.
829 */
830 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
831 {
832 spin_lock_init(&iommu->lock);
833 list_add_tail(&iommu->list, &amd_iommu_list);
834
835 /*
836 * Copy data from ACPI table entry to the iommu struct
837 */
838 iommu->dev = pci_get_bus_and_slot(PCI_BUS(h->devid), h->devid & 0xff);
839 if (!iommu->dev)
840 return 1;
841
842 iommu->cap_ptr = h->cap_ptr;
843 iommu->pci_seg = h->pci_seg;
844 iommu->mmio_phys = h->mmio_phys;
845 iommu->mmio_base = iommu_map_mmio_space(h->mmio_phys);
846 if (!iommu->mmio_base)
847 return -ENOMEM;
848
849 iommu->cmd_buf = alloc_command_buffer(iommu);
850 if (!iommu->cmd_buf)
851 return -ENOMEM;
852
853 iommu->evt_buf = alloc_event_buffer(iommu);
854 if (!iommu->evt_buf)
855 return -ENOMEM;
856
857 iommu->int_enabled = false;
858
859 init_iommu_from_pci(iommu);
860 init_iommu_from_acpi(iommu, h);
861 init_iommu_devices(iommu);
862
863 return pci_enable_device(iommu->dev);
864 }
865
866 /*
867 * Iterates over all IOMMU entries in the ACPI table, allocates the
868 * IOMMU structure and initializes it with init_iommu_one()
869 */
870 static int __init init_iommu_all(struct acpi_table_header *table)
871 {
872 u8 *p = (u8 *)table, *end = (u8 *)table;
873 struct ivhd_header *h;
874 struct amd_iommu *iommu;
875 int ret;
876
877 end += table->length;
878 p += IVRS_HEADER_LENGTH;
879
880 while (p < end) {
881 h = (struct ivhd_header *)p;
882 switch (*p) {
883 case ACPI_IVHD_TYPE:
884
885 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
886 "seg: %d flags: %01x info %04x\n",
887 PCI_BUS(h->devid), PCI_SLOT(h->devid),
888 PCI_FUNC(h->devid), h->cap_ptr,
889 h->pci_seg, h->flags, h->info);
890 DUMP_printk(" mmio-addr: %016llx\n",
891 h->mmio_phys);
892
893 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
894 if (iommu == NULL)
895 return -ENOMEM;
896 ret = init_iommu_one(iommu, h);
897 if (ret)
898 return ret;
899 break;
900 default:
901 break;
902 }
903 p += h->length;
904
905 }
906 WARN_ON(p != end);
907
908 amd_iommu_initialized = true;
909
910 return 0;
911 }
912
913 /****************************************************************************
914 *
915 * The following functions initialize the MSI interrupts for all IOMMUs
916 * in the system. Its a bit challenging because there could be multiple
917 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
918 * pci_dev.
919 *
920 ****************************************************************************/
921
922 static int iommu_setup_msi(struct amd_iommu *iommu)
923 {
924 int r;
925
926 if (pci_enable_msi(iommu->dev))
927 return 1;
928
929 r = request_irq(iommu->dev->irq, amd_iommu_int_handler,
930 IRQF_SAMPLE_RANDOM,
931 "AMD-Vi",
932 NULL);
933
934 if (r) {
935 pci_disable_msi(iommu->dev);
936 return 1;
937 }
938
939 iommu->int_enabled = true;
940 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
941
942 return 0;
943 }
944
945 static int iommu_init_msi(struct amd_iommu *iommu)
946 {
947 if (iommu->int_enabled)
948 return 0;
949
950 if (pci_find_capability(iommu->dev, PCI_CAP_ID_MSI))
951 return iommu_setup_msi(iommu);
952
953 return 1;
954 }
955
956 /****************************************************************************
957 *
958 * The next functions belong to the third pass of parsing the ACPI
959 * table. In this last pass the memory mapping requirements are
960 * gathered (like exclusion and unity mapping reanges).
961 *
962 ****************************************************************************/
963
964 static void __init free_unity_maps(void)
965 {
966 struct unity_map_entry *entry, *next;
967
968 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
969 list_del(&entry->list);
970 kfree(entry);
971 }
972 }
973
974 /* called when we find an exclusion range definition in ACPI */
975 static int __init init_exclusion_range(struct ivmd_header *m)
976 {
977 int i;
978
979 switch (m->type) {
980 case ACPI_IVMD_TYPE:
981 set_device_exclusion_range(m->devid, m);
982 break;
983 case ACPI_IVMD_TYPE_ALL:
984 for (i = 0; i <= amd_iommu_last_bdf; ++i)
985 set_device_exclusion_range(i, m);
986 break;
987 case ACPI_IVMD_TYPE_RANGE:
988 for (i = m->devid; i <= m->aux; ++i)
989 set_device_exclusion_range(i, m);
990 break;
991 default:
992 break;
993 }
994
995 return 0;
996 }
997
998 /* called for unity map ACPI definition */
999 static int __init init_unity_map_range(struct ivmd_header *m)
1000 {
1001 struct unity_map_entry *e = 0;
1002 char *s;
1003
1004 e = kzalloc(sizeof(*e), GFP_KERNEL);
1005 if (e == NULL)
1006 return -ENOMEM;
1007
1008 switch (m->type) {
1009 default:
1010 kfree(e);
1011 return 0;
1012 case ACPI_IVMD_TYPE:
1013 s = "IVMD_TYPEi\t\t\t";
1014 e->devid_start = e->devid_end = m->devid;
1015 break;
1016 case ACPI_IVMD_TYPE_ALL:
1017 s = "IVMD_TYPE_ALL\t\t";
1018 e->devid_start = 0;
1019 e->devid_end = amd_iommu_last_bdf;
1020 break;
1021 case ACPI_IVMD_TYPE_RANGE:
1022 s = "IVMD_TYPE_RANGE\t\t";
1023 e->devid_start = m->devid;
1024 e->devid_end = m->aux;
1025 break;
1026 }
1027 e->address_start = PAGE_ALIGN(m->range_start);
1028 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1029 e->prot = m->flags >> 1;
1030
1031 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1032 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1033 PCI_BUS(e->devid_start), PCI_SLOT(e->devid_start),
1034 PCI_FUNC(e->devid_start), PCI_BUS(e->devid_end),
1035 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1036 e->address_start, e->address_end, m->flags);
1037
1038 list_add_tail(&e->list, &amd_iommu_unity_map);
1039
1040 return 0;
1041 }
1042
1043 /* iterates over all memory definitions we find in the ACPI table */
1044 static int __init init_memory_definitions(struct acpi_table_header *table)
1045 {
1046 u8 *p = (u8 *)table, *end = (u8 *)table;
1047 struct ivmd_header *m;
1048
1049 end += table->length;
1050 p += IVRS_HEADER_LENGTH;
1051
1052 while (p < end) {
1053 m = (struct ivmd_header *)p;
1054 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1055 init_exclusion_range(m);
1056 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1057 init_unity_map_range(m);
1058
1059 p += m->length;
1060 }
1061
1062 return 0;
1063 }
1064
1065 /*
1066 * Init the device table to not allow DMA access for devices and
1067 * suppress all page faults
1068 */
1069 static void init_device_table(void)
1070 {
1071 u32 devid;
1072
1073 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1074 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1075 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1076 }
1077 }
1078
1079 static void iommu_init_flags(struct amd_iommu *iommu)
1080 {
1081 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1082 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1083 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1084
1085 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1086 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1087 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1088
1089 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1090 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1091 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1092
1093 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1094 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1095 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1096
1097 /*
1098 * make IOMMU memory accesses cache coherent
1099 */
1100 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1101 }
1102
1103 static void iommu_apply_quirks(struct amd_iommu *iommu)
1104 {
1105 if (is_rd890_iommu(iommu->dev)) {
1106 pci_write_config_dword(iommu->dev, 0xf0, iommu->cache_cfg[0]);
1107 pci_write_config_dword(iommu->dev, 0xf4, iommu->cache_cfg[1]);
1108 pci_write_config_dword(iommu->dev, 0xf8, iommu->cache_cfg[2]);
1109 pci_write_config_dword(iommu->dev, 0xfc, iommu->cache_cfg[3]);
1110 }
1111 }
1112
1113 /*
1114 * This function finally enables all IOMMUs found in the system after
1115 * they have been initialized
1116 */
1117 static void enable_iommus(void)
1118 {
1119 struct amd_iommu *iommu;
1120
1121 for_each_iommu(iommu) {
1122 iommu_disable(iommu);
1123 iommu_apply_quirks(iommu);
1124 iommu_init_flags(iommu);
1125 iommu_set_device_table(iommu);
1126 iommu_enable_command_buffer(iommu);
1127 iommu_enable_event_buffer(iommu);
1128 iommu_set_exclusion_range(iommu);
1129 iommu_init_msi(iommu);
1130 iommu_enable(iommu);
1131 }
1132 }
1133
1134 static void disable_iommus(void)
1135 {
1136 struct amd_iommu *iommu;
1137
1138 for_each_iommu(iommu)
1139 iommu_disable(iommu);
1140 }
1141
1142 /*
1143 * Suspend/Resume support
1144 * disable suspend until real resume implemented
1145 */
1146
1147 static int amd_iommu_resume(struct sys_device *dev)
1148 {
1149 /* re-load the hardware */
1150 enable_iommus();
1151
1152 /*
1153 * we have to flush after the IOMMUs are enabled because a
1154 * disabled IOMMU will never execute the commands we send
1155 */
1156 amd_iommu_flush_all_devices();
1157 amd_iommu_flush_all_domains();
1158
1159 return 0;
1160 }
1161
1162 static int amd_iommu_suspend(struct sys_device *dev, pm_message_t state)
1163 {
1164 /* disable IOMMUs to go out of the way for BIOS */
1165 disable_iommus();
1166
1167 return 0;
1168 }
1169
1170 static struct sysdev_class amd_iommu_sysdev_class = {
1171 .name = "amd_iommu",
1172 .suspend = amd_iommu_suspend,
1173 .resume = amd_iommu_resume,
1174 };
1175
1176 static struct sys_device device_amd_iommu = {
1177 .id = 0,
1178 .cls = &amd_iommu_sysdev_class,
1179 };
1180
1181 /*
1182 * This is the core init function for AMD IOMMU hardware in the system.
1183 * This function is called from the generic x86 DMA layer initialization
1184 * code.
1185 *
1186 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
1187 * three times:
1188 *
1189 * 1 pass) Find the highest PCI device id the driver has to handle.
1190 * Upon this information the size of the data structures is
1191 * determined that needs to be allocated.
1192 *
1193 * 2 pass) Initialize the data structures just allocated with the
1194 * information in the ACPI table about available AMD IOMMUs
1195 * in the system. It also maps the PCI devices in the
1196 * system to specific IOMMUs
1197 *
1198 * 3 pass) After the basic data structures are allocated and
1199 * initialized we update them with information about memory
1200 * remapping requirements parsed out of the ACPI table in
1201 * this last pass.
1202 *
1203 * After that the hardware is initialized and ready to go. In the last
1204 * step we do some Linux specific things like registering the driver in
1205 * the dma_ops interface and initializing the suspend/resume support
1206 * functions. Finally it prints some information about AMD IOMMUs and
1207 * the driver state and enables the hardware.
1208 */
1209 int __init amd_iommu_init(void)
1210 {
1211 int i, ret = 0;
1212
1213
1214 if (no_iommu) {
1215 printk(KERN_INFO "AMD-Vi disabled by kernel command line\n");
1216 return 0;
1217 }
1218
1219 if (!amd_iommu_detected)
1220 return -ENODEV;
1221
1222 /*
1223 * First parse ACPI tables to find the largest Bus/Dev/Func
1224 * we need to handle. Upon this information the shared data
1225 * structures for the IOMMUs in the system will be allocated
1226 */
1227 if (acpi_table_parse("IVRS", find_last_devid_acpi) != 0)
1228 return -ENODEV;
1229
1230 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
1231 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
1232 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
1233
1234 ret = -ENOMEM;
1235
1236 /* Device table - directly used by all IOMMUs */
1237 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1238 get_order(dev_table_size));
1239 if (amd_iommu_dev_table == NULL)
1240 goto out;
1241
1242 /*
1243 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
1244 * IOMMU see for that device
1245 */
1246 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
1247 get_order(alias_table_size));
1248 if (amd_iommu_alias_table == NULL)
1249 goto free;
1250
1251 /* IOMMU rlookup table - find the IOMMU for a specific device */
1252 amd_iommu_rlookup_table = (void *)__get_free_pages(
1253 GFP_KERNEL | __GFP_ZERO,
1254 get_order(rlookup_table_size));
1255 if (amd_iommu_rlookup_table == NULL)
1256 goto free;
1257
1258 /*
1259 * Protection Domain table - maps devices to protection domains
1260 * This table has the same size as the rlookup_table
1261 */
1262 amd_iommu_pd_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
1263 get_order(rlookup_table_size));
1264 if (amd_iommu_pd_table == NULL)
1265 goto free;
1266
1267 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
1268 GFP_KERNEL | __GFP_ZERO,
1269 get_order(MAX_DOMAIN_ID/8));
1270 if (amd_iommu_pd_alloc_bitmap == NULL)
1271 goto free;
1272
1273 /* init the device table */
1274 init_device_table();
1275
1276 /*
1277 * let all alias entries point to itself
1278 */
1279 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1280 amd_iommu_alias_table[i] = i;
1281
1282 /*
1283 * never allocate domain 0 because its used as the non-allocated and
1284 * error value placeholder
1285 */
1286 amd_iommu_pd_alloc_bitmap[0] = 1;
1287
1288 /*
1289 * now the data structures are allocated and basically initialized
1290 * start the real acpi table scan
1291 */
1292 ret = -ENODEV;
1293 if (acpi_table_parse("IVRS", init_iommu_all) != 0)
1294 goto free;
1295
1296 if (!amd_iommu_initialized)
1297 goto free;
1298
1299 if (acpi_table_parse("IVRS", init_memory_definitions) != 0)
1300 goto free;
1301
1302 ret = sysdev_class_register(&amd_iommu_sysdev_class);
1303 if (ret)
1304 goto free;
1305
1306 ret = sysdev_register(&device_amd_iommu);
1307 if (ret)
1308 goto free;
1309
1310 enable_iommus();
1311
1312 if (iommu_pass_through)
1313 ret = amd_iommu_init_passthrough();
1314 else
1315 ret = amd_iommu_init_dma_ops();
1316
1317 if (ret)
1318 goto free;
1319
1320 amd_iommu_init_api();
1321
1322 if (iommu_pass_through)
1323 goto out;
1324
1325 printk(KERN_INFO "AMD-Vi: device isolation ");
1326 if (amd_iommu_isolate)
1327 printk("enabled\n");
1328 else
1329 printk("disabled\n");
1330
1331 if (amd_iommu_unmap_flush)
1332 printk(KERN_INFO "AMD-Vi: IO/TLB flush on unmap enabled\n");
1333 else
1334 printk(KERN_INFO "AMD-Vi: Lazy IO/TLB flushing enabled\n");
1335
1336 out:
1337 return ret;
1338
1339 free:
1340 disable_iommus();
1341
1342 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
1343 get_order(MAX_DOMAIN_ID/8));
1344
1345 free_pages((unsigned long)amd_iommu_pd_table,
1346 get_order(rlookup_table_size));
1347
1348 free_pages((unsigned long)amd_iommu_rlookup_table,
1349 get_order(rlookup_table_size));
1350
1351 free_pages((unsigned long)amd_iommu_alias_table,
1352 get_order(alias_table_size));
1353
1354 free_pages((unsigned long)amd_iommu_dev_table,
1355 get_order(dev_table_size));
1356
1357 free_iommu_all();
1358
1359 free_unity_maps();
1360
1361 goto out;
1362 }
1363
1364 void amd_iommu_shutdown(void)
1365 {
1366 disable_iommus();
1367 }
1368
1369 /****************************************************************************
1370 *
1371 * Early detect code. This code runs at IOMMU detection time in the DMA
1372 * layer. It just looks if there is an IVRS ACPI table to detect AMD
1373 * IOMMUs
1374 *
1375 ****************************************************************************/
1376 static int __init early_amd_iommu_detect(struct acpi_table_header *table)
1377 {
1378 return 0;
1379 }
1380
1381 void __init amd_iommu_detect(void)
1382 {
1383 if (swiotlb || no_iommu || (iommu_detected && !gart_iommu_aperture))
1384 return;
1385
1386 if (acpi_table_parse("IVRS", early_amd_iommu_detect) == 0) {
1387 iommu_detected = 1;
1388 amd_iommu_detected = 1;
1389 #ifdef CONFIG_GART_IOMMU
1390 gart_iommu_aperture_disabled = 1;
1391 gart_iommu_aperture = 0;
1392 #endif
1393 }
1394 }
1395
1396 /****************************************************************************
1397 *
1398 * Parsing functions for the AMD IOMMU specific kernel command line
1399 * options.
1400 *
1401 ****************************************************************************/
1402
1403 static int __init parse_amd_iommu_dump(char *str)
1404 {
1405 amd_iommu_dump = true;
1406
1407 return 1;
1408 }
1409
1410 static int __init parse_amd_iommu_options(char *str)
1411 {
1412 for (; *str; ++str) {
1413 if (strncmp(str, "isolate", 7) == 0)
1414 amd_iommu_isolate = true;
1415 if (strncmp(str, "share", 5) == 0)
1416 amd_iommu_isolate = false;
1417 if (strncmp(str, "fullflush", 9) == 0)
1418 amd_iommu_unmap_flush = true;
1419 }
1420
1421 return 1;
1422 }
1423
1424 __setup("amd_iommu_dump", parse_amd_iommu_dump);
1425 __setup("amd_iommu=", parse_amd_iommu_options);
Linux ARM platform port for MOXA ART SoC