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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / arch / x86 / kernel / cpu / intel_cacheinfo.c
blob417990f04b5d2e66cd5d06efd35b8fc5d4a3ffd1
1 /*
2 * Routines to indentify caches on Intel CPU.
3 *
4 * Changes:
5 * Venkatesh Pallipadi : Adding cache identification through cpuid(4)
6 * Ashok Raj <ashok.raj@intel.com>: Work with CPU hotplug infrastructure.
7 * Andi Kleen / Andreas Herrmann : CPUID4 emulation on AMD.
8 */
9
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/device.h>
13 #include <linux/compiler.h>
14 #include <linux/cpu.h>
15 #include <linux/sched.h>
16 #include <linux/pci.h>
17
18 #include <asm/processor.h>
19 #include <linux/smp.h>
20 #include <asm/k8.h>
21 #include <asm/smp.h>
22
23 #define LVL_1_INST 1
24 #define LVL_1_DATA 2
25 #define LVL_2 3
26 #define LVL_3 4
27 #define LVL_TRACE 5
28
29 struct _cache_table {
30 unsigned char descriptor;
31 char cache_type;
32 short size;
33 };
34
35 /* All the cache descriptor types we care about (no TLB or
36 trace cache entries) */
37
38 static const struct _cache_table __cpuinitconst cache_table[] =
39 {
40 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
41 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
42 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
43 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
44 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
45 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
46 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
47 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
48 { 0x23, LVL_3, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
49 { 0x25, LVL_3, 2048 }, /* 8-way set assoc, sectored cache, 64 byte line size */
50 { 0x29, LVL_3, 4096 }, /* 8-way set assoc, sectored cache, 64 byte line size */
51 { 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
52 { 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
53 { 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
54 { 0x3a, LVL_2, 192 }, /* 6-way set assoc, sectored cache, 64 byte line size */
55 { 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
56 { 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
57 { 0x3d, LVL_2, 384 }, /* 6-way set assoc, sectored cache, 64 byte line size */
58 { 0x3e, LVL_2, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
59 { 0x3f, LVL_2, 256 }, /* 2-way set assoc, 64 byte line size */
60 { 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
61 { 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
62 { 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
63 { 0x44, LVL_2, 1024 }, /* 4-way set assoc, 32 byte line size */
64 { 0x45, LVL_2, 2048 }, /* 4-way set assoc, 32 byte line size */
65 { 0x46, LVL_3, 4096 }, /* 4-way set assoc, 64 byte line size */
66 { 0x47, LVL_3, 8192 }, /* 8-way set assoc, 64 byte line size */
67 { 0x49, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
68 { 0x4a, LVL_3, 6144 }, /* 12-way set assoc, 64 byte line size */
69 { 0x4b, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
70 { 0x4c, LVL_3, 12288 }, /* 12-way set assoc, 64 byte line size */
71 { 0x4d, LVL_3, 16384 }, /* 16-way set assoc, 64 byte line size */
72 { 0x4e, LVL_2, 6144 }, /* 24-way set assoc, 64 byte line size */
73 { 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
74 { 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
75 { 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
76 { 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
77 { 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
78 { 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
79 { 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
80 { 0x73, LVL_TRACE, 64 }, /* 8-way set assoc */
81 { 0x78, LVL_2, 1024 }, /* 4-way set assoc, 64 byte line size */
82 { 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
83 { 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
84 { 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
85 { 0x7c, LVL_2, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
86 { 0x7d, LVL_2, 2048 }, /* 8-way set assoc, 64 byte line size */
87 { 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
88 { 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
89 { 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
90 { 0x84, LVL_2, 1024 }, /* 8-way set assoc, 32 byte line size */
91 { 0x85, LVL_2, 2048 }, /* 8-way set assoc, 32 byte line size */
92 { 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
93 { 0x87, LVL_2, 1024 }, /* 8-way set assoc, 64 byte line size */
94 { 0xd0, LVL_3, 512 }, /* 4-way set assoc, 64 byte line size */
95 { 0xd1, LVL_3, 1024 }, /* 4-way set assoc, 64 byte line size */
96 { 0xd2, LVL_3, 2048 }, /* 4-way set assoc, 64 byte line size */
97 { 0xd6, LVL_3, 1024 }, /* 8-way set assoc, 64 byte line size */
98 { 0xd7, LVL_3, 2048 }, /* 8-way set assoc, 64 byte line size */
99 { 0xd8, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */
100 { 0xdc, LVL_3, 2048 }, /* 12-way set assoc, 64 byte line size */
101 { 0xdd, LVL_3, 4096 }, /* 12-way set assoc, 64 byte line size */
102 { 0xde, LVL_3, 8192 }, /* 12-way set assoc, 64 byte line size */
103 { 0xe2, LVL_3, 2048 }, /* 16-way set assoc, 64 byte line size */
104 { 0xe3, LVL_3, 4096 }, /* 16-way set assoc, 64 byte line size */
105 { 0xe4, LVL_3, 8192 }, /* 16-way set assoc, 64 byte line size */
106 { 0xea, LVL_3, 12288 }, /* 24-way set assoc, 64 byte line size */
107 { 0xeb, LVL_3, 18432 }, /* 24-way set assoc, 64 byte line size */
108 { 0xec, LVL_3, 24576 }, /* 24-way set assoc, 64 byte line size */
109 { 0x00, 0, 0}
110 };
111
112
113 enum _cache_type {
114 CACHE_TYPE_NULL = 0,
115 CACHE_TYPE_DATA = 1,
116 CACHE_TYPE_INST = 2,
117 CACHE_TYPE_UNIFIED = 3
118 };
119
120 union _cpuid4_leaf_eax {
121 struct {
122 enum _cache_type type:5;
123 unsigned int level:3;
124 unsigned int is_self_initializing:1;
125 unsigned int is_fully_associative:1;
126 unsigned int reserved:4;
127 unsigned int num_threads_sharing:12;
128 unsigned int num_cores_on_die:6;
129 } split;
130 u32 full;
131 };
132
133 union _cpuid4_leaf_ebx {
134 struct {
135 unsigned int coherency_line_size:12;
136 unsigned int physical_line_partition:10;
137 unsigned int ways_of_associativity:10;
138 } split;
139 u32 full;
140 };
141
142 union _cpuid4_leaf_ecx {
143 struct {
144 unsigned int number_of_sets:32;
145 } split;
146 u32 full;
147 };
148
149 struct _cpuid4_info {
150 union _cpuid4_leaf_eax eax;
151 union _cpuid4_leaf_ebx ebx;
152 union _cpuid4_leaf_ecx ecx;
153 unsigned long size;
154 bool can_disable;
155 unsigned int l3_indices;
156 DECLARE_BITMAP(shared_cpu_map, NR_CPUS);
157 };
158
159 /* subset of above _cpuid4_info w/o shared_cpu_map */
160 struct _cpuid4_info_regs {
161 union _cpuid4_leaf_eax eax;
162 union _cpuid4_leaf_ebx ebx;
163 union _cpuid4_leaf_ecx ecx;
164 unsigned long size;
165 bool can_disable;
166 unsigned int l3_indices;
167 };
168
169 unsigned short num_cache_leaves;
170
171 /* AMD doesn't have CPUID4. Emulate it here to report the same
172 information to the user. This makes some assumptions about the machine:
173 L2 not shared, no SMT etc. that is currently true on AMD CPUs.
174
175 In theory the TLBs could be reported as fake type (they are in "dummy").
176 Maybe later */
177 union l1_cache {
178 struct {
179 unsigned line_size:8;
180 unsigned lines_per_tag:8;
181 unsigned assoc:8;
182 unsigned size_in_kb:8;
183 };
184 unsigned val;
185 };
186
187 union l2_cache {
188 struct {
189 unsigned line_size:8;
190 unsigned lines_per_tag:4;
191 unsigned assoc:4;
192 unsigned size_in_kb:16;
193 };
194 unsigned val;
195 };
196
197 union l3_cache {
198 struct {
199 unsigned line_size:8;
200 unsigned lines_per_tag:4;
201 unsigned assoc:4;
202 unsigned res:2;
203 unsigned size_encoded:14;
204 };
205 unsigned val;
206 };
207
208 static const unsigned short __cpuinitconst assocs[] = {
209 [1] = 1,
210 [2] = 2,
211 [4] = 4,
212 [6] = 8,
213 [8] = 16,
214 [0xa] = 32,
215 [0xb] = 48,
216 [0xc] = 64,
217 [0xd] = 96,
218 [0xe] = 128,
219 [0xf] = 0xffff /* fully associative - no way to show this currently */
220 };
221
222 static const unsigned char __cpuinitconst levels[] = { 1, 1, 2, 3 };
223 static const unsigned char __cpuinitconst types[] = { 1, 2, 3, 3 };
224
225 static void __cpuinit
226 amd_cpuid4(int leaf, union _cpuid4_leaf_eax *eax,
227 union _cpuid4_leaf_ebx *ebx,
228 union _cpuid4_leaf_ecx *ecx)
229 {
230 unsigned dummy;
231 unsigned line_size, lines_per_tag, assoc, size_in_kb;
232 union l1_cache l1i, l1d;
233 union l2_cache l2;
234 union l3_cache l3;
235 union l1_cache *l1 = &l1d;
236
237 eax->full = 0;
238 ebx->full = 0;
239 ecx->full = 0;
240
241 cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val);
242 cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val);
243
244 switch (leaf) {
245 case 1:
246 l1 = &l1i;
247 case 0:
248 if (!l1->val)
249 return;
250 assoc = assocs[l1->assoc];
251 line_size = l1->line_size;
252 lines_per_tag = l1->lines_per_tag;
253 size_in_kb = l1->size_in_kb;
254 break;
255 case 2:
256 if (!l2.val)
257 return;
258 assoc = assocs[l2.assoc];
259 line_size = l2.line_size;
260 lines_per_tag = l2.lines_per_tag;
261 /* cpu_data has errata corrections for K7 applied */
262 size_in_kb = current_cpu_data.x86_cache_size;
263 break;
264 case 3:
265 if (!l3.val)
266 return;
267 assoc = assocs[l3.assoc];
268 line_size = l3.line_size;
269 lines_per_tag = l3.lines_per_tag;
270 size_in_kb = l3.size_encoded * 512;
271 if (boot_cpu_has(X86_FEATURE_AMD_DCM)) {
272 size_in_kb = size_in_kb >> 1;
273 assoc = assoc >> 1;
274 }
275 break;
276 default:
277 return;
278 }
279
280 eax->split.is_self_initializing = 1;
281 eax->split.type = types[leaf];
282 eax->split.level = levels[leaf];
283 eax->split.num_threads_sharing = 0;
284 eax->split.num_cores_on_die = current_cpu_data.x86_max_cores - 1;
285
286
287 if (assoc == 0xffff)
288 eax->split.is_fully_associative = 1;
289 ebx->split.coherency_line_size = line_size - 1;
290 ebx->split.ways_of_associativity = assoc - 1;
291 ebx->split.physical_line_partition = lines_per_tag - 1;
292 ecx->split.number_of_sets = (size_in_kb * 1024) / line_size /
293 (ebx->split.ways_of_associativity + 1) - 1;
294 }
295
296 struct _cache_attr {
297 struct attribute attr;
298 ssize_t (*show)(struct _cpuid4_info *, char *);
299 ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
300 };
301
302 #ifdef CONFIG_CPU_SUP_AMD
303 static unsigned int __cpuinit amd_calc_l3_indices(void)
304 {
305 /*
306 * We're called over smp_call_function_single() and therefore
307 * are on the correct cpu.
308 */
309 int cpu = smp_processor_id();
310 int node = cpu_to_node(cpu);
311 struct pci_dev *dev = node_to_k8_nb_misc(node);
312 unsigned int sc0, sc1, sc2, sc3;
313 u32 val = 0;
314
315 pci_read_config_dword(dev, 0x1C4, &val);
316
317 /* calculate subcache sizes */
318 sc0 = !(val & BIT(0));
319 sc1 = !(val & BIT(4));
320 sc2 = !(val & BIT(8)) + !(val & BIT(9));
321 sc3 = !(val & BIT(12)) + !(val & BIT(13));
322
323 return (max(max(max(sc0, sc1), sc2), sc3) << 10) - 1;
324 }
325
326 static void __cpuinit
327 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
328 {
329 if (index < 3)
330 return;
331
332 if (boot_cpu_data.x86 == 0x11)
333 return;
334
335 /* see errata #382 and #388 */
336 if ((boot_cpu_data.x86 == 0x10) &&
337 ((boot_cpu_data.x86_model < 0x8) ||
338 (boot_cpu_data.x86_mask < 0x1)))
339 return;
340
341 /* not in virtualized environments */
342 if (num_k8_northbridges == 0)
343 return;
344
345 this_leaf->can_disable = true;
346 this_leaf->l3_indices = amd_calc_l3_indices();
347 }
348
349 static ssize_t show_cache_disable(struct _cpuid4_info *this_leaf, char *buf,
350 unsigned int index)
351 {
352 int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
353 int node = amd_get_nb_id(cpu);
354 struct pci_dev *dev = node_to_k8_nb_misc(node);
355 unsigned int reg = 0;
356
357 if (!this_leaf->can_disable)
358 return -EINVAL;
359
360 if (!dev)
361 return -EINVAL;
362
363 pci_read_config_dword(dev, 0x1BC + index * 4, &reg);
364 return sprintf(buf, "0x%08x\n", reg);
365 }
366
367 #define SHOW_CACHE_DISABLE(index) \
368 static ssize_t \
369 show_cache_disable_##index(struct _cpuid4_info *this_leaf, char *buf) \
370 { \
371 return show_cache_disable(this_leaf, buf, index); \
372 }
373 SHOW_CACHE_DISABLE(0)
374 SHOW_CACHE_DISABLE(1)
375
376 static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
377 const char *buf, size_t count, unsigned int index)
378 {
379 int cpu = cpumask_first(to_cpumask(this_leaf->shared_cpu_map));
380 int node = amd_get_nb_id(cpu);
381 struct pci_dev *dev = node_to_k8_nb_misc(node);
382 unsigned long val = 0;
383
384 #define SUBCACHE_MASK (3UL << 20)
385 #define SUBCACHE_INDEX 0xfff
386
387 if (!this_leaf->can_disable)
388 return -EINVAL;
389
390 if (!capable(CAP_SYS_ADMIN))
391 return -EPERM;
392
393 if (!dev)
394 return -EINVAL;
395
396 if (strict_strtoul(buf, 10, &val) < 0)
397 return -EINVAL;
398
399 /* do not allow writes outside of allowed bits */
400 if ((val & ~(SUBCACHE_MASK | SUBCACHE_INDEX)) ||
401 ((val & SUBCACHE_INDEX) > this_leaf->l3_indices))
402 return -EINVAL;
403
404 val |= BIT(30);
405 pci_write_config_dword(dev, 0x1BC + index * 4, val);
406 /*
407 * We need to WBINVD on a core on the node containing the L3 cache which
408 * indices we disable therefore a simple wbinvd() is not sufficient.
409 */
410 wbinvd_on_cpu(cpu);
411 pci_write_config_dword(dev, 0x1BC + index * 4, val | BIT(31));
412 return count;
413 }
414
415 #define STORE_CACHE_DISABLE(index) \
416 static ssize_t \
417 store_cache_disable_##index(struct _cpuid4_info *this_leaf, \
418 const char *buf, size_t count) \
419 { \
420 return store_cache_disable(this_leaf, buf, count, index); \
421 }
422 STORE_CACHE_DISABLE(0)
423 STORE_CACHE_DISABLE(1)
424
425 static struct _cache_attr cache_disable_0 = __ATTR(cache_disable_0, 0644,
426 show_cache_disable_0, store_cache_disable_0);
427 static struct _cache_attr cache_disable_1 = __ATTR(cache_disable_1, 0644,
428 show_cache_disable_1, store_cache_disable_1);
429
430 #else /* CONFIG_CPU_SUP_AMD */
431 static void __cpuinit
432 amd_check_l3_disable(int index, struct _cpuid4_info_regs *this_leaf)
433 {
434 };
435 #endif /* CONFIG_CPU_SUP_AMD */
436
437 static int
438 __cpuinit cpuid4_cache_lookup_regs(int index,
439 struct _cpuid4_info_regs *this_leaf)
440 {
441 union _cpuid4_leaf_eax eax;
442 union _cpuid4_leaf_ebx ebx;
443 union _cpuid4_leaf_ecx ecx;
444 unsigned edx;
445
446 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {
447 amd_cpuid4(index, &eax, &ebx, &ecx);
448 if (boot_cpu_data.x86 >= 0x10)
449 amd_check_l3_disable(index, this_leaf);
450 } else {
451 cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &edx);
452 }
453
454 if (eax.split.type == CACHE_TYPE_NULL)
455 return -EIO; /* better error ? */
456
457 this_leaf->eax = eax;
458 this_leaf->ebx = ebx;
459 this_leaf->ecx = ecx;
460 this_leaf->size = (ecx.split.number_of_sets + 1) *
461 (ebx.split.coherency_line_size + 1) *
462 (ebx.split.physical_line_partition + 1) *
463 (ebx.split.ways_of_associativity + 1);
464 return 0;
465 }
466
467 static int __cpuinit find_num_cache_leaves(void)
468 {
469 unsigned int eax, ebx, ecx, edx;
470 union _cpuid4_leaf_eax cache_eax;
471 int i = -1;
472
473 do {
474 ++i;
475 /* Do cpuid(4) loop to find out num_cache_leaves */
476 cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
477 cache_eax.full = eax;
478 } while (cache_eax.split.type != CACHE_TYPE_NULL);
479 return i;
480 }
481
482 unsigned int __cpuinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
483 {
484 /* Cache sizes */
485 unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0;
486 unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
487 unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
488 unsigned int l2_id = 0, l3_id = 0, num_threads_sharing, index_msb;
489 #ifdef CONFIG_X86_HT
490 unsigned int cpu = c->cpu_index;
491 #endif
492
493 if (c->cpuid_level > 3) {
494 static int is_initialized;
495
496 if (is_initialized == 0) {
497 /* Init num_cache_leaves from boot CPU */
498 num_cache_leaves = find_num_cache_leaves();
499 is_initialized++;
500 }
501
502 /*
503 * Whenever possible use cpuid(4), deterministic cache
504 * parameters cpuid leaf to find the cache details
505 */
506 for (i = 0; i < num_cache_leaves; i++) {
507 struct _cpuid4_info_regs this_leaf;
508 int retval;
509
510 retval = cpuid4_cache_lookup_regs(i, &this_leaf);
511 if (retval >= 0) {
512 switch (this_leaf.eax.split.level) {
513 case 1:
514 if (this_leaf.eax.split.type ==
515 CACHE_TYPE_DATA)
516 new_l1d = this_leaf.size/1024;
517 else if (this_leaf.eax.split.type ==
518 CACHE_TYPE_INST)
519 new_l1i = this_leaf.size/1024;
520 break;
521 case 2:
522 new_l2 = this_leaf.size/1024;
523 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
524 index_msb = get_count_order(num_threads_sharing);
525 l2_id = c->apicid >> index_msb;
526 break;
527 case 3:
528 new_l3 = this_leaf.size/1024;
529 num_threads_sharing = 1 + this_leaf.eax.split.num_threads_sharing;
530 index_msb = get_count_order(
531 num_threads_sharing);
532 l3_id = c->apicid >> index_msb;
533 break;
534 default:
535 break;
536 }
537 }
538 }
539 }
540 /*
541 * Don't use cpuid2 if cpuid4 is supported. For P4, we use cpuid2 for
542 * trace cache
543 */
544 if ((num_cache_leaves == 0 || c->x86 == 15) && c->cpuid_level > 1) {
545 /* supports eax=2 call */
546 int j, n;
547 unsigned int regs[4];
548 unsigned char *dp = (unsigned char *)regs;
549 int only_trace = 0;
550
551 if (num_cache_leaves != 0 && c->x86 == 15)
552 only_trace = 1;
553
554 /* Number of times to iterate */
555 n = cpuid_eax(2) & 0xFF;
556
557 for (i = 0 ; i < n ; i++) {
558 cpuid(2, &regs[0], &regs[1], &regs[2], &regs[3]);
559
560 /* If bit 31 is set, this is an unknown format */
561 for (j = 0 ; j < 3 ; j++)
562 if (regs[j] & (1 << 31))
563 regs[j] = 0;
564
565 /* Byte 0 is level count, not a descriptor */
566 for (j = 1 ; j < 16 ; j++) {
567 unsigned char des = dp[j];
568 unsigned char k = 0;
569
570 /* look up this descriptor in the table */
571 while (cache_table[k].descriptor != 0) {
572 if (cache_table[k].descriptor == des) {
573 if (only_trace && cache_table[k].cache_type != LVL_TRACE)
574 break;
575 switch (cache_table[k].cache_type) {
576 case LVL_1_INST:
577 l1i += cache_table[k].size;
578 break;
579 case LVL_1_DATA:
580 l1d += cache_table[k].size;
581 break;
582 case LVL_2:
583 l2 += cache_table[k].size;
584 break;
585 case LVL_3:
586 l3 += cache_table[k].size;
587 break;
588 case LVL_TRACE:
589 trace += cache_table[k].size;
590 break;
591 }
592
593 break;
594 }
595
596 k++;
597 }
598 }
599 }
600 }
601
602 if (new_l1d)
603 l1d = new_l1d;
604
605 if (new_l1i)
606 l1i = new_l1i;
607
608 if (new_l2) {
609 l2 = new_l2;
610 #ifdef CONFIG_X86_HT
611 per_cpu(cpu_llc_id, cpu) = l2_id;
612 #endif
613 }
614
615 if (new_l3) {
616 l3 = new_l3;
617 #ifdef CONFIG_X86_HT
618 per_cpu(cpu_llc_id, cpu) = l3_id;
619 #endif
620 }
621
622 if (trace)
623 printk(KERN_INFO "CPU: Trace cache: %dK uops", trace);
624 else if (l1i)
625 printk(KERN_INFO "CPU: L1 I cache: %dK", l1i);
626
627 if (l1d)
628 printk(KERN_CONT ", L1 D cache: %dK\n", l1d);
629 else
630 printk(KERN_CONT "\n");
631
632 if (l2)
633 printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
634
635 if (l3)
636 printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
637
638 c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
639
640 return l2;
641 }
642
643 #ifdef CONFIG_SYSFS
644
645 /* pointer to _cpuid4_info array (for each cache leaf) */
646 static DEFINE_PER_CPU(struct _cpuid4_info *, cpuid4_info);
647 #define CPUID4_INFO_IDX(x, y) (&((per_cpu(cpuid4_info, x))[y]))
648
649 #ifdef CONFIG_SMP
650 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
651 {
652 struct _cpuid4_info *this_leaf, *sibling_leaf;
653 unsigned long num_threads_sharing;
654 int index_msb, i, sibling;
655 struct cpuinfo_x86 *c = &cpu_data(cpu);
656
657 if ((index == 3) && (c->x86_vendor == X86_VENDOR_AMD)) {
658 for_each_cpu(i, c->llc_shared_map) {
659 if (!per_cpu(cpuid4_info, i))
660 continue;
661 this_leaf = CPUID4_INFO_IDX(i, index);
662 for_each_cpu(sibling, c->llc_shared_map) {
663 if (!cpu_online(sibling))
664 continue;
665 set_bit(sibling, this_leaf->shared_cpu_map);
666 }
667 }
668 return;
669 }
670 this_leaf = CPUID4_INFO_IDX(cpu, index);
671 num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
672
673 if (num_threads_sharing == 1)
674 cpumask_set_cpu(cpu, to_cpumask(this_leaf->shared_cpu_map));
675 else {
676 index_msb = get_count_order(num_threads_sharing);
677
678 for_each_online_cpu(i) {
679 if (cpu_data(i).apicid >> index_msb ==
680 c->apicid >> index_msb) {
681 cpumask_set_cpu(i,
682 to_cpumask(this_leaf->shared_cpu_map));
683 if (i != cpu && per_cpu(cpuid4_info, i)) {
684 sibling_leaf =
685 CPUID4_INFO_IDX(i, index);
686 cpumask_set_cpu(cpu, to_cpumask(
687 sibling_leaf->shared_cpu_map));
688 }
689 }
690 }
691 }
692 }
693 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
694 {
695 struct _cpuid4_info *this_leaf, *sibling_leaf;
696 int sibling;
697
698 this_leaf = CPUID4_INFO_IDX(cpu, index);
699 for_each_cpu(sibling, to_cpumask(this_leaf->shared_cpu_map)) {
700 sibling_leaf = CPUID4_INFO_IDX(sibling, index);
701 cpumask_clear_cpu(cpu,
702 to_cpumask(sibling_leaf->shared_cpu_map));
703 }
704 }
705 #else
706 static void __cpuinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
707 {
708 }
709
710 static void __cpuinit cache_remove_shared_cpu_map(unsigned int cpu, int index)
711 {
712 }
713 #endif
714
715 static void __cpuinit free_cache_attributes(unsigned int cpu)
716 {
717 int i;
718
719 for (i = 0; i < num_cache_leaves; i++)
720 cache_remove_shared_cpu_map(cpu, i);
721
722 kfree(per_cpu(cpuid4_info, cpu));
723 per_cpu(cpuid4_info, cpu) = NULL;
724 }
725
726 static int
727 __cpuinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
728 {
729 struct _cpuid4_info_regs *leaf_regs =
730 (struct _cpuid4_info_regs *)this_leaf;
731
732 return cpuid4_cache_lookup_regs(index, leaf_regs);
733 }
734
735 static void __cpuinit get_cpu_leaves(void *_retval)
736 {
737 int j, *retval = _retval, cpu = smp_processor_id();
738
739 /* Do cpuid and store the results */
740 for (j = 0; j < num_cache_leaves; j++) {
741 struct _cpuid4_info *this_leaf;
742 this_leaf = CPUID4_INFO_IDX(cpu, j);
743 *retval = cpuid4_cache_lookup(j, this_leaf);
744 if (unlikely(*retval < 0)) {
745 int i;
746
747 for (i = 0; i < j; i++)
748 cache_remove_shared_cpu_map(cpu, i);
749 break;
750 }
751 cache_shared_cpu_map_setup(cpu, j);
752 }
753 }
754
755 static int __cpuinit detect_cache_attributes(unsigned int cpu)
756 {
757 int retval;
758
759 if (num_cache_leaves == 0)
760 return -ENOENT;
761
762 per_cpu(cpuid4_info, cpu) = kzalloc(
763 sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
764 if (per_cpu(cpuid4_info, cpu) == NULL)
765 return -ENOMEM;
766
767 smp_call_function_single(cpu, get_cpu_leaves, &retval, true);
768 if (retval) {
769 kfree(per_cpu(cpuid4_info, cpu));
770 per_cpu(cpuid4_info, cpu) = NULL;
771 }
772
773 return retval;
774 }
775
776 #include <linux/kobject.h>
777 #include <linux/sysfs.h>
778
779 extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
780
781 /* pointer to kobject for cpuX/cache */
782 static DEFINE_PER_CPU(struct kobject *, cache_kobject);
783
784 struct _index_kobject {
785 struct kobject kobj;
786 unsigned int cpu;
787 unsigned short index;
788 };
789
790 /* pointer to array of kobjects for cpuX/cache/indexY */
791 static DEFINE_PER_CPU(struct _index_kobject *, index_kobject);
792 #define INDEX_KOBJECT_PTR(x, y) (&((per_cpu(index_kobject, x))[y]))
793
794 #define show_one_plus(file_name, object, val) \
795 static ssize_t show_##file_name \
796 (struct _cpuid4_info *this_leaf, char *buf) \
797 { \
798 return sprintf(buf, "%lu\n", (unsigned long)this_leaf->object + val); \
799 }
800
801 show_one_plus(level, eax.split.level, 0);
802 show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
803 show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
804 show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
805 show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
806
807 static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
808 {
809 return sprintf(buf, "%luK\n", this_leaf->size / 1024);
810 }
811
812 static ssize_t show_shared_cpu_map_func(struct _cpuid4_info *this_leaf,
813 int type, char *buf)
814 {
815 ptrdiff_t len = PTR_ALIGN(buf + PAGE_SIZE - 1, PAGE_SIZE) - buf;
816 int n = 0;
817
818 if (len > 1) {
819 const struct cpumask *mask;
820
821 mask = to_cpumask(this_leaf->shared_cpu_map);
822 n = type ?
823 cpulist_scnprintf(buf, len-2, mask) :
824 cpumask_scnprintf(buf, len-2, mask);
825 buf[n++] = '\n';
826 buf[n] = '\0';
827 }
828 return n;
829 }
830
831 static inline ssize_t show_shared_cpu_map(struct _cpuid4_info *leaf, char *buf)
832 {
833 return show_shared_cpu_map_func(leaf, 0, buf);
834 }
835
836 static inline ssize_t show_shared_cpu_list(struct _cpuid4_info *leaf, char *buf)
837 {
838 return show_shared_cpu_map_func(leaf, 1, buf);
839 }
840
841 static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf)
842 {
843 switch (this_leaf->eax.split.type) {
844 case CACHE_TYPE_DATA:
845 return sprintf(buf, "Data\n");
846 case CACHE_TYPE_INST:
847 return sprintf(buf, "Instruction\n");
848 case CACHE_TYPE_UNIFIED:
849 return sprintf(buf, "Unified\n");
850 default:
851 return sprintf(buf, "Unknown\n");
852 }
853 }
854
855 #define to_object(k) container_of(k, struct _index_kobject, kobj)
856 #define to_attr(a) container_of(a, struct _cache_attr, attr)
857
858 #define define_one_ro(_name) \
859 static struct _cache_attr _name = \
860 __ATTR(_name, 0444, show_##_name, NULL)
861
862 define_one_ro(level);
863 define_one_ro(type);
864 define_one_ro(coherency_line_size);
865 define_one_ro(physical_line_partition);
866 define_one_ro(ways_of_associativity);
867 define_one_ro(number_of_sets);
868 define_one_ro(size);
869 define_one_ro(shared_cpu_map);
870 define_one_ro(shared_cpu_list);
871
872 #define DEFAULT_SYSFS_CACHE_ATTRS \
873 &type.attr, \
874 &level.attr, \
875 &coherency_line_size.attr, \
876 &physical_line_partition.attr, \
877 &ways_of_associativity.attr, \
878 &number_of_sets.attr, \
879 &size.attr, \
880 &shared_cpu_map.attr, \
881 &shared_cpu_list.attr
882
883 static struct attribute *default_attrs[] = {
884 DEFAULT_SYSFS_CACHE_ATTRS,
885 NULL
886 };
887
888 static struct attribute *default_l3_attrs[] = {
889 DEFAULT_SYSFS_CACHE_ATTRS,
890 #ifdef CONFIG_CPU_SUP_AMD
891 &cache_disable_0.attr,
892 &cache_disable_1.attr,
893 #endif
894 NULL
895 };
896
897 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
898 {
899 struct _cache_attr *fattr = to_attr(attr);
900 struct _index_kobject *this_leaf = to_object(kobj);
901 ssize_t ret;
902
903 ret = fattr->show ?
904 fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
905 buf) :
906 0;
907 return ret;
908 }
909
910 static ssize_t store(struct kobject *kobj, struct attribute *attr,
911 const char *buf, size_t count)
912 {
913 struct _cache_attr *fattr = to_attr(attr);
914 struct _index_kobject *this_leaf = to_object(kobj);
915 ssize_t ret;
916
917 ret = fattr->store ?
918 fattr->store(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
919 buf, count) :
920 0;
921 return ret;
922 }
923
924 static struct sysfs_ops sysfs_ops = {
925 .show = show,
926 .store = store,
927 };
928
929 static struct kobj_type ktype_cache = {
930 .sysfs_ops = &sysfs_ops,
931 .default_attrs = default_attrs,
932 };
933
934 static struct kobj_type ktype_percpu_entry = {
935 .sysfs_ops = &sysfs_ops,
936 };
937
938 static void __cpuinit cpuid4_cache_sysfs_exit(unsigned int cpu)
939 {
940 kfree(per_cpu(cache_kobject, cpu));
941 kfree(per_cpu(index_kobject, cpu));
942 per_cpu(cache_kobject, cpu) = NULL;
943 per_cpu(index_kobject, cpu) = NULL;
944 free_cache_attributes(cpu);
945 }
946
947 static int __cpuinit cpuid4_cache_sysfs_init(unsigned int cpu)
948 {
949 int err;
950
951 if (num_cache_leaves == 0)
952 return -ENOENT;
953
954 err = detect_cache_attributes(cpu);
955 if (err)
956 return err;
957
958 /* Allocate all required memory */
959 per_cpu(cache_kobject, cpu) =
960 kzalloc(sizeof(struct kobject), GFP_KERNEL);
961 if (unlikely(per_cpu(cache_kobject, cpu) == NULL))
962 goto err_out;
963
964 per_cpu(index_kobject, cpu) = kzalloc(
965 sizeof(struct _index_kobject) * num_cache_leaves, GFP_KERNEL);
966 if (unlikely(per_cpu(index_kobject, cpu) == NULL))
967 goto err_out;
968
969 return 0;
970
971 err_out:
972 cpuid4_cache_sysfs_exit(cpu);
973 return -ENOMEM;
974 }
975
976 static DECLARE_BITMAP(cache_dev_map, NR_CPUS);
977
978 /* Add/Remove cache interface for CPU device */
979 static int __cpuinit cache_add_dev(struct sys_device * sys_dev)
980 {
981 unsigned int cpu = sys_dev->id;
982 unsigned long i, j;
983 struct _index_kobject *this_object;
984 struct _cpuid4_info *this_leaf;
985 int retval;
986
987 retval = cpuid4_cache_sysfs_init(cpu);
988 if (unlikely(retval < 0))
989 return retval;
990
991 retval = kobject_init_and_add(per_cpu(cache_kobject, cpu),
992 &ktype_percpu_entry,
993 &sys_dev->kobj, "%s", "cache");
994 if (retval < 0) {
995 cpuid4_cache_sysfs_exit(cpu);
996 return retval;
997 }
998
999 for (i = 0; i < num_cache_leaves; i++) {
1000 this_object = INDEX_KOBJECT_PTR(cpu, i);
1001 this_object->cpu = cpu;
1002 this_object->index = i;
1003
1004 this_leaf = CPUID4_INFO_IDX(cpu, i);
1005
1006 if (this_leaf->can_disable)
1007 ktype_cache.default_attrs = default_l3_attrs;
1008 else
1009 ktype_cache.default_attrs = default_attrs;
1010
1011 retval = kobject_init_and_add(&(this_object->kobj),
1012 &ktype_cache,
1013 per_cpu(cache_kobject, cpu),
1014 "index%1lu", i);
1015 if (unlikely(retval)) {
1016 for (j = 0; j < i; j++)
1017 kobject_put(&(INDEX_KOBJECT_PTR(cpu, j)->kobj));
1018 kobject_put(per_cpu(cache_kobject, cpu));
1019 cpuid4_cache_sysfs_exit(cpu);
1020 return retval;
1021 }
1022 kobject_uevent(&(this_object->kobj), KOBJ_ADD);
1023 }
1024 cpumask_set_cpu(cpu, to_cpumask(cache_dev_map));
1025
1026 kobject_uevent(per_cpu(cache_kobject, cpu), KOBJ_ADD);
1027 return 0;
1028 }
1029
1030 static void __cpuinit cache_remove_dev(struct sys_device * sys_dev)
1031 {
1032 unsigned int cpu = sys_dev->id;
1033 unsigned long i;
1034
1035 if (per_cpu(cpuid4_info, cpu) == NULL)
1036 return;
1037 if (!cpumask_test_cpu(cpu, to_cpumask(cache_dev_map)))
1038 return;
1039 cpumask_clear_cpu(cpu, to_cpumask(cache_dev_map));
1040
1041 for (i = 0; i < num_cache_leaves; i++)
1042 kobject_put(&(INDEX_KOBJECT_PTR(cpu, i)->kobj));
1043 kobject_put(per_cpu(cache_kobject, cpu));
1044 cpuid4_cache_sysfs_exit(cpu);
1045 }
1046
1047 static int __cpuinit cacheinfo_cpu_callback(struct notifier_block *nfb,
1048 unsigned long action, void *hcpu)
1049 {
1050 unsigned int cpu = (unsigned long)hcpu;
1051 struct sys_device *sys_dev;
1052
1053 sys_dev = get_cpu_sysdev(cpu);
1054 switch (action) {
1055 case CPU_ONLINE:
1056 case CPU_ONLINE_FROZEN:
1057 cache_add_dev(sys_dev);
1058 break;
1059 case CPU_DEAD:
1060 case CPU_DEAD_FROZEN:
1061 cache_remove_dev(sys_dev);
1062 break;
1063 }
1064 return NOTIFY_OK;
1065 }
1066
1067 static struct notifier_block __cpuinitdata cacheinfo_cpu_notifier = {
1068 .notifier_call = cacheinfo_cpu_callback,
1069 };
1070
1071 static int __cpuinit cache_sysfs_init(void)
1072 {
1073 int i;
1074
1075 if (num_cache_leaves == 0)
1076 return 0;
1077
1078 for_each_online_cpu(i) {
1079 int err;
1080 struct sys_device *sys_dev = get_cpu_sysdev(i);
1081
1082 err = cache_add_dev(sys_dev);
1083 if (err)
1084 return err;
1085 }
1086 register_hotcpu_notifier(&cacheinfo_cpu_notifier);
1087 return 0;
1088 }
1089
1090 device_initcall(cache_sysfs_init);
1091
1092 #endif
Linux ARM platform port for MOXA ART SoC