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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / arch / x86 / kvm / mmu.c
blobfdf2e28f3bc6080b0a219039bb6472c8c8ee2d70
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 *
11 * Authors:
12 * Yaniv Kamay <yaniv@qumranet.com>
13 * Avi Kivity <avi@qumranet.com>
14 *
15 * This work is licensed under the terms of the GNU GPL, version 2. See
16 * the COPYING file in the top-level directory.
17 *
18 */
19
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22
23 #include <linux/kvm_host.h>
24 #include <linux/types.h>
25 #include <linux/string.h>
26 #include <linux/mm.h>
27 #include <linux/highmem.h>
28 #include <linux/module.h>
29 #include <linux/swap.h>
30 #include <linux/hugetlb.h>
31 #include <linux/compiler.h>
32
33 #include <asm/page.h>
34 #include <asm/cmpxchg.h>
35 #include <asm/io.h>
36 #include <asm/vmx.h>
37
38 /*
39 * When setting this variable to true it enables Two-Dimensional-Paging
40 * where the hardware walks 2 page tables:
41 * 1. the guest-virtual to guest-physical
42 * 2. while doing 1. it walks guest-physical to host-physical
43 * If the hardware supports that we don't need to do shadow paging.
44 */
45 bool tdp_enabled = false;
46
47 #undef MMU_DEBUG
48
49 #undef AUDIT
50
51 #ifdef AUDIT
52 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg);
53 #else
54 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg) {}
55 #endif
56
57 #ifdef MMU_DEBUG
58
59 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
60 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
61
62 #else
63
64 #define pgprintk(x...) do { } while (0)
65 #define rmap_printk(x...) do { } while (0)
66
67 #endif
68
69 #if defined(MMU_DEBUG) || defined(AUDIT)
70 static int dbg = 0;
71 module_param(dbg, bool, 0644);
72 #endif
73
74 static int oos_shadow = 1;
75 module_param(oos_shadow, bool, 0644);
76
77 #ifndef MMU_DEBUG
78 #define ASSERT(x) do { } while (0)
79 #else
80 #define ASSERT(x) \
81 if (!(x)) { \
82 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
83 __FILE__, __LINE__, #x); \
84 }
85 #endif
86
87 #define PT_FIRST_AVAIL_BITS_SHIFT 9
88 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
89
90 #define VALID_PAGE(x) ((x) != INVALID_PAGE)
91
92 #define PT64_LEVEL_BITS 9
93
94 #define PT64_LEVEL_SHIFT(level) \
95 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
96
97 #define PT64_LEVEL_MASK(level) \
98 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
99
100 #define PT64_INDEX(address, level)\
101 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
102
103
104 #define PT32_LEVEL_BITS 10
105
106 #define PT32_LEVEL_SHIFT(level) \
107 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
108
109 #define PT32_LEVEL_MASK(level) \
110 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
111 #define PT32_LVL_OFFSET_MASK(level) \
112 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
113 * PT32_LEVEL_BITS))) - 1))
114
115 #define PT32_INDEX(address, level)\
116 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
117
118
119 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
120 #define PT64_DIR_BASE_ADDR_MASK \
121 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
122 #define PT64_LVL_ADDR_MASK(level) \
123 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT64_LEVEL_BITS))) - 1))
125 #define PT64_LVL_OFFSET_MASK(level) \
126 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
127 * PT64_LEVEL_BITS))) - 1))
128
129 #define PT32_BASE_ADDR_MASK PAGE_MASK
130 #define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
132 #define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
135
136 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
137 | PT64_NX_MASK)
138
139 #define PT_PDPE_LEVEL 3
140 #define PT_DIRECTORY_LEVEL 2
141 #define PT_PAGE_TABLE_LEVEL 1
142
143 #define RMAP_EXT 4
144
145 #define ACC_EXEC_MASK 1
146 #define ACC_WRITE_MASK PT_WRITABLE_MASK
147 #define ACC_USER_MASK PT_USER_MASK
148 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
149
150 #define CREATE_TRACE_POINTS
151 #include "mmutrace.h"
152
153 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
154
155 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
156
157 struct kvm_rmap_desc {
158 u64 *sptes[RMAP_EXT];
159 struct kvm_rmap_desc *more;
160 };
161
162 struct kvm_shadow_walk_iterator {
163 u64 addr;
164 hpa_t shadow_addr;
165 int level;
166 u64 *sptep;
167 unsigned index;
168 };
169
170 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
171 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
172 shadow_walk_okay(&(_walker)); \
173 shadow_walk_next(&(_walker)))
174
175
176 struct kvm_unsync_walk {
177 int (*entry) (struct kvm_mmu_page *sp, struct kvm_unsync_walk *walk);
178 };
179
180 typedef int (*mmu_parent_walk_fn) (struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp);
181
182 static struct kmem_cache *pte_chain_cache;
183 static struct kmem_cache *rmap_desc_cache;
184 static struct kmem_cache *mmu_page_header_cache;
185
186 static u64 __read_mostly shadow_trap_nonpresent_pte;
187 static u64 __read_mostly shadow_notrap_nonpresent_pte;
188 static u64 __read_mostly shadow_base_present_pte;
189 static u64 __read_mostly shadow_nx_mask;
190 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
191 static u64 __read_mostly shadow_user_mask;
192 static u64 __read_mostly shadow_accessed_mask;
193 static u64 __read_mostly shadow_dirty_mask;
194
195 static inline u64 rsvd_bits(int s, int e)
196 {
197 return ((1ULL << (e - s + 1)) - 1) << s;
198 }
199
200 void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
201 {
202 shadow_trap_nonpresent_pte = trap_pte;
203 shadow_notrap_nonpresent_pte = notrap_pte;
204 }
205 EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
206
207 void kvm_mmu_set_base_ptes(u64 base_pte)
208 {
209 shadow_base_present_pte = base_pte;
210 }
211 EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
212
213 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
214 u64 dirty_mask, u64 nx_mask, u64 x_mask)
215 {
216 shadow_user_mask = user_mask;
217 shadow_accessed_mask = accessed_mask;
218 shadow_dirty_mask = dirty_mask;
219 shadow_nx_mask = nx_mask;
220 shadow_x_mask = x_mask;
221 }
222 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
223
224 static bool is_write_protection(struct kvm_vcpu *vcpu)
225 {
226 return vcpu->arch.cr0 & X86_CR0_WP;
227 }
228
229 static int is_cpuid_PSE36(void)
230 {
231 return 1;
232 }
233
234 static int is_nx(struct kvm_vcpu *vcpu)
235 {
236 return vcpu->arch.shadow_efer & EFER_NX;
237 }
238
239 static int is_shadow_present_pte(u64 pte)
240 {
241 return pte != shadow_trap_nonpresent_pte
242 && pte != shadow_notrap_nonpresent_pte;
243 }
244
245 static int is_large_pte(u64 pte)
246 {
247 return pte & PT_PAGE_SIZE_MASK;
248 }
249
250 static int is_writeble_pte(unsigned long pte)
251 {
252 return pte & PT_WRITABLE_MASK;
253 }
254
255 static int is_dirty_gpte(unsigned long pte)
256 {
257 return pte & PT_DIRTY_MASK;
258 }
259
260 static int is_rmap_spte(u64 pte)
261 {
262 return is_shadow_present_pte(pte);
263 }
264
265 static int is_last_spte(u64 pte, int level)
266 {
267 if (level == PT_PAGE_TABLE_LEVEL)
268 return 1;
269 if (is_large_pte(pte))
270 return 1;
271 return 0;
272 }
273
274 static pfn_t spte_to_pfn(u64 pte)
275 {
276 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
277 }
278
279 static gfn_t pse36_gfn_delta(u32 gpte)
280 {
281 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
282
283 return (gpte & PT32_DIR_PSE36_MASK) << shift;
284 }
285
286 static void __set_spte(u64 *sptep, u64 spte)
287 {
288 #ifdef CONFIG_X86_64
289 set_64bit((unsigned long *)sptep, spte);
290 #else
291 set_64bit((unsigned long long *)sptep, spte);
292 #endif
293 }
294
295 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
296 struct kmem_cache *base_cache, int min)
297 {
298 void *obj;
299
300 if (cache->nobjs >= min)
301 return 0;
302 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
303 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
304 if (!obj)
305 return -ENOMEM;
306 cache->objects[cache->nobjs++] = obj;
307 }
308 return 0;
309 }
310
311 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc)
312 {
313 while (mc->nobjs)
314 kfree(mc->objects[--mc->nobjs]);
315 }
316
317 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
318 int min)
319 {
320 struct page *page;
321
322 if (cache->nobjs >= min)
323 return 0;
324 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
325 page = alloc_page(GFP_KERNEL);
326 if (!page)
327 return -ENOMEM;
328 set_page_private(page, 0);
329 cache->objects[cache->nobjs++] = page_address(page);
330 }
331 return 0;
332 }
333
334 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
335 {
336 while (mc->nobjs)
337 free_page((unsigned long)mc->objects[--mc->nobjs]);
338 }
339
340 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
341 {
342 int r;
343
344 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
345 pte_chain_cache, 4);
346 if (r)
347 goto out;
348 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
349 rmap_desc_cache, 4);
350 if (r)
351 goto out;
352 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
353 if (r)
354 goto out;
355 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
356 mmu_page_header_cache, 4);
357 out:
358 return r;
359 }
360
361 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
362 {
363 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache);
364 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache);
365 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
366 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
367 }
368
369 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
370 size_t size)
371 {
372 void *p;
373
374 BUG_ON(!mc->nobjs);
375 p = mc->objects[--mc->nobjs];
376 return p;
377 }
378
379 static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
380 {
381 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
382 sizeof(struct kvm_pte_chain));
383 }
384
385 static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
386 {
387 kfree(pc);
388 }
389
390 static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
391 {
392 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
393 sizeof(struct kvm_rmap_desc));
394 }
395
396 static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
397 {
398 kfree(rd);
399 }
400
401 /*
402 * Return the pointer to the largepage write count for a given
403 * gfn, handling slots that are not large page aligned.
404 */
405 static int *slot_largepage_idx(gfn_t gfn,
406 struct kvm_memory_slot *slot,
407 int level)
408 {
409 unsigned long idx;
410
411 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
412 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
413 return &slot->lpage_info[level - 2][idx].write_count;
414 }
415
416 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
417 {
418 struct kvm_memory_slot *slot;
419 int *write_count;
420 int i;
421
422 gfn = unalias_gfn(kvm, gfn);
423
424 slot = gfn_to_memslot_unaliased(kvm, gfn);
425 for (i = PT_DIRECTORY_LEVEL;
426 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
427 write_count = slot_largepage_idx(gfn, slot, i);
428 *write_count += 1;
429 }
430 }
431
432 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
433 {
434 struct kvm_memory_slot *slot;
435 int *write_count;
436 int i;
437
438 gfn = unalias_gfn(kvm, gfn);
439 for (i = PT_DIRECTORY_LEVEL;
440 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
441 slot = gfn_to_memslot_unaliased(kvm, gfn);
442 write_count = slot_largepage_idx(gfn, slot, i);
443 *write_count -= 1;
444 WARN_ON(*write_count < 0);
445 }
446 }
447
448 static int has_wrprotected_page(struct kvm *kvm,
449 gfn_t gfn,
450 int level)
451 {
452 struct kvm_memory_slot *slot;
453 int *largepage_idx;
454
455 gfn = unalias_gfn(kvm, gfn);
456 slot = gfn_to_memslot_unaliased(kvm, gfn);
457 if (slot) {
458 largepage_idx = slot_largepage_idx(gfn, slot, level);
459 return *largepage_idx;
460 }
461
462 return 1;
463 }
464
465 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
466 {
467 unsigned long page_size = PAGE_SIZE;
468 struct vm_area_struct *vma;
469 unsigned long addr;
470 int i, ret = 0;
471
472 addr = gfn_to_hva(kvm, gfn);
473 if (kvm_is_error_hva(addr))
474 return PT_PAGE_TABLE_LEVEL;
475
476 down_read(&current->mm->mmap_sem);
477 vma = find_vma(current->mm, addr);
478 if (!vma)
479 goto out;
480
481 page_size = vma_kernel_pagesize(vma);
482
483 out:
484 up_read(&current->mm->mmap_sem);
485
486 for (i = PT_PAGE_TABLE_LEVEL;
487 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
488 if (page_size >= KVM_HPAGE_SIZE(i))
489 ret = i;
490 else
491 break;
492 }
493
494 return ret;
495 }
496
497 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
498 {
499 struct kvm_memory_slot *slot;
500 int host_level;
501 int level = PT_PAGE_TABLE_LEVEL;
502
503 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
504 if (slot && slot->dirty_bitmap)
505 return PT_PAGE_TABLE_LEVEL;
506
507 host_level = host_mapping_level(vcpu->kvm, large_gfn);
508
509 if (host_level == PT_PAGE_TABLE_LEVEL)
510 return host_level;
511
512 for (level = PT_DIRECTORY_LEVEL; level <= host_level; ++level)
513 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
514 break;
515
516 return level - 1;
517 }
518
519 /*
520 * Take gfn and return the reverse mapping to it.
521 * Note: gfn must be unaliased before this function get called
522 */
523
524 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
525 {
526 struct kvm_memory_slot *slot;
527 unsigned long idx;
528
529 slot = gfn_to_memslot(kvm, gfn);
530 if (likely(level == PT_PAGE_TABLE_LEVEL))
531 return &slot->rmap[gfn - slot->base_gfn];
532
533 idx = (gfn / KVM_PAGES_PER_HPAGE(level)) -
534 (slot->base_gfn / KVM_PAGES_PER_HPAGE(level));
535
536 return &slot->lpage_info[level - 2][idx].rmap_pde;
537 }
538
539 /*
540 * Reverse mapping data structures:
541 *
542 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
543 * that points to page_address(page).
544 *
545 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
546 * containing more mappings.
547 *
548 * Returns the number of rmap entries before the spte was added or zero if
549 * the spte was not added.
550 *
551 */
552 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
553 {
554 struct kvm_mmu_page *sp;
555 struct kvm_rmap_desc *desc;
556 unsigned long *rmapp;
557 int i, count = 0;
558
559 if (!is_rmap_spte(*spte))
560 return count;
561 gfn = unalias_gfn(vcpu->kvm, gfn);
562 sp = page_header(__pa(spte));
563 sp->gfns[spte - sp->spt] = gfn;
564 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
565 if (!*rmapp) {
566 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
567 *rmapp = (unsigned long)spte;
568 } else if (!(*rmapp & 1)) {
569 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
570 desc = mmu_alloc_rmap_desc(vcpu);
571 desc->sptes[0] = (u64 *)*rmapp;
572 desc->sptes[1] = spte;
573 *rmapp = (unsigned long)desc | 1;
574 } else {
575 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
576 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
577 while (desc->sptes[RMAP_EXT-1] && desc->more) {
578 desc = desc->more;
579 count += RMAP_EXT;
580 }
581 if (desc->sptes[RMAP_EXT-1]) {
582 desc->more = mmu_alloc_rmap_desc(vcpu);
583 desc = desc->more;
584 }
585 for (i = 0; desc->sptes[i]; ++i)
586 ;
587 desc->sptes[i] = spte;
588 }
589 return count;
590 }
591
592 static void rmap_desc_remove_entry(unsigned long *rmapp,
593 struct kvm_rmap_desc *desc,
594 int i,
595 struct kvm_rmap_desc *prev_desc)
596 {
597 int j;
598
599 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
600 ;
601 desc->sptes[i] = desc->sptes[j];
602 desc->sptes[j] = NULL;
603 if (j != 0)
604 return;
605 if (!prev_desc && !desc->more)
606 *rmapp = (unsigned long)desc->sptes[0];
607 else
608 if (prev_desc)
609 prev_desc->more = desc->more;
610 else
611 *rmapp = (unsigned long)desc->more | 1;
612 mmu_free_rmap_desc(desc);
613 }
614
615 static void rmap_remove(struct kvm *kvm, u64 *spte)
616 {
617 struct kvm_rmap_desc *desc;
618 struct kvm_rmap_desc *prev_desc;
619 struct kvm_mmu_page *sp;
620 pfn_t pfn;
621 unsigned long *rmapp;
622 int i;
623
624 if (!is_rmap_spte(*spte))
625 return;
626 sp = page_header(__pa(spte));
627 pfn = spte_to_pfn(*spte);
628 if (*spte & shadow_accessed_mask)
629 kvm_set_pfn_accessed(pfn);
630 if (is_writeble_pte(*spte))
631 kvm_set_pfn_dirty(pfn);
632 rmapp = gfn_to_rmap(kvm, sp->gfns[spte - sp->spt], sp->role.level);
633 if (!*rmapp) {
634 printk(KERN_ERR "rmap_remove: %p %llx 0->BUG\n", spte, *spte);
635 BUG();
636 } else if (!(*rmapp & 1)) {
637 rmap_printk("rmap_remove: %p %llx 1->0\n", spte, *spte);
638 if ((u64 *)*rmapp != spte) {
639 printk(KERN_ERR "rmap_remove: %p %llx 1->BUG\n",
640 spte, *spte);
641 BUG();
642 }
643 *rmapp = 0;
644 } else {
645 rmap_printk("rmap_remove: %p %llx many->many\n", spte, *spte);
646 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
647 prev_desc = NULL;
648 while (desc) {
649 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
650 if (desc->sptes[i] == spte) {
651 rmap_desc_remove_entry(rmapp,
652 desc, i,
653 prev_desc);
654 return;
655 }
656 prev_desc = desc;
657 desc = desc->more;
658 }
659 BUG();
660 }
661 }
662
663 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
664 {
665 struct kvm_rmap_desc *desc;
666 struct kvm_rmap_desc *prev_desc;
667 u64 *prev_spte;
668 int i;
669
670 if (!*rmapp)
671 return NULL;
672 else if (!(*rmapp & 1)) {
673 if (!spte)
674 return (u64 *)*rmapp;
675 return NULL;
676 }
677 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
678 prev_desc = NULL;
679 prev_spte = NULL;
680 while (desc) {
681 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
682 if (prev_spte == spte)
683 return desc->sptes[i];
684 prev_spte = desc->sptes[i];
685 }
686 desc = desc->more;
687 }
688 return NULL;
689 }
690
691 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
692 {
693 unsigned long *rmapp;
694 u64 *spte;
695 int i, write_protected = 0;
696
697 gfn = unalias_gfn(kvm, gfn);
698 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
699
700 spte = rmap_next(kvm, rmapp, NULL);
701 while (spte) {
702 BUG_ON(!spte);
703 BUG_ON(!(*spte & PT_PRESENT_MASK));
704 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
705 if (is_writeble_pte(*spte)) {
706 __set_spte(spte, *spte & ~PT_WRITABLE_MASK);
707 write_protected = 1;
708 }
709 spte = rmap_next(kvm, rmapp, spte);
710 }
711 if (write_protected) {
712 pfn_t pfn;
713
714 spte = rmap_next(kvm, rmapp, NULL);
715 pfn = spte_to_pfn(*spte);
716 kvm_set_pfn_dirty(pfn);
717 }
718
719 /* check for huge page mappings */
720 for (i = PT_DIRECTORY_LEVEL;
721 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
722 rmapp = gfn_to_rmap(kvm, gfn, i);
723 spte = rmap_next(kvm, rmapp, NULL);
724 while (spte) {
725 BUG_ON(!spte);
726 BUG_ON(!(*spte & PT_PRESENT_MASK));
727 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
728 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
729 if (is_writeble_pte(*spte)) {
730 rmap_remove(kvm, spte);
731 --kvm->stat.lpages;
732 __set_spte(spte, shadow_trap_nonpresent_pte);
733 spte = NULL;
734 write_protected = 1;
735 }
736 spte = rmap_next(kvm, rmapp, spte);
737 }
738 }
739
740 return write_protected;
741 }
742
743 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
744 unsigned long data)
745 {
746 u64 *spte;
747 int need_tlb_flush = 0;
748
749 while ((spte = rmap_next(kvm, rmapp, NULL))) {
750 BUG_ON(!(*spte & PT_PRESENT_MASK));
751 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
752 rmap_remove(kvm, spte);
753 __set_spte(spte, shadow_trap_nonpresent_pte);
754 need_tlb_flush = 1;
755 }
756 return need_tlb_flush;
757 }
758
759 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
760 unsigned long data)
761 {
762 int need_flush = 0;
763 u64 *spte, new_spte;
764 pte_t *ptep = (pte_t *)data;
765 pfn_t new_pfn;
766
767 WARN_ON(pte_huge(*ptep));
768 new_pfn = pte_pfn(*ptep);
769 spte = rmap_next(kvm, rmapp, NULL);
770 while (spte) {
771 BUG_ON(!is_shadow_present_pte(*spte));
772 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
773 need_flush = 1;
774 if (pte_write(*ptep)) {
775 rmap_remove(kvm, spte);
776 __set_spte(spte, shadow_trap_nonpresent_pte);
777 spte = rmap_next(kvm, rmapp, NULL);
778 } else {
779 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
780 new_spte |= (u64)new_pfn << PAGE_SHIFT;
781
782 new_spte &= ~PT_WRITABLE_MASK;
783 new_spte &= ~SPTE_HOST_WRITEABLE;
784 if (is_writeble_pte(*spte))
785 kvm_set_pfn_dirty(spte_to_pfn(*spte));
786 __set_spte(spte, new_spte);
787 spte = rmap_next(kvm, rmapp, spte);
788 }
789 }
790 if (need_flush)
791 kvm_flush_remote_tlbs(kvm);
792
793 return 0;
794 }
795
796 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
797 unsigned long data,
798 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
799 unsigned long data))
800 {
801 int i, j;
802 int retval = 0;
803
804 /*
805 * If mmap_sem isn't taken, we can look the memslots with only
806 * the mmu_lock by skipping over the slots with userspace_addr == 0.
807 */
808 for (i = 0; i < kvm->nmemslots; i++) {
809 struct kvm_memory_slot *memslot = &kvm->memslots[i];
810 unsigned long start = memslot->userspace_addr;
811 unsigned long end;
812
813 /* mmu_lock protects userspace_addr */
814 if (!start)
815 continue;
816
817 end = start + (memslot->npages << PAGE_SHIFT);
818 if (hva >= start && hva < end) {
819 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
820
821 retval |= handler(kvm, &memslot->rmap[gfn_offset],
822 data);
823
824 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
825 int idx = gfn_offset;
826 idx /= KVM_PAGES_PER_HPAGE(PT_DIRECTORY_LEVEL + j);
827 retval |= handler(kvm,
828 &memslot->lpage_info[j][idx].rmap_pde,
829 data);
830 }
831 }
832 }
833
834 return retval;
835 }
836
837 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
838 {
839 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
840 }
841
842 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
843 {
844 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
845 }
846
847 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
848 unsigned long data)
849 {
850 u64 *spte;
851 int young = 0;
852
853 /* always return old for EPT */
854 if (!shadow_accessed_mask)
855 return 0;
856
857 spte = rmap_next(kvm, rmapp, NULL);
858 while (spte) {
859 int _young;
860 u64 _spte = *spte;
861 BUG_ON(!(_spte & PT_PRESENT_MASK));
862 _young = _spte & PT_ACCESSED_MASK;
863 if (_young) {
864 young = 1;
865 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
866 }
867 spte = rmap_next(kvm, rmapp, spte);
868 }
869 return young;
870 }
871
872 #define RMAP_RECYCLE_THRESHOLD 1000
873
874 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
875 {
876 unsigned long *rmapp;
877 struct kvm_mmu_page *sp;
878
879 sp = page_header(__pa(spte));
880
881 gfn = unalias_gfn(vcpu->kvm, gfn);
882 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
883
884 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
885 kvm_flush_remote_tlbs(vcpu->kvm);
886 }
887
888 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
889 {
890 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
891 }
892
893 #ifdef MMU_DEBUG
894 static int is_empty_shadow_page(u64 *spt)
895 {
896 u64 *pos;
897 u64 *end;
898
899 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
900 if (is_shadow_present_pte(*pos)) {
901 printk(KERN_ERR "%s: %p %llx\n", __func__,
902 pos, *pos);
903 return 0;
904 }
905 return 1;
906 }
907 #endif
908
909 static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
910 {
911 ASSERT(is_empty_shadow_page(sp->spt));
912 list_del(&sp->link);
913 __free_page(virt_to_page(sp->spt));
914 __free_page(virt_to_page(sp->gfns));
915 kfree(sp);
916 ++kvm->arch.n_free_mmu_pages;
917 }
918
919 static unsigned kvm_page_table_hashfn(gfn_t gfn)
920 {
921 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
922 }
923
924 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
925 u64 *parent_pte)
926 {
927 struct kvm_mmu_page *sp;
928
929 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
930 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
931 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
932 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
933 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
934 INIT_LIST_HEAD(&sp->oos_link);
935 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
936 sp->multimapped = 0;
937 sp->parent_pte = parent_pte;
938 --vcpu->kvm->arch.n_free_mmu_pages;
939 return sp;
940 }
941
942 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
943 struct kvm_mmu_page *sp, u64 *parent_pte)
944 {
945 struct kvm_pte_chain *pte_chain;
946 struct hlist_node *node;
947 int i;
948
949 if (!parent_pte)
950 return;
951 if (!sp->multimapped) {
952 u64 *old = sp->parent_pte;
953
954 if (!old) {
955 sp->parent_pte = parent_pte;
956 return;
957 }
958 sp->multimapped = 1;
959 pte_chain = mmu_alloc_pte_chain(vcpu);
960 INIT_HLIST_HEAD(&sp->parent_ptes);
961 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
962 pte_chain->parent_ptes[0] = old;
963 }
964 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
965 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
966 continue;
967 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
968 if (!pte_chain->parent_ptes[i]) {
969 pte_chain->parent_ptes[i] = parent_pte;
970 return;
971 }
972 }
973 pte_chain = mmu_alloc_pte_chain(vcpu);
974 BUG_ON(!pte_chain);
975 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
976 pte_chain->parent_ptes[0] = parent_pte;
977 }
978
979 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
980 u64 *parent_pte)
981 {
982 struct kvm_pte_chain *pte_chain;
983 struct hlist_node *node;
984 int i;
985
986 if (!sp->multimapped) {
987 BUG_ON(sp->parent_pte != parent_pte);
988 sp->parent_pte = NULL;
989 return;
990 }
991 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
992 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
993 if (!pte_chain->parent_ptes[i])
994 break;
995 if (pte_chain->parent_ptes[i] != parent_pte)
996 continue;
997 while (i + 1 < NR_PTE_CHAIN_ENTRIES
998 && pte_chain->parent_ptes[i + 1]) {
999 pte_chain->parent_ptes[i]
1000 = pte_chain->parent_ptes[i + 1];
1001 ++i;
1002 }
1003 pte_chain->parent_ptes[i] = NULL;
1004 if (i == 0) {
1005 hlist_del(&pte_chain->link);
1006 mmu_free_pte_chain(pte_chain);
1007 if (hlist_empty(&sp->parent_ptes)) {
1008 sp->multimapped = 0;
1009 sp->parent_pte = NULL;
1010 }
1011 }
1012 return;
1013 }
1014 BUG();
1015 }
1016
1017
1018 static void mmu_parent_walk(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1019 mmu_parent_walk_fn fn)
1020 {
1021 struct kvm_pte_chain *pte_chain;
1022 struct hlist_node *node;
1023 struct kvm_mmu_page *parent_sp;
1024 int i;
1025
1026 if (!sp->multimapped && sp->parent_pte) {
1027 parent_sp = page_header(__pa(sp->parent_pte));
1028 fn(vcpu, parent_sp);
1029 mmu_parent_walk(vcpu, parent_sp, fn);
1030 return;
1031 }
1032 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1033 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1034 if (!pte_chain->parent_ptes[i])
1035 break;
1036 parent_sp = page_header(__pa(pte_chain->parent_ptes[i]));
1037 fn(vcpu, parent_sp);
1038 mmu_parent_walk(vcpu, parent_sp, fn);
1039 }
1040 }
1041
1042 static void kvm_mmu_update_unsync_bitmap(u64 *spte)
1043 {
1044 unsigned int index;
1045 struct kvm_mmu_page *sp = page_header(__pa(spte));
1046
1047 index = spte - sp->spt;
1048 if (!__test_and_set_bit(index, sp->unsync_child_bitmap))
1049 sp->unsync_children++;
1050 WARN_ON(!sp->unsync_children);
1051 }
1052
1053 static void kvm_mmu_update_parents_unsync(struct kvm_mmu_page *sp)
1054 {
1055 struct kvm_pte_chain *pte_chain;
1056 struct hlist_node *node;
1057 int i;
1058
1059 if (!sp->parent_pte)
1060 return;
1061
1062 if (!sp->multimapped) {
1063 kvm_mmu_update_unsync_bitmap(sp->parent_pte);
1064 return;
1065 }
1066
1067 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1068 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1069 if (!pte_chain->parent_ptes[i])
1070 break;
1071 kvm_mmu_update_unsync_bitmap(pte_chain->parent_ptes[i]);
1072 }
1073 }
1074
1075 static int unsync_walk_fn(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1076 {
1077 kvm_mmu_update_parents_unsync(sp);
1078 return 1;
1079 }
1080
1081 static void kvm_mmu_mark_parents_unsync(struct kvm_vcpu *vcpu,
1082 struct kvm_mmu_page *sp)
1083 {
1084 mmu_parent_walk(vcpu, sp, unsync_walk_fn);
1085 kvm_mmu_update_parents_unsync(sp);
1086 }
1087
1088 static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1089 struct kvm_mmu_page *sp)
1090 {
1091 int i;
1092
1093 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1094 sp->spt[i] = shadow_trap_nonpresent_pte;
1095 }
1096
1097 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1098 struct kvm_mmu_page *sp)
1099 {
1100 return 1;
1101 }
1102
1103 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1104 {
1105 }
1106
1107 #define KVM_PAGE_ARRAY_NR 16
1108
1109 struct kvm_mmu_pages {
1110 struct mmu_page_and_offset {
1111 struct kvm_mmu_page *sp;
1112 unsigned int idx;
1113 } page[KVM_PAGE_ARRAY_NR];
1114 unsigned int nr;
1115 };
1116
1117 #define for_each_unsync_children(bitmap, idx) \
1118 for (idx = find_first_bit(bitmap, 512); \
1119 idx < 512; \
1120 idx = find_next_bit(bitmap, 512, idx+1))
1121
1122 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1123 int idx)
1124 {
1125 int i;
1126
1127 if (sp->unsync)
1128 for (i=0; i < pvec->nr; i++)
1129 if (pvec->page[i].sp == sp)
1130 return 0;
1131
1132 pvec->page[pvec->nr].sp = sp;
1133 pvec->page[pvec->nr].idx = idx;
1134 pvec->nr++;
1135 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1136 }
1137
1138 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1139 struct kvm_mmu_pages *pvec)
1140 {
1141 int i, ret, nr_unsync_leaf = 0;
1142
1143 for_each_unsync_children(sp->unsync_child_bitmap, i) {
1144 u64 ent = sp->spt[i];
1145
1146 if (is_shadow_present_pte(ent) && !is_large_pte(ent)) {
1147 struct kvm_mmu_page *child;
1148 child = page_header(ent & PT64_BASE_ADDR_MASK);
1149
1150 if (child->unsync_children) {
1151 if (mmu_pages_add(pvec, child, i))
1152 return -ENOSPC;
1153
1154 ret = __mmu_unsync_walk(child, pvec);
1155 if (!ret)
1156 __clear_bit(i, sp->unsync_child_bitmap);
1157 else if (ret > 0)
1158 nr_unsync_leaf += ret;
1159 else
1160 return ret;
1161 }
1162
1163 if (child->unsync) {
1164 nr_unsync_leaf++;
1165 if (mmu_pages_add(pvec, child, i))
1166 return -ENOSPC;
1167 }
1168 }
1169 }
1170
1171 if (find_first_bit(sp->unsync_child_bitmap, 512) == 512)
1172 sp->unsync_children = 0;
1173
1174 return nr_unsync_leaf;
1175 }
1176
1177 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1178 struct kvm_mmu_pages *pvec)
1179 {
1180 if (!sp->unsync_children)
1181 return 0;
1182
1183 mmu_pages_add(pvec, sp, 0);
1184 return __mmu_unsync_walk(sp, pvec);
1185 }
1186
1187 static struct kvm_mmu_page *kvm_mmu_lookup_page(struct kvm *kvm, gfn_t gfn)
1188 {
1189 unsigned index;
1190 struct hlist_head *bucket;
1191 struct kvm_mmu_page *sp;
1192 struct hlist_node *node;
1193
1194 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1195 index = kvm_page_table_hashfn(gfn);
1196 bucket = &kvm->arch.mmu_page_hash[index];
1197 hlist_for_each_entry(sp, node, bucket, hash_link)
1198 if (sp->gfn == gfn && !sp->role.direct
1199 && !sp->role.invalid) {
1200 pgprintk("%s: found role %x\n",
1201 __func__, sp->role.word);
1202 return sp;
1203 }
1204 return NULL;
1205 }
1206
1207 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1208 {
1209 WARN_ON(!sp->unsync);
1210 sp->unsync = 0;
1211 --kvm->stat.mmu_unsync;
1212 }
1213
1214 static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp);
1215
1216 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1217 {
1218 if (sp->role.glevels != vcpu->arch.mmu.root_level) {
1219 kvm_mmu_zap_page(vcpu->kvm, sp);
1220 return 1;
1221 }
1222
1223 trace_kvm_mmu_sync_page(sp);
1224 if (rmap_write_protect(vcpu->kvm, sp->gfn))
1225 kvm_flush_remote_tlbs(vcpu->kvm);
1226 kvm_unlink_unsync_page(vcpu->kvm, sp);
1227 if (vcpu->arch.mmu.sync_page(vcpu, sp)) {
1228 kvm_mmu_zap_page(vcpu->kvm, sp);
1229 return 1;
1230 }
1231
1232 kvm_mmu_flush_tlb(vcpu);
1233 return 0;
1234 }
1235
1236 struct mmu_page_path {
1237 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1238 unsigned int idx[PT64_ROOT_LEVEL-1];
1239 };
1240
1241 #define for_each_sp(pvec, sp, parents, i) \
1242 for (i = mmu_pages_next(&pvec, &parents, -1), \
1243 sp = pvec.page[i].sp; \
1244 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1245 i = mmu_pages_next(&pvec, &parents, i))
1246
1247 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1248 struct mmu_page_path *parents,
1249 int i)
1250 {
1251 int n;
1252
1253 for (n = i+1; n < pvec->nr; n++) {
1254 struct kvm_mmu_page *sp = pvec->page[n].sp;
1255
1256 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1257 parents->idx[0] = pvec->page[n].idx;
1258 return n;
1259 }
1260
1261 parents->parent[sp->role.level-2] = sp;
1262 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1263 }
1264
1265 return n;
1266 }
1267
1268 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1269 {
1270 struct kvm_mmu_page *sp;
1271 unsigned int level = 0;
1272
1273 do {
1274 unsigned int idx = parents->idx[level];
1275
1276 sp = parents->parent[level];
1277 if (!sp)
1278 return;
1279
1280 --sp->unsync_children;
1281 WARN_ON((int)sp->unsync_children < 0);
1282 __clear_bit(idx, sp->unsync_child_bitmap);
1283 level++;
1284 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1285 }
1286
1287 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1288 struct mmu_page_path *parents,
1289 struct kvm_mmu_pages *pvec)
1290 {
1291 parents->parent[parent->role.level-1] = NULL;
1292 pvec->nr = 0;
1293 }
1294
1295 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1296 struct kvm_mmu_page *parent)
1297 {
1298 int i;
1299 struct kvm_mmu_page *sp;
1300 struct mmu_page_path parents;
1301 struct kvm_mmu_pages pages;
1302
1303 kvm_mmu_pages_init(parent, &parents, &pages);
1304 while (mmu_unsync_walk(parent, &pages)) {
1305 int protected = 0;
1306
1307 for_each_sp(pages, sp, parents, i)
1308 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1309
1310 if (protected)
1311 kvm_flush_remote_tlbs(vcpu->kvm);
1312
1313 for_each_sp(pages, sp, parents, i) {
1314 kvm_sync_page(vcpu, sp);
1315 mmu_pages_clear_parents(&parents);
1316 }
1317 cond_resched_lock(&vcpu->kvm->mmu_lock);
1318 kvm_mmu_pages_init(parent, &parents, &pages);
1319 }
1320 }
1321
1322 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1323 gfn_t gfn,
1324 gva_t gaddr,
1325 unsigned level,
1326 int direct,
1327 unsigned access,
1328 u64 *parent_pte)
1329 {
1330 union kvm_mmu_page_role role;
1331 unsigned index;
1332 unsigned quadrant;
1333 struct hlist_head *bucket;
1334 struct kvm_mmu_page *sp;
1335 struct hlist_node *node, *tmp;
1336
1337 role = vcpu->arch.mmu.base_role;
1338 role.level = level;
1339 role.direct = direct;
1340 role.access = access;
1341 if (vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1342 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1343 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1344 role.quadrant = quadrant;
1345 }
1346 index = kvm_page_table_hashfn(gfn);
1347 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1348 hlist_for_each_entry_safe(sp, node, tmp, bucket, hash_link)
1349 if (sp->gfn == gfn) {
1350 if (sp->unsync)
1351 if (kvm_sync_page(vcpu, sp))
1352 continue;
1353
1354 if (sp->role.word != role.word)
1355 continue;
1356
1357 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1358 if (sp->unsync_children) {
1359 set_bit(KVM_REQ_MMU_SYNC, &vcpu->requests);
1360 kvm_mmu_mark_parents_unsync(vcpu, sp);
1361 }
1362 trace_kvm_mmu_get_page(sp, false);
1363 return sp;
1364 }
1365 ++vcpu->kvm->stat.mmu_cache_miss;
1366 sp = kvm_mmu_alloc_page(vcpu, parent_pte);
1367 if (!sp)
1368 return sp;
1369 sp->gfn = gfn;
1370 sp->role = role;
1371 hlist_add_head(&sp->hash_link, bucket);
1372 if (!direct) {
1373 if (rmap_write_protect(vcpu->kvm, gfn))
1374 kvm_flush_remote_tlbs(vcpu->kvm);
1375 account_shadowed(vcpu->kvm, gfn);
1376 }
1377 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1378 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1379 else
1380 nonpaging_prefetch_page(vcpu, sp);
1381 trace_kvm_mmu_get_page(sp, true);
1382 return sp;
1383 }
1384
1385 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1386 struct kvm_vcpu *vcpu, u64 addr)
1387 {
1388 iterator->addr = addr;
1389 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1390 iterator->level = vcpu->arch.mmu.shadow_root_level;
1391 if (iterator->level == PT32E_ROOT_LEVEL) {
1392 iterator->shadow_addr
1393 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1394 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1395 --iterator->level;
1396 if (!iterator->shadow_addr)
1397 iterator->level = 0;
1398 }
1399 }
1400
1401 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1402 {
1403 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1404 return false;
1405
1406 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1407 if (is_large_pte(*iterator->sptep))
1408 return false;
1409
1410 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1411 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1412 return true;
1413 }
1414
1415 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1416 {
1417 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1418 --iterator->level;
1419 }
1420
1421 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1422 struct kvm_mmu_page *sp)
1423 {
1424 unsigned i;
1425 u64 *pt;
1426 u64 ent;
1427
1428 pt = sp->spt;
1429
1430 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1431 ent = pt[i];
1432
1433 if (is_shadow_present_pte(ent)) {
1434 if (!is_last_spte(ent, sp->role.level)) {
1435 ent &= PT64_BASE_ADDR_MASK;
1436 mmu_page_remove_parent_pte(page_header(ent),
1437 &pt[i]);
1438 } else {
1439 if (is_large_pte(ent))
1440 --kvm->stat.lpages;
1441 rmap_remove(kvm, &pt[i]);
1442 }
1443 }
1444 pt[i] = shadow_trap_nonpresent_pte;
1445 }
1446 }
1447
1448 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1449 {
1450 mmu_page_remove_parent_pte(sp, parent_pte);
1451 }
1452
1453 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1454 {
1455 int i;
1456 struct kvm_vcpu *vcpu;
1457
1458 kvm_for_each_vcpu(i, vcpu, kvm)
1459 vcpu->arch.last_pte_updated = NULL;
1460 }
1461
1462 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1463 {
1464 u64 *parent_pte;
1465
1466 while (sp->multimapped || sp->parent_pte) {
1467 if (!sp->multimapped)
1468 parent_pte = sp->parent_pte;
1469 else {
1470 struct kvm_pte_chain *chain;
1471
1472 chain = container_of(sp->parent_ptes.first,
1473 struct kvm_pte_chain, link);
1474 parent_pte = chain->parent_ptes[0];
1475 }
1476 BUG_ON(!parent_pte);
1477 kvm_mmu_put_page(sp, parent_pte);
1478 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
1479 }
1480 }
1481
1482 static int mmu_zap_unsync_children(struct kvm *kvm,
1483 struct kvm_mmu_page *parent)
1484 {
1485 int i, zapped = 0;
1486 struct mmu_page_path parents;
1487 struct kvm_mmu_pages pages;
1488
1489 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1490 return 0;
1491
1492 kvm_mmu_pages_init(parent, &parents, &pages);
1493 while (mmu_unsync_walk(parent, &pages)) {
1494 struct kvm_mmu_page *sp;
1495
1496 for_each_sp(pages, sp, parents, i) {
1497 kvm_mmu_zap_page(kvm, sp);
1498 mmu_pages_clear_parents(&parents);
1499 zapped++;
1500 }
1501 kvm_mmu_pages_init(parent, &parents, &pages);
1502 }
1503
1504 return zapped;
1505 }
1506
1507 static int kvm_mmu_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1508 {
1509 int ret;
1510
1511 trace_kvm_mmu_zap_page(sp);
1512 ++kvm->stat.mmu_shadow_zapped;
1513 ret = mmu_zap_unsync_children(kvm, sp);
1514 kvm_mmu_page_unlink_children(kvm, sp);
1515 kvm_mmu_unlink_parents(kvm, sp);
1516 kvm_flush_remote_tlbs(kvm);
1517 if (!sp->role.invalid && !sp->role.direct)
1518 unaccount_shadowed(kvm, sp->gfn);
1519 if (sp->unsync)
1520 kvm_unlink_unsync_page(kvm, sp);
1521 if (!sp->root_count) {
1522 hlist_del(&sp->hash_link);
1523 kvm_mmu_free_page(kvm, sp);
1524 } else {
1525 sp->role.invalid = 1;
1526 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1527 kvm_reload_remote_mmus(kvm);
1528 }
1529 kvm_mmu_reset_last_pte_updated(kvm);
1530 return ret;
1531 }
1532
1533 /*
1534 * Changing the number of mmu pages allocated to the vm
1535 * Note: if kvm_nr_mmu_pages is too small, you will get dead lock
1536 */
1537 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int kvm_nr_mmu_pages)
1538 {
1539 int used_pages;
1540
1541 used_pages = kvm->arch.n_alloc_mmu_pages - kvm->arch.n_free_mmu_pages;
1542 used_pages = max(0, used_pages);
1543
1544 /*
1545 * If we set the number of mmu pages to be smaller be than the
1546 * number of actived pages , we must to free some mmu pages before we
1547 * change the value
1548 */
1549
1550 if (used_pages > kvm_nr_mmu_pages) {
1551 while (used_pages > kvm_nr_mmu_pages &&
1552 !list_empty(&kvm->arch.active_mmu_pages)) {
1553 struct kvm_mmu_page *page;
1554
1555 page = container_of(kvm->arch.active_mmu_pages.prev,
1556 struct kvm_mmu_page, link);
1557 used_pages -= kvm_mmu_zap_page(kvm, page);
1558 used_pages--;
1559 }
1560 kvm_nr_mmu_pages = used_pages;
1561 kvm->arch.n_free_mmu_pages = 0;
1562 }
1563 else
1564 kvm->arch.n_free_mmu_pages += kvm_nr_mmu_pages
1565 - kvm->arch.n_alloc_mmu_pages;
1566
1567 kvm->arch.n_alloc_mmu_pages = kvm_nr_mmu_pages;
1568 }
1569
1570 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1571 {
1572 unsigned index;
1573 struct hlist_head *bucket;
1574 struct kvm_mmu_page *sp;
1575 struct hlist_node *node, *n;
1576 int r;
1577
1578 pgprintk("%s: looking for gfn %lx\n", __func__, gfn);
1579 r = 0;
1580 index = kvm_page_table_hashfn(gfn);
1581 bucket = &kvm->arch.mmu_page_hash[index];
1582 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link)
1583 if (sp->gfn == gfn && !sp->role.direct) {
1584 pgprintk("%s: gfn %lx role %x\n", __func__, gfn,
1585 sp->role.word);
1586 r = 1;
1587 if (kvm_mmu_zap_page(kvm, sp))
1588 n = bucket->first;
1589 }
1590 return r;
1591 }
1592
1593 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
1594 {
1595 unsigned index;
1596 struct hlist_head *bucket;
1597 struct kvm_mmu_page *sp;
1598 struct hlist_node *node, *nn;
1599
1600 index = kvm_page_table_hashfn(gfn);
1601 bucket = &kvm->arch.mmu_page_hash[index];
1602 hlist_for_each_entry_safe(sp, node, nn, bucket, hash_link) {
1603 if (sp->gfn == gfn && !sp->role.direct
1604 && !sp->role.invalid) {
1605 pgprintk("%s: zap %lx %x\n",
1606 __func__, gfn, sp->role.word);
1607 if (kvm_mmu_zap_page(kvm, sp))
1608 nn = bucket->first;
1609 }
1610 }
1611 }
1612
1613 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
1614 {
1615 int slot = memslot_id(kvm, gfn_to_memslot(kvm, gfn));
1616 struct kvm_mmu_page *sp = page_header(__pa(pte));
1617
1618 __set_bit(slot, sp->slot_bitmap);
1619 }
1620
1621 static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1622 {
1623 int i;
1624 u64 *pt = sp->spt;
1625
1626 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1627 return;
1628
1629 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1630 if (pt[i] == shadow_notrap_nonpresent_pte)
1631 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
1632 }
1633 }
1634
1635 struct page *gva_to_page(struct kvm_vcpu *vcpu, gva_t gva)
1636 {
1637 struct page *page;
1638
1639 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
1640
1641 if (gpa == UNMAPPED_GVA)
1642 return NULL;
1643
1644 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
1645
1646 return page;
1647 }
1648
1649 /*
1650 * The function is based on mtrr_type_lookup() in
1651 * arch/x86/kernel/cpu/mtrr/generic.c
1652 */
1653 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1654 u64 start, u64 end)
1655 {
1656 int i;
1657 u64 base, mask;
1658 u8 prev_match, curr_match;
1659 int num_var_ranges = KVM_NR_VAR_MTRR;
1660
1661 if (!mtrr_state->enabled)
1662 return 0xFF;
1663
1664 /* Make end inclusive end, instead of exclusive */
1665 end--;
1666
1667 /* Look in fixed ranges. Just return the type as per start */
1668 if (mtrr_state->have_fixed && (start < 0x100000)) {
1669 int idx;
1670
1671 if (start < 0x80000) {
1672 idx = 0;
1673 idx += (start >> 16);
1674 return mtrr_state->fixed_ranges[idx];
1675 } else if (start < 0xC0000) {
1676 idx = 1 * 8;
1677 idx += ((start - 0x80000) >> 14);
1678 return mtrr_state->fixed_ranges[idx];
1679 } else if (start < 0x1000000) {
1680 idx = 3 * 8;
1681 idx += ((start - 0xC0000) >> 12);
1682 return mtrr_state->fixed_ranges[idx];
1683 }
1684 }
1685
1686 /*
1687 * Look in variable ranges
1688 * Look of multiple ranges matching this address and pick type
1689 * as per MTRR precedence
1690 */
1691 if (!(mtrr_state->enabled & 2))
1692 return mtrr_state->def_type;
1693
1694 prev_match = 0xFF;
1695 for (i = 0; i < num_var_ranges; ++i) {
1696 unsigned short start_state, end_state;
1697
1698 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1699 continue;
1700
1701 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1702 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1703 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1704 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1705
1706 start_state = ((start & mask) == (base & mask));
1707 end_state = ((end & mask) == (base & mask));
1708 if (start_state != end_state)
1709 return 0xFE;
1710
1711 if ((start & mask) != (base & mask))
1712 continue;
1713
1714 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1715 if (prev_match == 0xFF) {
1716 prev_match = curr_match;
1717 continue;
1718 }
1719
1720 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1721 curr_match == MTRR_TYPE_UNCACHABLE)
1722 return MTRR_TYPE_UNCACHABLE;
1723
1724 if ((prev_match == MTRR_TYPE_WRBACK &&
1725 curr_match == MTRR_TYPE_WRTHROUGH) ||
1726 (prev_match == MTRR_TYPE_WRTHROUGH &&
1727 curr_match == MTRR_TYPE_WRBACK)) {
1728 prev_match = MTRR_TYPE_WRTHROUGH;
1729 curr_match = MTRR_TYPE_WRTHROUGH;
1730 }
1731
1732 if (prev_match != curr_match)
1733 return MTRR_TYPE_UNCACHABLE;
1734 }
1735
1736 if (prev_match != 0xFF)
1737 return prev_match;
1738
1739 return mtrr_state->def_type;
1740 }
1741
1742 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
1743 {
1744 u8 mtrr;
1745
1746 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1747 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1748 if (mtrr == 0xfe || mtrr == 0xff)
1749 mtrr = MTRR_TYPE_WRBACK;
1750 return mtrr;
1751 }
1752 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
1753
1754 static int kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1755 {
1756 unsigned index;
1757 struct hlist_head *bucket;
1758 struct kvm_mmu_page *s;
1759 struct hlist_node *node, *n;
1760
1761 trace_kvm_mmu_unsync_page(sp);
1762 index = kvm_page_table_hashfn(sp->gfn);
1763 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
1764 /* don't unsync if pagetable is shadowed with multiple roles */
1765 hlist_for_each_entry_safe(s, node, n, bucket, hash_link) {
1766 if (s->gfn != sp->gfn || s->role.direct)
1767 continue;
1768 if (s->role.word != sp->role.word)
1769 return 1;
1770 }
1771 ++vcpu->kvm->stat.mmu_unsync;
1772 sp->unsync = 1;
1773
1774 kvm_mmu_mark_parents_unsync(vcpu, sp);
1775
1776 mmu_convert_notrap(sp);
1777 return 0;
1778 }
1779
1780 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1781 bool can_unsync)
1782 {
1783 struct kvm_mmu_page *shadow;
1784
1785 shadow = kvm_mmu_lookup_page(vcpu->kvm, gfn);
1786 if (shadow) {
1787 if (shadow->role.level != PT_PAGE_TABLE_LEVEL)
1788 return 1;
1789 if (shadow->unsync)
1790 return 0;
1791 if (can_unsync && oos_shadow)
1792 return kvm_unsync_page(vcpu, shadow);
1793 return 1;
1794 }
1795 return 0;
1796 }
1797
1798 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1799 unsigned pte_access, int user_fault,
1800 int write_fault, int dirty, int level,
1801 gfn_t gfn, pfn_t pfn, bool speculative,
1802 bool can_unsync, bool reset_host_protection)
1803 {
1804 u64 spte;
1805 int ret = 0;
1806
1807 /*
1808 * We don't set the accessed bit, since we sometimes want to see
1809 * whether the guest actually used the pte (in order to detect
1810 * demand paging).
1811 */
1812 spte = shadow_base_present_pte | shadow_dirty_mask;
1813 if (!speculative)
1814 spte |= shadow_accessed_mask;
1815 if (!dirty)
1816 pte_access &= ~ACC_WRITE_MASK;
1817 if (pte_access & ACC_EXEC_MASK)
1818 spte |= shadow_x_mask;
1819 else
1820 spte |= shadow_nx_mask;
1821 if (pte_access & ACC_USER_MASK)
1822 spte |= shadow_user_mask;
1823 if (level > PT_PAGE_TABLE_LEVEL)
1824 spte |= PT_PAGE_SIZE_MASK;
1825 if (tdp_enabled)
1826 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1827 kvm_is_mmio_pfn(pfn));
1828
1829 if (reset_host_protection)
1830 spte |= SPTE_HOST_WRITEABLE;
1831
1832 spte |= (u64)pfn << PAGE_SHIFT;
1833
1834 if ((pte_access & ACC_WRITE_MASK)
1835 || (write_fault && !is_write_protection(vcpu) && !user_fault)) {
1836
1837 if (level > PT_PAGE_TABLE_LEVEL &&
1838 has_wrprotected_page(vcpu->kvm, gfn, level)) {
1839 ret = 1;
1840 spte = shadow_trap_nonpresent_pte;
1841 goto set_pte;
1842 }
1843
1844 spte |= PT_WRITABLE_MASK;
1845
1846 if (!tdp_enabled && !(pte_access & ACC_WRITE_MASK))
1847 spte &= ~PT_USER_MASK;
1848
1849 /*
1850 * Optimization: for pte sync, if spte was writable the hash
1851 * lookup is unnecessary (and expensive). Write protection
1852 * is responsibility of mmu_get_page / kvm_sync_page.
1853 * Same reasoning can be applied to dirty page accounting.
1854 */
1855 if (!can_unsync && is_writeble_pte(*sptep))
1856 goto set_pte;
1857
1858 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
1859 pgprintk("%s: found shadow page for %lx, marking ro\n",
1860 __func__, gfn);
1861 ret = 1;
1862 pte_access &= ~ACC_WRITE_MASK;
1863 if (is_writeble_pte(spte))
1864 spte &= ~PT_WRITABLE_MASK;
1865 }
1866 }
1867
1868 if (pte_access & ACC_WRITE_MASK)
1869 mark_page_dirty(vcpu->kvm, gfn);
1870
1871 set_pte:
1872 __set_spte(sptep, spte);
1873 return ret;
1874 }
1875
1876 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1877 unsigned pt_access, unsigned pte_access,
1878 int user_fault, int write_fault, int dirty,
1879 int *ptwrite, int level, gfn_t gfn,
1880 pfn_t pfn, bool speculative,
1881 bool reset_host_protection)
1882 {
1883 int was_rmapped = 0;
1884 int was_writeble = is_writeble_pte(*sptep);
1885 int rmap_count;
1886
1887 pgprintk("%s: spte %llx access %x write_fault %d"
1888 " user_fault %d gfn %lx\n",
1889 __func__, *sptep, pt_access,
1890 write_fault, user_fault, gfn);
1891
1892 if (is_rmap_spte(*sptep)) {
1893 /*
1894 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
1895 * the parent of the now unreachable PTE.
1896 */
1897 if (level > PT_PAGE_TABLE_LEVEL &&
1898 !is_large_pte(*sptep)) {
1899 struct kvm_mmu_page *child;
1900 u64 pte = *sptep;
1901
1902 child = page_header(pte & PT64_BASE_ADDR_MASK);
1903 mmu_page_remove_parent_pte(child, sptep);
1904 __set_spte(sptep, shadow_trap_nonpresent_pte);
1905 kvm_flush_remote_tlbs(vcpu->kvm);
1906 } else if (pfn != spte_to_pfn(*sptep)) {
1907 pgprintk("hfn old %lx new %lx\n",
1908 spte_to_pfn(*sptep), pfn);
1909 rmap_remove(vcpu->kvm, sptep);
1910 } else
1911 was_rmapped = 1;
1912 }
1913
1914 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
1915 dirty, level, gfn, pfn, speculative, true,
1916 reset_host_protection)) {
1917 if (write_fault)
1918 *ptwrite = 1;
1919 kvm_x86_ops->tlb_flush(vcpu);
1920 }
1921
1922 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
1923 pgprintk("instantiating %s PTE (%s) at %ld (%llx) addr %p\n",
1924 is_large_pte(*sptep)? "2MB" : "4kB",
1925 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
1926 *sptep, sptep);
1927 if (!was_rmapped && is_large_pte(*sptep))
1928 ++vcpu->kvm->stat.lpages;
1929
1930 page_header_update_slot(vcpu->kvm, sptep, gfn);
1931 if (!was_rmapped) {
1932 rmap_count = rmap_add(vcpu, sptep, gfn);
1933 kvm_release_pfn_clean(pfn);
1934 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
1935 rmap_recycle(vcpu, sptep, gfn);
1936 } else {
1937 if (was_writeble)
1938 kvm_release_pfn_dirty(pfn);
1939 else
1940 kvm_release_pfn_clean(pfn);
1941 }
1942 if (speculative) {
1943 vcpu->arch.last_pte_updated = sptep;
1944 vcpu->arch.last_pte_gfn = gfn;
1945 }
1946 }
1947
1948 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
1949 {
1950 }
1951
1952 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
1953 int level, gfn_t gfn, pfn_t pfn)
1954 {
1955 struct kvm_shadow_walk_iterator iterator;
1956 struct kvm_mmu_page *sp;
1957 int pt_write = 0;
1958 gfn_t pseudo_gfn;
1959
1960 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
1961 if (iterator.level == level) {
1962 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
1963 0, write, 1, &pt_write,
1964 level, gfn, pfn, false, true);
1965 ++vcpu->stat.pf_fixed;
1966 break;
1967 }
1968
1969 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
1970 pseudo_gfn = (iterator.addr & PT64_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
1971 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
1972 iterator.level - 1,
1973 1, ACC_ALL, iterator.sptep);
1974 if (!sp) {
1975 pgprintk("nonpaging_map: ENOMEM\n");
1976 kvm_release_pfn_clean(pfn);
1977 return -ENOMEM;
1978 }
1979
1980 __set_spte(iterator.sptep,
1981 __pa(sp->spt)
1982 | PT_PRESENT_MASK | PT_WRITABLE_MASK
1983 | shadow_user_mask | shadow_x_mask);
1984 }
1985 }
1986 return pt_write;
1987 }
1988
1989 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
1990 {
1991 int r;
1992 int level;
1993 pfn_t pfn;
1994 unsigned long mmu_seq;
1995
1996 level = mapping_level(vcpu, gfn);
1997
1998 /*
1999 * This path builds a PAE pagetable - so we can map 2mb pages at
2000 * maximum. Therefore check if the level is larger than that.
2001 */
2002 if (level > PT_DIRECTORY_LEVEL)
2003 level = PT_DIRECTORY_LEVEL;
2004
2005 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2006
2007 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2008 smp_rmb();
2009 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2010
2011 /* mmio */
2012 if (is_error_pfn(pfn)) {
2013 kvm_release_pfn_clean(pfn);
2014 return 1;
2015 }
2016
2017 spin_lock(&vcpu->kvm->mmu_lock);
2018 if (mmu_notifier_retry(vcpu, mmu_seq))
2019 goto out_unlock;
2020 kvm_mmu_free_some_pages(vcpu);
2021 r = __direct_map(vcpu, v, write, level, gfn, pfn);
2022 spin_unlock(&vcpu->kvm->mmu_lock);
2023
2024
2025 return r;
2026
2027 out_unlock:
2028 spin_unlock(&vcpu->kvm->mmu_lock);
2029 kvm_release_pfn_clean(pfn);
2030 return 0;
2031 }
2032
2033
2034 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2035 {
2036 int i;
2037 struct kvm_mmu_page *sp;
2038
2039 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2040 return;
2041 spin_lock(&vcpu->kvm->mmu_lock);
2042 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2043 hpa_t root = vcpu->arch.mmu.root_hpa;
2044
2045 sp = page_header(root);
2046 --sp->root_count;
2047 if (!sp->root_count && sp->role.invalid)
2048 kvm_mmu_zap_page(vcpu->kvm, sp);
2049 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2050 spin_unlock(&vcpu->kvm->mmu_lock);
2051 return;
2052 }
2053 for (i = 0; i < 4; ++i) {
2054 hpa_t root = vcpu->arch.mmu.pae_root[i];
2055
2056 if (root) {
2057 root &= PT64_BASE_ADDR_MASK;
2058 sp = page_header(root);
2059 --sp->root_count;
2060 if (!sp->root_count && sp->role.invalid)
2061 kvm_mmu_zap_page(vcpu->kvm, sp);
2062 }
2063 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2064 }
2065 spin_unlock(&vcpu->kvm->mmu_lock);
2066 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2067 }
2068
2069 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2070 {
2071 int ret = 0;
2072
2073 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2074 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
2075 ret = 1;
2076 }
2077
2078 return ret;
2079 }
2080
2081 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2082 {
2083 int i;
2084 gfn_t root_gfn;
2085 struct kvm_mmu_page *sp;
2086 int direct = 0;
2087 u64 pdptr;
2088
2089 root_gfn = vcpu->arch.cr3 >> PAGE_SHIFT;
2090
2091 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2092 hpa_t root = vcpu->arch.mmu.root_hpa;
2093
2094 ASSERT(!VALID_PAGE(root));
2095 if (tdp_enabled)
2096 direct = 1;
2097 if (mmu_check_root(vcpu, root_gfn))
2098 return 1;
2099 spin_lock(&vcpu->kvm->mmu_lock);
2100 sp = kvm_mmu_get_page(vcpu, root_gfn, 0,
2101 PT64_ROOT_LEVEL, direct,
2102 ACC_ALL, NULL);
2103 root = __pa(sp->spt);
2104 ++sp->root_count;
2105 spin_unlock(&vcpu->kvm->mmu_lock);
2106 vcpu->arch.mmu.root_hpa = root;
2107 return 0;
2108 }
2109 direct = !is_paging(vcpu);
2110 if (tdp_enabled)
2111 direct = 1;
2112 for (i = 0; i < 4; ++i) {
2113 hpa_t root = vcpu->arch.mmu.pae_root[i];
2114
2115 ASSERT(!VALID_PAGE(root));
2116 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2117 pdptr = kvm_pdptr_read(vcpu, i);
2118 if (!is_present_gpte(pdptr)) {
2119 vcpu->arch.mmu.pae_root[i] = 0;
2120 continue;
2121 }
2122 root_gfn = pdptr >> PAGE_SHIFT;
2123 } else if (vcpu->arch.mmu.root_level == 0)
2124 root_gfn = 0;
2125 if (mmu_check_root(vcpu, root_gfn))
2126 return 1;
2127 spin_lock(&vcpu->kvm->mmu_lock);
2128 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2129 PT32_ROOT_LEVEL, direct,
2130 ACC_ALL, NULL);
2131 root = __pa(sp->spt);
2132 ++sp->root_count;
2133 spin_unlock(&vcpu->kvm->mmu_lock);
2134
2135 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2136 }
2137 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2138 return 0;
2139 }
2140
2141 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2142 {
2143 int i;
2144 struct kvm_mmu_page *sp;
2145
2146 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2147 return;
2148 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2149 hpa_t root = vcpu->arch.mmu.root_hpa;
2150 sp = page_header(root);
2151 mmu_sync_children(vcpu, sp);
2152 return;
2153 }
2154 for (i = 0; i < 4; ++i) {
2155 hpa_t root = vcpu->arch.mmu.pae_root[i];
2156
2157 if (root && VALID_PAGE(root)) {
2158 root &= PT64_BASE_ADDR_MASK;
2159 sp = page_header(root);
2160 mmu_sync_children(vcpu, sp);
2161 }
2162 }
2163 }
2164
2165 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2166 {
2167 spin_lock(&vcpu->kvm->mmu_lock);
2168 mmu_sync_roots(vcpu);
2169 spin_unlock(&vcpu->kvm->mmu_lock);
2170 }
2171
2172 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2173 u32 access, u32 *error)
2174 {
2175 if (error)
2176 *error = 0;
2177 return vaddr;
2178 }
2179
2180 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2181 u32 error_code)
2182 {
2183 gfn_t gfn;
2184 int r;
2185
2186 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2187 r = mmu_topup_memory_caches(vcpu);
2188 if (r)
2189 return r;
2190
2191 ASSERT(vcpu);
2192 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2193
2194 gfn = gva >> PAGE_SHIFT;
2195
2196 return nonpaging_map(vcpu, gva & PAGE_MASK,
2197 error_code & PFERR_WRITE_MASK, gfn);
2198 }
2199
2200 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2201 u32 error_code)
2202 {
2203 pfn_t pfn;
2204 int r;
2205 int level;
2206 gfn_t gfn = gpa >> PAGE_SHIFT;
2207 unsigned long mmu_seq;
2208
2209 ASSERT(vcpu);
2210 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2211
2212 r = mmu_topup_memory_caches(vcpu);
2213 if (r)
2214 return r;
2215
2216 level = mapping_level(vcpu, gfn);
2217
2218 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2219
2220 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2221 smp_rmb();
2222 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2223 if (is_error_pfn(pfn)) {
2224 kvm_release_pfn_clean(pfn);
2225 return 1;
2226 }
2227 spin_lock(&vcpu->kvm->mmu_lock);
2228 if (mmu_notifier_retry(vcpu, mmu_seq))
2229 goto out_unlock;
2230 kvm_mmu_free_some_pages(vcpu);
2231 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
2232 level, gfn, pfn);
2233 spin_unlock(&vcpu->kvm->mmu_lock);
2234
2235 return r;
2236
2237 out_unlock:
2238 spin_unlock(&vcpu->kvm->mmu_lock);
2239 kvm_release_pfn_clean(pfn);
2240 return 0;
2241 }
2242
2243 static void nonpaging_free(struct kvm_vcpu *vcpu)
2244 {
2245 mmu_free_roots(vcpu);
2246 }
2247
2248 static int nonpaging_init_context(struct kvm_vcpu *vcpu)
2249 {
2250 struct kvm_mmu *context = &vcpu->arch.mmu;
2251
2252 context->new_cr3 = nonpaging_new_cr3;
2253 context->page_fault = nonpaging_page_fault;
2254 context->gva_to_gpa = nonpaging_gva_to_gpa;
2255 context->free = nonpaging_free;
2256 context->prefetch_page = nonpaging_prefetch_page;
2257 context->sync_page = nonpaging_sync_page;
2258 context->invlpg = nonpaging_invlpg;
2259 context->root_level = 0;
2260 context->shadow_root_level = PT32E_ROOT_LEVEL;
2261 context->root_hpa = INVALID_PAGE;
2262 return 0;
2263 }
2264
2265 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
2266 {
2267 ++vcpu->stat.tlb_flush;
2268 kvm_x86_ops->tlb_flush(vcpu);
2269 }
2270
2271 static void paging_new_cr3(struct kvm_vcpu *vcpu)
2272 {
2273 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
2274 mmu_free_roots(vcpu);
2275 }
2276
2277 static void inject_page_fault(struct kvm_vcpu *vcpu,
2278 u64 addr,
2279 u32 err_code)
2280 {
2281 kvm_inject_page_fault(vcpu, addr, err_code);
2282 }
2283
2284 static void paging_free(struct kvm_vcpu *vcpu)
2285 {
2286 nonpaging_free(vcpu);
2287 }
2288
2289 static bool is_rsvd_bits_set(struct kvm_vcpu *vcpu, u64 gpte, int level)
2290 {
2291 int bit7;
2292
2293 bit7 = (gpte >> 7) & 1;
2294 return (gpte & vcpu->arch.mmu.rsvd_bits_mask[bit7][level-1]) != 0;
2295 }
2296
2297 #define PTTYPE 64
2298 #include "paging_tmpl.h"
2299 #undef PTTYPE
2300
2301 #define PTTYPE 32
2302 #include "paging_tmpl.h"
2303 #undef PTTYPE
2304
2305 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, int level)
2306 {
2307 struct kvm_mmu *context = &vcpu->arch.mmu;
2308 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2309 u64 exb_bit_rsvd = 0;
2310
2311 if (!is_nx(vcpu))
2312 exb_bit_rsvd = rsvd_bits(63, 63);
2313 switch (level) {
2314 case PT32_ROOT_LEVEL:
2315 /* no rsvd bits for 2 level 4K page table entries */
2316 context->rsvd_bits_mask[0][1] = 0;
2317 context->rsvd_bits_mask[0][0] = 0;
2318 if (is_cpuid_PSE36())
2319 /* 36bits PSE 4MB page */
2320 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2321 else
2322 /* 32 bits PSE 4MB page */
2323 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
2324 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
2325 break;
2326 case PT32E_ROOT_LEVEL:
2327 context->rsvd_bits_mask[0][2] =
2328 rsvd_bits(maxphyaddr, 63) |
2329 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
2330 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2331 rsvd_bits(maxphyaddr, 62); /* PDE */
2332 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2333 rsvd_bits(maxphyaddr, 62); /* PTE */
2334 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2335 rsvd_bits(maxphyaddr, 62) |
2336 rsvd_bits(13, 20); /* large page */
2337 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
2338 break;
2339 case PT64_ROOT_LEVEL:
2340 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2341 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2342 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2343 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2344 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2345 rsvd_bits(maxphyaddr, 51);
2346 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2347 rsvd_bits(maxphyaddr, 51);
2348 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
2349 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2350 rsvd_bits(maxphyaddr, 51) |
2351 rsvd_bits(13, 29);
2352 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2353 rsvd_bits(maxphyaddr, 51) |
2354 rsvd_bits(13, 20); /* large page */
2355 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[1][0];
2356 break;
2357 }
2358 }
2359
2360 static int paging64_init_context_common(struct kvm_vcpu *vcpu, int level)
2361 {
2362 struct kvm_mmu *context = &vcpu->arch.mmu;
2363
2364 ASSERT(is_pae(vcpu));
2365 context->new_cr3 = paging_new_cr3;
2366 context->page_fault = paging64_page_fault;
2367 context->gva_to_gpa = paging64_gva_to_gpa;
2368 context->prefetch_page = paging64_prefetch_page;
2369 context->sync_page = paging64_sync_page;
2370 context->invlpg = paging64_invlpg;
2371 context->free = paging_free;
2372 context->root_level = level;
2373 context->shadow_root_level = level;
2374 context->root_hpa = INVALID_PAGE;
2375 return 0;
2376 }
2377
2378 static int paging64_init_context(struct kvm_vcpu *vcpu)
2379 {
2380 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
2381 return paging64_init_context_common(vcpu, PT64_ROOT_LEVEL);
2382 }
2383
2384 static int paging32_init_context(struct kvm_vcpu *vcpu)
2385 {
2386 struct kvm_mmu *context = &vcpu->arch.mmu;
2387
2388 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
2389 context->new_cr3 = paging_new_cr3;
2390 context->page_fault = paging32_page_fault;
2391 context->gva_to_gpa = paging32_gva_to_gpa;
2392 context->free = paging_free;
2393 context->prefetch_page = paging32_prefetch_page;
2394 context->sync_page = paging32_sync_page;
2395 context->invlpg = paging32_invlpg;
2396 context->root_level = PT32_ROOT_LEVEL;
2397 context->shadow_root_level = PT32E_ROOT_LEVEL;
2398 context->root_hpa = INVALID_PAGE;
2399 return 0;
2400 }
2401
2402 static int paging32E_init_context(struct kvm_vcpu *vcpu)
2403 {
2404 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
2405 return paging64_init_context_common(vcpu, PT32E_ROOT_LEVEL);
2406 }
2407
2408 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2409 {
2410 struct kvm_mmu *context = &vcpu->arch.mmu;
2411
2412 context->new_cr3 = nonpaging_new_cr3;
2413 context->page_fault = tdp_page_fault;
2414 context->free = nonpaging_free;
2415 context->prefetch_page = nonpaging_prefetch_page;
2416 context->sync_page = nonpaging_sync_page;
2417 context->invlpg = nonpaging_invlpg;
2418 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
2419 context->root_hpa = INVALID_PAGE;
2420
2421 if (!is_paging(vcpu)) {
2422 context->gva_to_gpa = nonpaging_gva_to_gpa;
2423 context->root_level = 0;
2424 } else if (is_long_mode(vcpu)) {
2425 reset_rsvds_bits_mask(vcpu, PT64_ROOT_LEVEL);
2426 context->gva_to_gpa = paging64_gva_to_gpa;
2427 context->root_level = PT64_ROOT_LEVEL;
2428 } else if (is_pae(vcpu)) {
2429 reset_rsvds_bits_mask(vcpu, PT32E_ROOT_LEVEL);
2430 context->gva_to_gpa = paging64_gva_to_gpa;
2431 context->root_level = PT32E_ROOT_LEVEL;
2432 } else {
2433 reset_rsvds_bits_mask(vcpu, PT32_ROOT_LEVEL);
2434 context->gva_to_gpa = paging32_gva_to_gpa;
2435 context->root_level = PT32_ROOT_LEVEL;
2436 }
2437
2438 return 0;
2439 }
2440
2441 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
2442 {
2443 int r;
2444
2445 ASSERT(vcpu);
2446 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2447
2448 if (!is_paging(vcpu))
2449 r = nonpaging_init_context(vcpu);
2450 else if (is_long_mode(vcpu))
2451 r = paging64_init_context(vcpu);
2452 else if (is_pae(vcpu))
2453 r = paging32E_init_context(vcpu);
2454 else
2455 r = paging32_init_context(vcpu);
2456
2457 vcpu->arch.mmu.base_role.glevels = vcpu->arch.mmu.root_level;
2458 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
2459
2460 return r;
2461 }
2462
2463 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2464 {
2465 vcpu->arch.update_pte.pfn = bad_pfn;
2466
2467 if (tdp_enabled)
2468 return init_kvm_tdp_mmu(vcpu);
2469 else
2470 return init_kvm_softmmu(vcpu);
2471 }
2472
2473 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2474 {
2475 ASSERT(vcpu);
2476 if (VALID_PAGE(vcpu->arch.mmu.root_hpa)) {
2477 vcpu->arch.mmu.free(vcpu);
2478 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2479 }
2480 }
2481
2482 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
2483 {
2484 destroy_kvm_mmu(vcpu);
2485 return init_kvm_mmu(vcpu);
2486 }
2487 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
2488
2489 int kvm_mmu_load(struct kvm_vcpu *vcpu)
2490 {
2491 int r;
2492
2493 r = mmu_topup_memory_caches(vcpu);
2494 if (r)
2495 goto out;
2496 spin_lock(&vcpu->kvm->mmu_lock);
2497 kvm_mmu_free_some_pages(vcpu);
2498 spin_unlock(&vcpu->kvm->mmu_lock);
2499 r = mmu_alloc_roots(vcpu);
2500 spin_lock(&vcpu->kvm->mmu_lock);
2501 mmu_sync_roots(vcpu);
2502 spin_unlock(&vcpu->kvm->mmu_lock);
2503 if (r)
2504 goto out;
2505 /* set_cr3() should ensure TLB has been flushed */
2506 kvm_x86_ops->set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
2507 out:
2508 return r;
2509 }
2510 EXPORT_SYMBOL_GPL(kvm_mmu_load);
2511
2512 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2513 {
2514 mmu_free_roots(vcpu);
2515 }
2516
2517 static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
2518 struct kvm_mmu_page *sp,
2519 u64 *spte)
2520 {
2521 u64 pte;
2522 struct kvm_mmu_page *child;
2523
2524 pte = *spte;
2525 if (is_shadow_present_pte(pte)) {
2526 if (is_last_spte(pte, sp->role.level))
2527 rmap_remove(vcpu->kvm, spte);
2528 else {
2529 child = page_header(pte & PT64_BASE_ADDR_MASK);
2530 mmu_page_remove_parent_pte(child, spte);
2531 }
2532 }
2533 __set_spte(spte, shadow_trap_nonpresent_pte);
2534 if (is_large_pte(pte))
2535 --vcpu->kvm->stat.lpages;
2536 }
2537
2538 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
2539 struct kvm_mmu_page *sp,
2540 u64 *spte,
2541 const void *new)
2542 {
2543 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
2544 ++vcpu->kvm->stat.mmu_pde_zapped;
2545 return;
2546 }
2547
2548 ++vcpu->kvm->stat.mmu_pte_updated;
2549 if (sp->role.glevels == PT32_ROOT_LEVEL)
2550 paging32_update_pte(vcpu, sp, spte, new);
2551 else
2552 paging64_update_pte(vcpu, sp, spte, new);
2553 }
2554
2555 static bool need_remote_flush(u64 old, u64 new)
2556 {
2557 if (!is_shadow_present_pte(old))
2558 return false;
2559 if (!is_shadow_present_pte(new))
2560 return true;
2561 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2562 return true;
2563 old ^= PT64_NX_MASK;
2564 new ^= PT64_NX_MASK;
2565 return (old & ~new & PT64_PERM_MASK) != 0;
2566 }
2567
2568 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, u64 old, u64 new)
2569 {
2570 if (need_remote_flush(old, new))
2571 kvm_flush_remote_tlbs(vcpu->kvm);
2572 else
2573 kvm_mmu_flush_tlb(vcpu);
2574 }
2575
2576 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2577 {
2578 u64 *spte = vcpu->arch.last_pte_updated;
2579
2580 return !!(spte && (*spte & shadow_accessed_mask));
2581 }
2582
2583 static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2584 const u8 *new, int bytes)
2585 {
2586 gfn_t gfn;
2587 int r;
2588 u64 gpte = 0;
2589 pfn_t pfn;
2590
2591 if (bytes != 4 && bytes != 8)
2592 return;
2593
2594 /*
2595 * Assume that the pte write on a page table of the same type
2596 * as the current vcpu paging mode. This is nearly always true
2597 * (might be false while changing modes). Note it is verified later
2598 * by update_pte().
2599 */
2600 if (is_pae(vcpu)) {
2601 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
2602 if ((bytes == 4) && (gpa % 4 == 0)) {
2603 r = kvm_read_guest(vcpu->kvm, gpa & ~(u64)7, &gpte, 8);
2604 if (r)
2605 return;
2606 memcpy((void *)&gpte + (gpa % 8), new, 4);
2607 } else if ((bytes == 8) && (gpa % 8 == 0)) {
2608 memcpy((void *)&gpte, new, 8);
2609 }
2610 } else {
2611 if ((bytes == 4) && (gpa % 4 == 0))
2612 memcpy((void *)&gpte, new, 4);
2613 }
2614 if (!is_present_gpte(gpte))
2615 return;
2616 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
2617
2618 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
2619 smp_rmb();
2620 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2621
2622 if (is_error_pfn(pfn)) {
2623 kvm_release_pfn_clean(pfn);
2624 return;
2625 }
2626 vcpu->arch.update_pte.gfn = gfn;
2627 vcpu->arch.update_pte.pfn = pfn;
2628 }
2629
2630 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
2631 {
2632 u64 *spte = vcpu->arch.last_pte_updated;
2633
2634 if (spte
2635 && vcpu->arch.last_pte_gfn == gfn
2636 && shadow_accessed_mask
2637 && !(*spte & shadow_accessed_mask)
2638 && is_shadow_present_pte(*spte))
2639 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
2640 }
2641
2642 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2643 const u8 *new, int bytes,
2644 bool guest_initiated)
2645 {
2646 gfn_t gfn = gpa >> PAGE_SHIFT;
2647 struct kvm_mmu_page *sp;
2648 struct hlist_node *node, *n;
2649 struct hlist_head *bucket;
2650 unsigned index;
2651 u64 entry, gentry;
2652 u64 *spte;
2653 unsigned offset = offset_in_page(gpa);
2654 unsigned pte_size;
2655 unsigned page_offset;
2656 unsigned misaligned;
2657 unsigned quadrant;
2658 int level;
2659 int flooded = 0;
2660 int npte;
2661 int r;
2662
2663 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
2664 mmu_guess_page_from_pte_write(vcpu, gpa, new, bytes);
2665 spin_lock(&vcpu->kvm->mmu_lock);
2666 kvm_mmu_access_page(vcpu, gfn);
2667 kvm_mmu_free_some_pages(vcpu);
2668 ++vcpu->kvm->stat.mmu_pte_write;
2669 kvm_mmu_audit(vcpu, "pre pte write");
2670 if (guest_initiated) {
2671 if (gfn == vcpu->arch.last_pt_write_gfn
2672 && !last_updated_pte_accessed(vcpu)) {
2673 ++vcpu->arch.last_pt_write_count;
2674 if (vcpu->arch.last_pt_write_count >= 3)
2675 flooded = 1;
2676 } else {
2677 vcpu->arch.last_pt_write_gfn = gfn;
2678 vcpu->arch.last_pt_write_count = 1;
2679 vcpu->arch.last_pte_updated = NULL;
2680 }
2681 }
2682 index = kvm_page_table_hashfn(gfn);
2683 bucket = &vcpu->kvm->arch.mmu_page_hash[index];
2684 hlist_for_each_entry_safe(sp, node, n, bucket, hash_link) {
2685 if (sp->gfn != gfn || sp->role.direct || sp->role.invalid)
2686 continue;
2687 pte_size = sp->role.glevels == PT32_ROOT_LEVEL ? 4 : 8;
2688 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
2689 misaligned |= bytes < 4;
2690 if (misaligned || flooded) {
2691 /*
2692 * Misaligned accesses are too much trouble to fix
2693 * up; also, they usually indicate a page is not used
2694 * as a page table.
2695 *
2696 * If we're seeing too many writes to a page,
2697 * it may no longer be a page table, or we may be
2698 * forking, in which case it is better to unmap the
2699 * page.
2700 */
2701 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
2702 gpa, bytes, sp->role.word);
2703 if (kvm_mmu_zap_page(vcpu->kvm, sp))
2704 n = bucket->first;
2705 ++vcpu->kvm->stat.mmu_flooded;
2706 continue;
2707 }
2708 page_offset = offset;
2709 level = sp->role.level;
2710 npte = 1;
2711 if (sp->role.glevels == PT32_ROOT_LEVEL) {
2712 page_offset <<= 1; /* 32->64 */
2713 /*
2714 * A 32-bit pde maps 4MB while the shadow pdes map
2715 * only 2MB. So we need to double the offset again
2716 * and zap two pdes instead of one.
2717 */
2718 if (level == PT32_ROOT_LEVEL) {
2719 page_offset &= ~7; /* kill rounding error */
2720 page_offset <<= 1;
2721 npte = 2;
2722 }
2723 quadrant = page_offset >> PAGE_SHIFT;
2724 page_offset &= ~PAGE_MASK;
2725 if (quadrant != sp->role.quadrant)
2726 continue;
2727 }
2728 spte = &sp->spt[page_offset / sizeof(*spte)];
2729 if ((gpa & (pte_size - 1)) || (bytes < pte_size)) {
2730 gentry = 0;
2731 r = kvm_read_guest_atomic(vcpu->kvm,
2732 gpa & ~(u64)(pte_size - 1),
2733 &gentry, pte_size);
2734 new = (const void *)&gentry;
2735 if (r < 0)
2736 new = NULL;
2737 }
2738 while (npte--) {
2739 entry = *spte;
2740 mmu_pte_write_zap_pte(vcpu, sp, spte);
2741 if (new)
2742 mmu_pte_write_new_pte(vcpu, sp, spte, new);
2743 mmu_pte_write_flush_tlb(vcpu, entry, *spte);
2744 ++spte;
2745 }
2746 }
2747 kvm_mmu_audit(vcpu, "post pte write");
2748 spin_unlock(&vcpu->kvm->mmu_lock);
2749 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
2750 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
2751 vcpu->arch.update_pte.pfn = bad_pfn;
2752 }
2753 }
2754
2755 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2756 {
2757 gpa_t gpa;
2758 int r;
2759
2760 if (tdp_enabled)
2761 return 0;
2762
2763 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2764
2765 spin_lock(&vcpu->kvm->mmu_lock);
2766 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2767 spin_unlock(&vcpu->kvm->mmu_lock);
2768 return r;
2769 }
2770 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
2771
2772 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
2773 {
2774 while (vcpu->kvm->arch.n_free_mmu_pages < KVM_REFILL_PAGES &&
2775 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
2776 struct kvm_mmu_page *sp;
2777
2778 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
2779 struct kvm_mmu_page, link);
2780 kvm_mmu_zap_page(vcpu->kvm, sp);
2781 ++vcpu->kvm->stat.mmu_recycled;
2782 }
2783 }
2784
2785 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
2786 {
2787 int r;
2788 enum emulation_result er;
2789
2790 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
2791 if (r < 0)
2792 goto out;
2793
2794 if (!r) {
2795 r = 1;
2796 goto out;
2797 }
2798
2799 r = mmu_topup_memory_caches(vcpu);
2800 if (r)
2801 goto out;
2802
2803 er = emulate_instruction(vcpu, vcpu->run, cr2, error_code, 0);
2804
2805 switch (er) {
2806 case EMULATE_DONE:
2807 return 1;
2808 case EMULATE_DO_MMIO:
2809 ++vcpu->stat.mmio_exits;
2810 return 0;
2811 case EMULATE_FAIL:
2812 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2813 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2814 return 0;
2815 default:
2816 BUG();
2817 }
2818 out:
2819 return r;
2820 }
2821 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
2822
2823 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
2824 {
2825 vcpu->arch.mmu.invlpg(vcpu, gva);
2826 kvm_mmu_flush_tlb(vcpu);
2827 ++vcpu->stat.invlpg;
2828 }
2829 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
2830
2831 void kvm_enable_tdp(void)
2832 {
2833 tdp_enabled = true;
2834 }
2835 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
2836
2837 void kvm_disable_tdp(void)
2838 {
2839 tdp_enabled = false;
2840 }
2841 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
2842
2843 static void free_mmu_pages(struct kvm_vcpu *vcpu)
2844 {
2845 free_page((unsigned long)vcpu->arch.mmu.pae_root);
2846 }
2847
2848 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
2849 {
2850 struct page *page;
2851 int i;
2852
2853 ASSERT(vcpu);
2854
2855 /*
2856 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
2857 * Therefore we need to allocate shadow page tables in the first
2858 * 4GB of memory, which happens to fit the DMA32 zone.
2859 */
2860 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
2861 if (!page)
2862 goto error_1;
2863 vcpu->arch.mmu.pae_root = page_address(page);
2864 for (i = 0; i < 4; ++i)
2865 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2866
2867 return 0;
2868
2869 error_1:
2870 free_mmu_pages(vcpu);
2871 return -ENOMEM;
2872 }
2873
2874 int kvm_mmu_create(struct kvm_vcpu *vcpu)
2875 {
2876 ASSERT(vcpu);
2877 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2878
2879 return alloc_mmu_pages(vcpu);
2880 }
2881
2882 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
2883 {
2884 ASSERT(vcpu);
2885 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2886
2887 return init_kvm_mmu(vcpu);
2888 }
2889
2890 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
2891 {
2892 ASSERT(vcpu);
2893
2894 destroy_kvm_mmu(vcpu);
2895 free_mmu_pages(vcpu);
2896 mmu_free_memory_caches(vcpu);
2897 }
2898
2899 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
2900 {
2901 struct kvm_mmu_page *sp;
2902
2903 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
2904 int i;
2905 u64 *pt;
2906
2907 if (!test_bit(slot, sp->slot_bitmap))
2908 continue;
2909
2910 pt = sp->spt;
2911 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2912 /* avoid RMW */
2913 if (pt[i] & PT_WRITABLE_MASK)
2914 pt[i] &= ~PT_WRITABLE_MASK;
2915 }
2916 kvm_flush_remote_tlbs(kvm);
2917 }
2918
2919 void kvm_mmu_zap_all(struct kvm *kvm)
2920 {
2921 struct kvm_mmu_page *sp, *node;
2922
2923 spin_lock(&kvm->mmu_lock);
2924 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
2925 if (kvm_mmu_zap_page(kvm, sp))
2926 node = container_of(kvm->arch.active_mmu_pages.next,
2927 struct kvm_mmu_page, link);
2928 spin_unlock(&kvm->mmu_lock);
2929
2930 kvm_flush_remote_tlbs(kvm);
2931 }
2932
2933 static void kvm_mmu_remove_one_alloc_mmu_page(struct kvm *kvm)
2934 {
2935 struct kvm_mmu_page *page;
2936
2937 page = container_of(kvm->arch.active_mmu_pages.prev,
2938 struct kvm_mmu_page, link);
2939 kvm_mmu_zap_page(kvm, page);
2940 }
2941
2942 static int mmu_shrink(int nr_to_scan, gfp_t gfp_mask)
2943 {
2944 struct kvm *kvm;
2945 struct kvm *kvm_freed = NULL;
2946 int cache_count = 0;
2947
2948 spin_lock(&kvm_lock);
2949
2950 list_for_each_entry(kvm, &vm_list, vm_list) {
2951 int npages;
2952
2953 if (!down_read_trylock(&kvm->slots_lock))
2954 continue;
2955 spin_lock(&kvm->mmu_lock);
2956 npages = kvm->arch.n_alloc_mmu_pages -
2957 kvm->arch.n_free_mmu_pages;
2958 cache_count += npages;
2959 if (!kvm_freed && nr_to_scan > 0 && npages > 0) {
2960 kvm_mmu_remove_one_alloc_mmu_page(kvm);
2961 cache_count--;
2962 kvm_freed = kvm;
2963 }
2964 nr_to_scan--;
2965
2966 spin_unlock(&kvm->mmu_lock);
2967 up_read(&kvm->slots_lock);
2968 }
2969 if (kvm_freed)
2970 list_move_tail(&kvm_freed->vm_list, &vm_list);
2971
2972 spin_unlock(&kvm_lock);
2973
2974 return cache_count;
2975 }
2976
2977 static struct shrinker mmu_shrinker = {
2978 .shrink = mmu_shrink,
2979 .seeks = DEFAULT_SEEKS * 10,
2980 };
2981
2982 static void mmu_destroy_caches(void)
2983 {
2984 if (pte_chain_cache)
2985 kmem_cache_destroy(pte_chain_cache);
2986 if (rmap_desc_cache)
2987 kmem_cache_destroy(rmap_desc_cache);
2988 if (mmu_page_header_cache)
2989 kmem_cache_destroy(mmu_page_header_cache);
2990 }
2991
2992 void kvm_mmu_module_exit(void)
2993 {
2994 mmu_destroy_caches();
2995 unregister_shrinker(&mmu_shrinker);
2996 }
2997
2998 int kvm_mmu_module_init(void)
2999 {
3000 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
3001 sizeof(struct kvm_pte_chain),
3002 0, 0, NULL);
3003 if (!pte_chain_cache)
3004 goto nomem;
3005 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
3006 sizeof(struct kvm_rmap_desc),
3007 0, 0, NULL);
3008 if (!rmap_desc_cache)
3009 goto nomem;
3010
3011 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3012 sizeof(struct kvm_mmu_page),
3013 0, 0, NULL);
3014 if (!mmu_page_header_cache)
3015 goto nomem;
3016
3017 register_shrinker(&mmu_shrinker);
3018
3019 return 0;
3020
3021 nomem:
3022 mmu_destroy_caches();
3023 return -ENOMEM;
3024 }
3025
3026 /*
3027 * Caculate mmu pages needed for kvm.
3028 */
3029 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3030 {
3031 int i;
3032 unsigned int nr_mmu_pages;
3033 unsigned int nr_pages = 0;
3034
3035 for (i = 0; i < kvm->nmemslots; i++)
3036 nr_pages += kvm->memslots[i].npages;
3037
3038 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3039 nr_mmu_pages = max(nr_mmu_pages,
3040 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3041
3042 return nr_mmu_pages;
3043 }
3044
3045 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3046 unsigned len)
3047 {
3048 if (len > buffer->len)
3049 return NULL;
3050 return buffer->ptr;
3051 }
3052
3053 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3054 unsigned len)
3055 {
3056 void *ret;
3057
3058 ret = pv_mmu_peek_buffer(buffer, len);
3059 if (!ret)
3060 return ret;
3061 buffer->ptr += len;
3062 buffer->len -= len;
3063 buffer->processed += len;
3064 return ret;
3065 }
3066
3067 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3068 gpa_t addr, gpa_t value)
3069 {
3070 int bytes = 8;
3071 int r;
3072
3073 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3074 bytes = 4;
3075
3076 r = mmu_topup_memory_caches(vcpu);
3077 if (r)
3078 return r;
3079
3080 if (!emulator_write_phys(vcpu, addr, &value, bytes))
3081 return -EFAULT;
3082
3083 return 1;
3084 }
3085
3086 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3087 {
3088 kvm_set_cr3(vcpu, vcpu->arch.cr3);
3089 return 1;
3090 }
3091
3092 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3093 {
3094 spin_lock(&vcpu->kvm->mmu_lock);
3095 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3096 spin_unlock(&vcpu->kvm->mmu_lock);
3097 return 1;
3098 }
3099
3100 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3101 struct kvm_pv_mmu_op_buffer *buffer)
3102 {
3103 struct kvm_mmu_op_header *header;
3104
3105 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3106 if (!header)
3107 return 0;
3108 switch (header->op) {
3109 case KVM_MMU_OP_WRITE_PTE: {
3110 struct kvm_mmu_op_write_pte *wpte;
3111
3112 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3113 if (!wpte)
3114 return 0;
3115 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3116 wpte->pte_val);
3117 }
3118 case KVM_MMU_OP_FLUSH_TLB: {
3119 struct kvm_mmu_op_flush_tlb *ftlb;
3120
3121 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3122 if (!ftlb)
3123 return 0;
3124 return kvm_pv_mmu_flush_tlb(vcpu);
3125 }
3126 case KVM_MMU_OP_RELEASE_PT: {
3127 struct kvm_mmu_op_release_pt *rpt;
3128
3129 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3130 if (!rpt)
3131 return 0;
3132 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3133 }
3134 default: return 0;
3135 }
3136 }
3137
3138 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3139 gpa_t addr, unsigned long *ret)
3140 {
3141 int r;
3142 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
3143
3144 buffer->ptr = buffer->buf;
3145 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3146 buffer->processed = 0;
3147
3148 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
3149 if (r)
3150 goto out;
3151
3152 while (buffer->len) {
3153 r = kvm_pv_mmu_op_one(vcpu, buffer);
3154 if (r < 0)
3155 goto out;
3156 if (r == 0)
3157 break;
3158 }
3159
3160 r = 1;
3161 out:
3162 *ret = buffer->processed;
3163 return r;
3164 }
3165
3166 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3167 {
3168 struct kvm_shadow_walk_iterator iterator;
3169 int nr_sptes = 0;
3170
3171 spin_lock(&vcpu->kvm->mmu_lock);
3172 for_each_shadow_entry(vcpu, addr, iterator) {
3173 sptes[iterator.level-1] = *iterator.sptep;
3174 nr_sptes++;
3175 if (!is_shadow_present_pte(*iterator.sptep))
3176 break;
3177 }
3178 spin_unlock(&vcpu->kvm->mmu_lock);
3179
3180 return nr_sptes;
3181 }
3182 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3183
3184 #ifdef AUDIT
3185
3186 static const char *audit_msg;
3187
3188 static gva_t canonicalize(gva_t gva)
3189 {
3190 #ifdef CONFIG_X86_64
3191 gva = (long long)(gva << 16) >> 16;
3192 #endif
3193 return gva;
3194 }
3195
3196
3197 typedef void (*inspect_spte_fn) (struct kvm *kvm, struct kvm_mmu_page *sp,
3198 u64 *sptep);
3199
3200 static void __mmu_spte_walk(struct kvm *kvm, struct kvm_mmu_page *sp,
3201 inspect_spte_fn fn)
3202 {
3203 int i;
3204
3205 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3206 u64 ent = sp->spt[i];
3207
3208 if (is_shadow_present_pte(ent)) {
3209 if (!is_last_spte(ent, sp->role.level)) {
3210 struct kvm_mmu_page *child;
3211 child = page_header(ent & PT64_BASE_ADDR_MASK);
3212 __mmu_spte_walk(kvm, child, fn);
3213 } else
3214 fn(kvm, sp, &sp->spt[i]);
3215 }
3216 }
3217 }
3218
3219 static void mmu_spte_walk(struct kvm_vcpu *vcpu, inspect_spte_fn fn)
3220 {
3221 int i;
3222 struct kvm_mmu_page *sp;
3223
3224 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3225 return;
3226 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
3227 hpa_t root = vcpu->arch.mmu.root_hpa;
3228 sp = page_header(root);
3229 __mmu_spte_walk(vcpu->kvm, sp, fn);
3230 return;
3231 }
3232 for (i = 0; i < 4; ++i) {
3233 hpa_t root = vcpu->arch.mmu.pae_root[i];
3234
3235 if (root && VALID_PAGE(root)) {
3236 root &= PT64_BASE_ADDR_MASK;
3237 sp = page_header(root);
3238 __mmu_spte_walk(vcpu->kvm, sp, fn);
3239 }
3240 }
3241 return;
3242 }
3243
3244 static void audit_mappings_page(struct kvm_vcpu *vcpu, u64 page_pte,
3245 gva_t va, int level)
3246 {
3247 u64 *pt = __va(page_pte & PT64_BASE_ADDR_MASK);
3248 int i;
3249 gva_t va_delta = 1ul << (PAGE_SHIFT + 9 * (level - 1));
3250
3251 for (i = 0; i < PT64_ENT_PER_PAGE; ++i, va += va_delta) {
3252 u64 ent = pt[i];
3253
3254 if (ent == shadow_trap_nonpresent_pte)
3255 continue;
3256
3257 va = canonicalize(va);
3258 if (is_shadow_present_pte(ent) && !is_last_spte(ent, level))
3259 audit_mappings_page(vcpu, ent, va, level - 1);
3260 else {
3261 gpa_t gpa = kvm_mmu_gva_to_gpa_read(vcpu, va, NULL);
3262 gfn_t gfn = gpa >> PAGE_SHIFT;
3263 pfn_t pfn = gfn_to_pfn(vcpu->kvm, gfn);
3264 hpa_t hpa = (hpa_t)pfn << PAGE_SHIFT;
3265
3266 if (is_error_pfn(pfn)) {
3267 kvm_release_pfn_clean(pfn);
3268 continue;
3269 }
3270
3271 if (is_shadow_present_pte(ent)
3272 && (ent & PT64_BASE_ADDR_MASK) != hpa)
3273 printk(KERN_ERR "xx audit error: (%s) levels %d"
3274 " gva %lx gpa %llx hpa %llx ent %llx %d\n",
3275 audit_msg, vcpu->arch.mmu.root_level,
3276 va, gpa, hpa, ent,
3277 is_shadow_present_pte(ent));
3278 else if (ent == shadow_notrap_nonpresent_pte
3279 && !is_error_hpa(hpa))
3280 printk(KERN_ERR "audit: (%s) notrap shadow,"
3281 " valid guest gva %lx\n", audit_msg, va);
3282 kvm_release_pfn_clean(pfn);
3283
3284 }
3285 }
3286 }
3287
3288 static void audit_mappings(struct kvm_vcpu *vcpu)
3289 {
3290 unsigned i;
3291
3292 if (vcpu->arch.mmu.root_level == 4)
3293 audit_mappings_page(vcpu, vcpu->arch.mmu.root_hpa, 0, 4);
3294 else
3295 for (i = 0; i < 4; ++i)
3296 if (vcpu->arch.mmu.pae_root[i] & PT_PRESENT_MASK)
3297 audit_mappings_page(vcpu,
3298 vcpu->arch.mmu.pae_root[i],
3299 i << 30,
3300 2);
3301 }
3302
3303 static int count_rmaps(struct kvm_vcpu *vcpu)
3304 {
3305 int nmaps = 0;
3306 int i, j, k;
3307
3308 for (i = 0; i < KVM_MEMORY_SLOTS; ++i) {
3309 struct kvm_memory_slot *m = &vcpu->kvm->memslots[i];
3310 struct kvm_rmap_desc *d;
3311
3312 for (j = 0; j < m->npages; ++j) {
3313 unsigned long *rmapp = &m->rmap[j];
3314
3315 if (!*rmapp)
3316 continue;
3317 if (!(*rmapp & 1)) {
3318 ++nmaps;
3319 continue;
3320 }
3321 d = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
3322 while (d) {
3323 for (k = 0; k < RMAP_EXT; ++k)
3324 if (d->sptes[k])
3325 ++nmaps;
3326 else
3327 break;
3328 d = d->more;
3329 }
3330 }
3331 }
3332 return nmaps;
3333 }
3334
3335 void inspect_spte_has_rmap(struct kvm *kvm, struct kvm_mmu_page *sp, u64 *sptep)
3336 {
3337 unsigned long *rmapp;
3338 struct kvm_mmu_page *rev_sp;
3339 gfn_t gfn;
3340
3341 if (*sptep & PT_WRITABLE_MASK) {
3342 rev_sp = page_header(__pa(sptep));
3343 gfn = rev_sp->gfns[sptep - rev_sp->spt];
3344
3345 if (!gfn_to_memslot(kvm, gfn)) {
3346 if (!printk_ratelimit())
3347 return;
3348 printk(KERN_ERR "%s: no memslot for gfn %ld\n",
3349 audit_msg, gfn);
3350 printk(KERN_ERR "%s: index %ld of sp (gfn=%lx)\n",
3351 audit_msg, sptep - rev_sp->spt,
3352 rev_sp->gfn);
3353 dump_stack();
3354 return;
3355 }
3356
3357 rmapp = gfn_to_rmap(kvm, rev_sp->gfns[sptep - rev_sp->spt],
3358 is_large_pte(*sptep));
3359 if (!*rmapp) {
3360 if (!printk_ratelimit())
3361 return;
3362 printk(KERN_ERR "%s: no rmap for writable spte %llx\n",
3363 audit_msg, *sptep);
3364 dump_stack();
3365 }
3366 }
3367
3368 }
3369
3370 void audit_writable_sptes_have_rmaps(struct kvm_vcpu *vcpu)
3371 {
3372 mmu_spte_walk(vcpu, inspect_spte_has_rmap);
3373 }
3374
3375 static void check_writable_mappings_rmap(struct kvm_vcpu *vcpu)
3376 {
3377 struct kvm_mmu_page *sp;
3378 int i;
3379
3380 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
3381 u64 *pt = sp->spt;
3382
3383 if (sp->role.level != PT_PAGE_TABLE_LEVEL)
3384 continue;
3385
3386 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
3387 u64 ent = pt[i];
3388
3389 if (!(ent & PT_PRESENT_MASK))
3390 continue;
3391 if (!(ent & PT_WRITABLE_MASK))
3392 continue;
3393 inspect_spte_has_rmap(vcpu->kvm, sp, &pt[i]);
3394 }
3395 }
3396 return;
3397 }
3398
3399 static void audit_rmap(struct kvm_vcpu *vcpu)
3400 {
3401 check_writable_mappings_rmap(vcpu);
3402 count_rmaps(vcpu);
3403 }
3404
3405 static void audit_write_protection(struct kvm_vcpu *vcpu)
3406 {
3407 struct kvm_mmu_page *sp;
3408 struct kvm_memory_slot *slot;
3409 unsigned long *rmapp;
3410 u64 *spte;
3411 gfn_t gfn;
3412
3413 list_for_each_entry(sp, &vcpu->kvm->arch.active_mmu_pages, link) {
3414 if (sp->role.direct)
3415 continue;
3416 if (sp->unsync)
3417 continue;
3418
3419 gfn = unalias_gfn(vcpu->kvm, sp->gfn);
3420 slot = gfn_to_memslot_unaliased(vcpu->kvm, sp->gfn);
3421 rmapp = &slot->rmap[gfn - slot->base_gfn];
3422
3423 spte = rmap_next(vcpu->kvm, rmapp, NULL);
3424 while (spte) {
3425 if (*spte & PT_WRITABLE_MASK)
3426 printk(KERN_ERR "%s: (%s) shadow page has "
3427 "writable mappings: gfn %lx role %x\n",
3428 __func__, audit_msg, sp->gfn,
3429 sp->role.word);
3430 spte = rmap_next(vcpu->kvm, rmapp, spte);
3431 }
3432 }
3433 }
3434
3435 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, const char *msg)
3436 {
3437 int olddbg = dbg;
3438
3439 dbg = 0;
3440 audit_msg = msg;
3441 audit_rmap(vcpu);
3442 audit_write_protection(vcpu);
3443 if (strcmp("pre pte write", audit_msg) != 0)
3444 audit_mappings(vcpu);
3445 audit_writable_sptes_have_rmaps(vcpu);
3446 dbg = olddbg;
3447 }
3448
3449 #endif
Linux ARM platform port for MOXA ART SoC