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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / ata / ata_piix.c
blobc33591d3a5999a4e624578132b53eea00d820a98
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <scsi/scsi_host.h>
94 #include <linux/libata.h>
95 #include <linux/dmi.h>
96
97 #define DRV_NAME "ata_piix"
98 #define DRV_VERSION "2.13"
99
100 enum {
101 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
102 ICH5_PMR = 0x90, /* port mapping register */
103 ICH5_PCS = 0x92, /* port control and status */
104 PIIX_SIDPR_BAR = 5,
105 PIIX_SIDPR_LEN = 16,
106 PIIX_SIDPR_IDX = 0,
107 PIIX_SIDPR_DATA = 4,
108
109 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
110 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
111
112 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
113 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
114
115 PIIX_80C_PRI = (1 << 5) | (1 << 4),
116 PIIX_80C_SEC = (1 << 7) | (1 << 6),
117
118 /* constants for mapping table */
119 P0 = 0, /* port 0 */
120 P1 = 1, /* port 1 */
121 P2 = 2, /* port 2 */
122 P3 = 3, /* port 3 */
123 IDE = -1, /* IDE */
124 NA = -2, /* not avaliable */
125 RV = -3, /* reserved */
126
127 PIIX_AHCI_DEVICE = 6,
128
129 /* host->flags bits */
130 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
131 };
132
133 enum piix_controller_ids {
134 /* controller IDs */
135 piix_pata_mwdma, /* PIIX3 MWDMA only */
136 piix_pata_33, /* PIIX4 at 33Mhz */
137 ich_pata_33, /* ICH up to UDMA 33 only */
138 ich_pata_66, /* ICH up to 66 Mhz */
139 ich_pata_100, /* ICH up to UDMA 100 */
140 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
141 ich5_sata,
142 ich6_sata,
143 ich6m_sata,
144 ich8_sata,
145 ich8_2port_sata,
146 ich8m_apple_sata, /* locks up on second port enable */
147 tolapai_sata,
148 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
149 };
150
151 struct piix_map_db {
152 const u32 mask;
153 const u16 port_enable;
154 const int map[][4];
155 };
156
157 struct piix_host_priv {
158 const int *map;
159 u32 saved_iocfg;
160 spinlock_t sidpr_lock; /* FIXME: remove once locking in EH is fixed */
161 void __iomem *sidpr;
162 };
163
164 static int piix_init_one(struct pci_dev *pdev,
165 const struct pci_device_id *ent);
166 static void piix_remove_one(struct pci_dev *pdev);
167 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
168 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
169 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
170 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
171 static int ich_pata_cable_detect(struct ata_port *ap);
172 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
173 static int piix_sidpr_scr_read(struct ata_link *link,
174 unsigned int reg, u32 *val);
175 static int piix_sidpr_scr_write(struct ata_link *link,
176 unsigned int reg, u32 val);
177 #ifdef CONFIG_PM
178 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
179 static int piix_pci_device_resume(struct pci_dev *pdev);
180 #endif
181
182 static unsigned int in_module_init = 1;
183
184 static const struct pci_device_id piix_pci_tbl[] = {
185 /* Intel PIIX3 for the 430HX etc */
186 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
187 /* VMware ICH4 */
188 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
189 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
190 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
191 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
192 /* Intel PIIX4 */
193 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
194 /* Intel PIIX4 */
195 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
196 /* Intel PIIX */
197 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
198 /* Intel ICH (i810, i815, i840) UDMA 66*/
199 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
200 /* Intel ICH0 : UDMA 33*/
201 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
202 /* Intel ICH2M */
203 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
205 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* Intel ICH3M */
207 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* Intel ICH3 (E7500/1) UDMA 100 */
209 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
210 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
211 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
212 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 /* Intel ICH5 */
214 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215 /* C-ICH (i810E2) */
216 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
217 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
218 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219 /* ICH6 (and 6) (i915) UDMA 100 */
220 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 /* ICH7/7-R (i945, i975) UDMA 100*/
222 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
223 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
224 /* ICH8 Mobile PATA Controller */
225 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
226
227 /* SATA ports */
228
229 /* 82801EB (ICH5) */
230 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
231 /* 82801EB (ICH5) */
232 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
233 /* 6300ESB (ICH5 variant with broken PCS present bits) */
234 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
235 /* 6300ESB pretending RAID */
236 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
237 /* 82801FB/FW (ICH6/ICH6W) */
238 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
239 /* 82801FR/FRW (ICH6R/ICH6RW) */
240 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
241 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
242 * Attach iff the controller is in IDE mode. */
243 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
244 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
245 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
246 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
247 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
248 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
249 /* Enterprise Southbridge 2 (631xESB/632xESB) */
250 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
251 /* SATA Controller 1 IDE (ICH8) */
252 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
253 /* SATA Controller 2 IDE (ICH8) */
254 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
255 /* Mobile SATA Controller IDE (ICH8M), Apple */
256 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
257 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
258 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
259 /* Mobile SATA Controller IDE (ICH8M) */
260 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
261 /* SATA Controller IDE (ICH9) */
262 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
263 /* SATA Controller IDE (ICH9) */
264 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
265 /* SATA Controller IDE (ICH9) */
266 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
267 /* SATA Controller IDE (ICH9M) */
268 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
269 /* SATA Controller IDE (ICH9M) */
270 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
271 /* SATA Controller IDE (ICH9M) */
272 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
273 /* SATA Controller IDE (Tolapai) */
274 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
275 /* SATA Controller IDE (ICH10) */
276 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
277 /* SATA Controller IDE (ICH10) */
278 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
279 /* SATA Controller IDE (ICH10) */
280 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
281 /* SATA Controller IDE (ICH10) */
282 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
283 /* SATA Controller IDE (PCH) */
284 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
285 /* SATA Controller IDE (PCH) */
286 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
287 /* SATA Controller IDE (PCH) */
288 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
289 /* SATA Controller IDE (PCH) */
290 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
291 /* SATA Controller IDE (PCH) */
292 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
293 /* SATA Controller IDE (PCH) */
294 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
295 /* SATA Controller IDE (CPT) */
296 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
297 /* SATA Controller IDE (CPT) */
298 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
299 /* SATA Controller IDE (CPT) */
300 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
301 /* SATA Controller IDE (CPT) */
302 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
303 { } /* terminate list */
304 };
305
306 static struct pci_driver piix_pci_driver = {
307 .name = DRV_NAME,
308 .id_table = piix_pci_tbl,
309 .probe = piix_init_one,
310 .remove = piix_remove_one,
311 #ifdef CONFIG_PM
312 .suspend = piix_pci_device_suspend,
313 .resume = piix_pci_device_resume,
314 #endif
315 };
316
317 static struct scsi_host_template piix_sht = {
318 ATA_BMDMA_SHT(DRV_NAME),
319 };
320
321 static struct ata_port_operations piix_pata_ops = {
322 .inherits = &ata_bmdma32_port_ops,
323 .cable_detect = ata_cable_40wire,
324 .set_piomode = piix_set_piomode,
325 .set_dmamode = piix_set_dmamode,
326 .prereset = piix_pata_prereset,
327 };
328
329 static struct ata_port_operations piix_vmw_ops = {
330 .inherits = &piix_pata_ops,
331 .bmdma_status = piix_vmw_bmdma_status,
332 };
333
334 static struct ata_port_operations ich_pata_ops = {
335 .inherits = &piix_pata_ops,
336 .cable_detect = ich_pata_cable_detect,
337 .set_dmamode = ich_set_dmamode,
338 };
339
340 static struct ata_port_operations piix_sata_ops = {
341 .inherits = &ata_bmdma_port_ops,
342 };
343
344 static struct ata_port_operations piix_sidpr_sata_ops = {
345 .inherits = &piix_sata_ops,
346 .hardreset = sata_std_hardreset,
347 .scr_read = piix_sidpr_scr_read,
348 .scr_write = piix_sidpr_scr_write,
349 };
350
351 static const struct piix_map_db ich5_map_db = {
352 .mask = 0x7,
353 .port_enable = 0x3,
354 .map = {
355 /* PM PS SM SS MAP */
356 { P0, NA, P1, NA }, /* 000b */
357 { P1, NA, P0, NA }, /* 001b */
358 { RV, RV, RV, RV },
359 { RV, RV, RV, RV },
360 { P0, P1, IDE, IDE }, /* 100b */
361 { P1, P0, IDE, IDE }, /* 101b */
362 { IDE, IDE, P0, P1 }, /* 110b */
363 { IDE, IDE, P1, P0 }, /* 111b */
364 },
365 };
366
367 static const struct piix_map_db ich6_map_db = {
368 .mask = 0x3,
369 .port_enable = 0xf,
370 .map = {
371 /* PM PS SM SS MAP */
372 { P0, P2, P1, P3 }, /* 00b */
373 { IDE, IDE, P1, P3 }, /* 01b */
374 { P0, P2, IDE, IDE }, /* 10b */
375 { RV, RV, RV, RV },
376 },
377 };
378
379 static const struct piix_map_db ich6m_map_db = {
380 .mask = 0x3,
381 .port_enable = 0x5,
382
383 /* Map 01b isn't specified in the doc but some notebooks use
384 * it anyway. MAP 01b have been spotted on both ICH6M and
385 * ICH7M.
386 */
387 .map = {
388 /* PM PS SM SS MAP */
389 { P0, P2, NA, NA }, /* 00b */
390 { IDE, IDE, P1, P3 }, /* 01b */
391 { P0, P2, IDE, IDE }, /* 10b */
392 { RV, RV, RV, RV },
393 },
394 };
395
396 static const struct piix_map_db ich8_map_db = {
397 .mask = 0x3,
398 .port_enable = 0xf,
399 .map = {
400 /* PM PS SM SS MAP */
401 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
402 { RV, RV, RV, RV },
403 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
404 { RV, RV, RV, RV },
405 },
406 };
407
408 static const struct piix_map_db ich8_2port_map_db = {
409 .mask = 0x3,
410 .port_enable = 0x3,
411 .map = {
412 /* PM PS SM SS MAP */
413 { P0, NA, P1, NA }, /* 00b */
414 { RV, RV, RV, RV }, /* 01b */
415 { RV, RV, RV, RV }, /* 10b */
416 { RV, RV, RV, RV },
417 },
418 };
419
420 static const struct piix_map_db ich8m_apple_map_db = {
421 .mask = 0x3,
422 .port_enable = 0x1,
423 .map = {
424 /* PM PS SM SS MAP */
425 { P0, NA, NA, NA }, /* 00b */
426 { RV, RV, RV, RV },
427 { P0, P2, IDE, IDE }, /* 10b */
428 { RV, RV, RV, RV },
429 },
430 };
431
432 static const struct piix_map_db tolapai_map_db = {
433 .mask = 0x3,
434 .port_enable = 0x3,
435 .map = {
436 /* PM PS SM SS MAP */
437 { P0, NA, P1, NA }, /* 00b */
438 { RV, RV, RV, RV }, /* 01b */
439 { RV, RV, RV, RV }, /* 10b */
440 { RV, RV, RV, RV },
441 },
442 };
443
444 static const struct piix_map_db *piix_map_db_table[] = {
445 [ich5_sata] = &ich5_map_db,
446 [ich6_sata] = &ich6_map_db,
447 [ich6m_sata] = &ich6m_map_db,
448 [ich8_sata] = &ich8_map_db,
449 [ich8_2port_sata] = &ich8_2port_map_db,
450 [ich8m_apple_sata] = &ich8m_apple_map_db,
451 [tolapai_sata] = &tolapai_map_db,
452 };
453
454 static struct ata_port_info piix_port_info[] = {
455 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
456 {
457 .flags = PIIX_PATA_FLAGS,
458 .pio_mask = ATA_PIO4,
459 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
460 .port_ops = &piix_pata_ops,
461 },
462
463 [piix_pata_33] = /* PIIX4 at 33MHz */
464 {
465 .flags = PIIX_PATA_FLAGS,
466 .pio_mask = ATA_PIO4,
467 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
468 .udma_mask = ATA_UDMA2,
469 .port_ops = &piix_pata_ops,
470 },
471
472 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
473 {
474 .flags = PIIX_PATA_FLAGS,
475 .pio_mask = ATA_PIO4,
476 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
477 .udma_mask = ATA_UDMA2,
478 .port_ops = &ich_pata_ops,
479 },
480
481 [ich_pata_66] = /* ICH controllers up to 66MHz */
482 {
483 .flags = PIIX_PATA_FLAGS,
484 .pio_mask = ATA_PIO4,
485 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
486 .udma_mask = ATA_UDMA4,
487 .port_ops = &ich_pata_ops,
488 },
489
490 [ich_pata_100] =
491 {
492 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
493 .pio_mask = ATA_PIO4,
494 .mwdma_mask = ATA_MWDMA12_ONLY,
495 .udma_mask = ATA_UDMA5,
496 .port_ops = &ich_pata_ops,
497 },
498
499 [ich_pata_100_nomwdma1] =
500 {
501 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
502 .pio_mask = ATA_PIO4,
503 .mwdma_mask = ATA_MWDMA2_ONLY,
504 .udma_mask = ATA_UDMA5,
505 .port_ops = &ich_pata_ops,
506 },
507
508 [ich5_sata] =
509 {
510 .flags = PIIX_SATA_FLAGS,
511 .pio_mask = ATA_PIO4,
512 .mwdma_mask = ATA_MWDMA2,
513 .udma_mask = ATA_UDMA6,
514 .port_ops = &piix_sata_ops,
515 },
516
517 [ich6_sata] =
518 {
519 .flags = PIIX_SATA_FLAGS,
520 .pio_mask = ATA_PIO4,
521 .mwdma_mask = ATA_MWDMA2,
522 .udma_mask = ATA_UDMA6,
523 .port_ops = &piix_sata_ops,
524 },
525
526 [ich6m_sata] =
527 {
528 .flags = PIIX_SATA_FLAGS,
529 .pio_mask = ATA_PIO4,
530 .mwdma_mask = ATA_MWDMA2,
531 .udma_mask = ATA_UDMA6,
532 .port_ops = &piix_sata_ops,
533 },
534
535 [ich8_sata] =
536 {
537 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
538 .pio_mask = ATA_PIO4,
539 .mwdma_mask = ATA_MWDMA2,
540 .udma_mask = ATA_UDMA6,
541 .port_ops = &piix_sata_ops,
542 },
543
544 [ich8_2port_sata] =
545 {
546 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
547 .pio_mask = ATA_PIO4,
548 .mwdma_mask = ATA_MWDMA2,
549 .udma_mask = ATA_UDMA6,
550 .port_ops = &piix_sata_ops,
551 },
552
553 [tolapai_sata] =
554 {
555 .flags = PIIX_SATA_FLAGS,
556 .pio_mask = ATA_PIO4,
557 .mwdma_mask = ATA_MWDMA2,
558 .udma_mask = ATA_UDMA6,
559 .port_ops = &piix_sata_ops,
560 },
561
562 [ich8m_apple_sata] =
563 {
564 .flags = PIIX_SATA_FLAGS,
565 .pio_mask = ATA_PIO4,
566 .mwdma_mask = ATA_MWDMA2,
567 .udma_mask = ATA_UDMA6,
568 .port_ops = &piix_sata_ops,
569 },
570
571 [piix_pata_vmw] =
572 {
573 .flags = PIIX_PATA_FLAGS,
574 .pio_mask = ATA_PIO4,
575 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
576 .udma_mask = ATA_UDMA2,
577 .port_ops = &piix_vmw_ops,
578 },
579
580 };
581
582 static struct pci_bits piix_enable_bits[] = {
583 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
584 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
585 };
586
587 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
588 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
589 MODULE_LICENSE("GPL");
590 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
591 MODULE_VERSION(DRV_VERSION);
592
593 struct ich_laptop {
594 u16 device;
595 u16 subvendor;
596 u16 subdevice;
597 };
598
599 /*
600 * List of laptops that use short cables rather than 80 wire
601 */
602
603 static const struct ich_laptop ich_laptop[] = {
604 /* devid, subvendor, subdev */
605 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
606 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
607 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
608 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
609 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
610 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
611 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unkown HP */
612 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
613 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
614 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
615 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
616 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
617 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
618 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
619 /* end marker */
620 { 0, }
621 };
622
623 /**
624 * ich_pata_cable_detect - Probe host controller cable detect info
625 * @ap: Port for which cable detect info is desired
626 *
627 * Read 80c cable indicator from ATA PCI device's PCI config
628 * register. This register is normally set by firmware (BIOS).
629 *
630 * LOCKING:
631 * None (inherited from caller).
632 */
633
634 static int ich_pata_cable_detect(struct ata_port *ap)
635 {
636 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
637 struct piix_host_priv *hpriv = ap->host->private_data;
638 const struct ich_laptop *lap = &ich_laptop[0];
639 u8 mask;
640
641 /* Check for specials - Acer Aspire 5602WLMi */
642 while (lap->device) {
643 if (lap->device == pdev->device &&
644 lap->subvendor == pdev->subsystem_vendor &&
645 lap->subdevice == pdev->subsystem_device)
646 return ATA_CBL_PATA40_SHORT;
647
648 lap++;
649 }
650
651 /* check BIOS cable detect results */
652 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
653 if ((hpriv->saved_iocfg & mask) == 0)
654 return ATA_CBL_PATA40;
655 return ATA_CBL_PATA80;
656 }
657
658 /**
659 * piix_pata_prereset - prereset for PATA host controller
660 * @link: Target link
661 * @deadline: deadline jiffies for the operation
662 *
663 * LOCKING:
664 * None (inherited from caller).
665 */
666 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
667 {
668 struct ata_port *ap = link->ap;
669 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
670
671 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
672 return -ENOENT;
673 return ata_sff_prereset(link, deadline);
674 }
675
676 static DEFINE_SPINLOCK(piix_lock);
677
678 /**
679 * piix_set_piomode - Initialize host controller PATA PIO timings
680 * @ap: Port whose timings we are configuring
681 * @adev: um
682 *
683 * Set PIO mode for device, in host controller PCI config space.
684 *
685 * LOCKING:
686 * None (inherited from caller).
687 */
688
689 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
690 {
691 struct pci_dev *dev = to_pci_dev(ap->host->dev);
692 unsigned long flags;
693 unsigned int pio = adev->pio_mode - XFER_PIO_0;
694 unsigned int is_slave = (adev->devno != 0);
695 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
696 unsigned int slave_port = 0x44;
697 u16 master_data;
698 u8 slave_data;
699 u8 udma_enable;
700 int control = 0;
701
702 /*
703 * See Intel Document 298600-004 for the timing programing rules
704 * for ICH controllers.
705 */
706
707 static const /* ISP RTC */
708 u8 timings[][2] = { { 0, 0 },
709 { 0, 0 },
710 { 1, 0 },
711 { 2, 1 },
712 { 2, 3 }, };
713
714 if (pio >= 2)
715 control |= 1; /* TIME1 enable */
716 if (ata_pio_need_iordy(adev))
717 control |= 2; /* IE enable */
718
719 /* Intel specifies that the PPE functionality is for disk only */
720 if (adev->class == ATA_DEV_ATA)
721 control |= 4; /* PPE enable */
722
723 spin_lock_irqsave(&piix_lock, flags);
724
725 /* PIO configuration clears DTE unconditionally. It will be
726 * programmed in set_dmamode which is guaranteed to be called
727 * after set_piomode if any DMA mode is available.
728 */
729 pci_read_config_word(dev, master_port, &master_data);
730 if (is_slave) {
731 /* clear TIME1|IE1|PPE1|DTE1 */
732 master_data &= 0xff0f;
733 /* Enable SITRE (separate slave timing register) */
734 master_data |= 0x4000;
735 /* enable PPE1, IE1 and TIME1 as needed */
736 master_data |= (control << 4);
737 pci_read_config_byte(dev, slave_port, &slave_data);
738 slave_data &= (ap->port_no ? 0x0f : 0xf0);
739 /* Load the timing nibble for this slave */
740 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
741 << (ap->port_no ? 4 : 0);
742 } else {
743 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
744 master_data &= 0xccf0;
745 /* Enable PPE, IE and TIME as appropriate */
746 master_data |= control;
747 /* load ISP and RCT */
748 master_data |=
749 (timings[pio][0] << 12) |
750 (timings[pio][1] << 8);
751 }
752 pci_write_config_word(dev, master_port, master_data);
753 if (is_slave)
754 pci_write_config_byte(dev, slave_port, slave_data);
755
756 /* Ensure the UDMA bit is off - it will be turned back on if
757 UDMA is selected */
758
759 if (ap->udma_mask) {
760 pci_read_config_byte(dev, 0x48, &udma_enable);
761 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
762 pci_write_config_byte(dev, 0x48, udma_enable);
763 }
764
765 spin_unlock_irqrestore(&piix_lock, flags);
766 }
767
768 /**
769 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
770 * @ap: Port whose timings we are configuring
771 * @adev: Drive in question
772 * @isich: set if the chip is an ICH device
773 *
774 * Set UDMA mode for device, in host controller PCI config space.
775 *
776 * LOCKING:
777 * None (inherited from caller).
778 */
779
780 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
781 {
782 struct pci_dev *dev = to_pci_dev(ap->host->dev);
783 unsigned long flags;
784 u8 master_port = ap->port_no ? 0x42 : 0x40;
785 u16 master_data;
786 u8 speed = adev->dma_mode;
787 int devid = adev->devno + 2 * ap->port_no;
788 u8 udma_enable = 0;
789
790 static const /* ISP RTC */
791 u8 timings[][2] = { { 0, 0 },
792 { 0, 0 },
793 { 1, 0 },
794 { 2, 1 },
795 { 2, 3 }, };
796
797 spin_lock_irqsave(&piix_lock, flags);
798
799 pci_read_config_word(dev, master_port, &master_data);
800 if (ap->udma_mask)
801 pci_read_config_byte(dev, 0x48, &udma_enable);
802
803 if (speed >= XFER_UDMA_0) {
804 unsigned int udma = adev->dma_mode - XFER_UDMA_0;
805 u16 udma_timing;
806 u16 ideconf;
807 int u_clock, u_speed;
808
809 /*
810 * UDMA is handled by a combination of clock switching and
811 * selection of dividers
812 *
813 * Handy rule: Odd modes are UDMATIMx 01, even are 02
814 * except UDMA0 which is 00
815 */
816 u_speed = min(2 - (udma & 1), udma);
817 if (udma == 5)
818 u_clock = 0x1000; /* 100Mhz */
819 else if (udma > 2)
820 u_clock = 1; /* 66Mhz */
821 else
822 u_clock = 0; /* 33Mhz */
823
824 udma_enable |= (1 << devid);
825
826 /* Load the CT/RP selection */
827 pci_read_config_word(dev, 0x4A, &udma_timing);
828 udma_timing &= ~(3 << (4 * devid));
829 udma_timing |= u_speed << (4 * devid);
830 pci_write_config_word(dev, 0x4A, udma_timing);
831
832 if (isich) {
833 /* Select a 33/66/100Mhz clock */
834 pci_read_config_word(dev, 0x54, &ideconf);
835 ideconf &= ~(0x1001 << devid);
836 ideconf |= u_clock << devid;
837 /* For ICH or later we should set bit 10 for better
838 performance (WR_PingPong_En) */
839 pci_write_config_word(dev, 0x54, ideconf);
840 }
841 } else {
842 /*
843 * MWDMA is driven by the PIO timings. We must also enable
844 * IORDY unconditionally along with TIME1. PPE has already
845 * been set when the PIO timing was set.
846 */
847 unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
848 unsigned int control;
849 u8 slave_data;
850 const unsigned int needed_pio[3] = {
851 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
852 };
853 int pio = needed_pio[mwdma] - XFER_PIO_0;
854
855 control = 3; /* IORDY|TIME1 */
856
857 /* If the drive MWDMA is faster than it can do PIO then
858 we must force PIO into PIO0 */
859
860 if (adev->pio_mode < needed_pio[mwdma])
861 /* Enable DMA timing only */
862 control |= 8; /* PIO cycles in PIO0 */
863
864 if (adev->devno) { /* Slave */
865 master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
866 master_data |= control << 4;
867 pci_read_config_byte(dev, 0x44, &slave_data);
868 slave_data &= (ap->port_no ? 0x0f : 0xf0);
869 /* Load the matching timing */
870 slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
871 pci_write_config_byte(dev, 0x44, slave_data);
872 } else { /* Master */
873 master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
874 and master timing bits */
875 master_data |= control;
876 master_data |=
877 (timings[pio][0] << 12) |
878 (timings[pio][1] << 8);
879 }
880
881 if (ap->udma_mask)
882 udma_enable &= ~(1 << devid);
883
884 pci_write_config_word(dev, master_port, master_data);
885 }
886 /* Don't scribble on 0x48 if the controller does not support UDMA */
887 if (ap->udma_mask)
888 pci_write_config_byte(dev, 0x48, udma_enable);
889
890 spin_unlock_irqrestore(&piix_lock, flags);
891 }
892
893 /**
894 * piix_set_dmamode - Initialize host controller PATA DMA timings
895 * @ap: Port whose timings we are configuring
896 * @adev: um
897 *
898 * Set MW/UDMA mode for device, in host controller PCI config space.
899 *
900 * LOCKING:
901 * None (inherited from caller).
902 */
903
904 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
905 {
906 do_pata_set_dmamode(ap, adev, 0);
907 }
908
909 /**
910 * ich_set_dmamode - Initialize host controller PATA DMA timings
911 * @ap: Port whose timings we are configuring
912 * @adev: um
913 *
914 * Set MW/UDMA mode for device, in host controller PCI config space.
915 *
916 * LOCKING:
917 * None (inherited from caller).
918 */
919
920 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
921 {
922 do_pata_set_dmamode(ap, adev, 1);
923 }
924
925 /*
926 * Serial ATA Index/Data Pair Superset Registers access
927 *
928 * Beginning from ICH8, there's a sane way to access SCRs using index
929 * and data register pair located at BAR5 which means that we have
930 * separate SCRs for master and slave. This is handled using libata
931 * slave_link facility.
932 */
933 static const int piix_sidx_map[] = {
934 [SCR_STATUS] = 0,
935 [SCR_ERROR] = 2,
936 [SCR_CONTROL] = 1,
937 };
938
939 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
940 {
941 struct ata_port *ap = link->ap;
942 struct piix_host_priv *hpriv = ap->host->private_data;
943
944 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
945 hpriv->sidpr + PIIX_SIDPR_IDX);
946 }
947
948 static int piix_sidpr_scr_read(struct ata_link *link,
949 unsigned int reg, u32 *val)
950 {
951 struct piix_host_priv *hpriv = link->ap->host->private_data;
952 unsigned long flags;
953
954 if (reg >= ARRAY_SIZE(piix_sidx_map))
955 return -EINVAL;
956
957 spin_lock_irqsave(&hpriv->sidpr_lock, flags);
958 piix_sidpr_sel(link, reg);
959 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
960 spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
961 return 0;
962 }
963
964 static int piix_sidpr_scr_write(struct ata_link *link,
965 unsigned int reg, u32 val)
966 {
967 struct piix_host_priv *hpriv = link->ap->host->private_data;
968 unsigned long flags;
969
970 if (reg >= ARRAY_SIZE(piix_sidx_map))
971 return -EINVAL;
972
973 spin_lock_irqsave(&hpriv->sidpr_lock, flags);
974 piix_sidpr_sel(link, reg);
975 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
976 spin_unlock_irqrestore(&hpriv->sidpr_lock, flags);
977 return 0;
978 }
979
980 #ifdef CONFIG_PM
981 static int piix_broken_suspend(void)
982 {
983 static const struct dmi_system_id sysids[] = {
984 {
985 .ident = "TECRA M3",
986 .matches = {
987 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
988 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
989 },
990 },
991 {
992 .ident = "TECRA M3",
993 .matches = {
994 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
995 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
996 },
997 },
998 {
999 .ident = "TECRA M4",
1000 .matches = {
1001 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1002 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1003 },
1004 },
1005 {
1006 .ident = "TECRA M4",
1007 .matches = {
1008 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1009 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1010 },
1011 },
1012 {
1013 .ident = "TECRA M5",
1014 .matches = {
1015 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1016 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1017 },
1018 },
1019 {
1020 .ident = "TECRA M6",
1021 .matches = {
1022 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1023 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1024 },
1025 },
1026 {
1027 .ident = "TECRA M7",
1028 .matches = {
1029 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1030 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1031 },
1032 },
1033 {
1034 .ident = "TECRA A8",
1035 .matches = {
1036 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1037 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1038 },
1039 },
1040 {
1041 .ident = "Satellite R20",
1042 .matches = {
1043 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1044 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1045 },
1046 },
1047 {
1048 .ident = "Satellite R25",
1049 .matches = {
1050 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1051 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1052 },
1053 },
1054 {
1055 .ident = "Satellite U200",
1056 .matches = {
1057 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1058 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1059 },
1060 },
1061 {
1062 .ident = "Satellite U200",
1063 .matches = {
1064 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1065 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1066 },
1067 },
1068 {
1069 .ident = "Satellite Pro U200",
1070 .matches = {
1071 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1072 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1073 },
1074 },
1075 {
1076 .ident = "Satellite U205",
1077 .matches = {
1078 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1079 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1080 },
1081 },
1082 {
1083 .ident = "SATELLITE U205",
1084 .matches = {
1085 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1086 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1087 },
1088 },
1089 {
1090 .ident = "Portege M500",
1091 .matches = {
1092 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1093 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1094 },
1095 },
1096 {
1097 .ident = "VGN-BX297XP",
1098 .matches = {
1099 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1100 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1101 },
1102 },
1103
1104 { } /* terminate list */
1105 };
1106 static const char *oemstrs[] = {
1107 "Tecra M3,",
1108 };
1109 int i;
1110
1111 if (dmi_check_system(sysids))
1112 return 1;
1113
1114 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1115 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1116 return 1;
1117
1118 /* TECRA M4 sometimes forgets its identify and reports bogus
1119 * DMI information. As the bogus information is a bit
1120 * generic, match as many entries as possible. This manual
1121 * matching is necessary because dmi_system_id.matches is
1122 * limited to four entries.
1123 */
1124 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1125 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1126 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1127 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1128 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1129 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1130 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1131 return 1;
1132
1133 return 0;
1134 }
1135
1136 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1137 {
1138 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1139 unsigned long flags;
1140 int rc = 0;
1141
1142 rc = ata_host_suspend(host, mesg);
1143 if (rc)
1144 return rc;
1145
1146 /* Some braindamaged ACPI suspend implementations expect the
1147 * controller to be awake on entry; otherwise, it burns cpu
1148 * cycles and power trying to do something to the sleeping
1149 * beauty.
1150 */
1151 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1152 pci_save_state(pdev);
1153
1154 /* mark its power state as "unknown", since we don't
1155 * know if e.g. the BIOS will change its device state
1156 * when we suspend.
1157 */
1158 if (pdev->current_state == PCI_D0)
1159 pdev->current_state = PCI_UNKNOWN;
1160
1161 /* tell resume that it's waking up from broken suspend */
1162 spin_lock_irqsave(&host->lock, flags);
1163 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1164 spin_unlock_irqrestore(&host->lock, flags);
1165 } else
1166 ata_pci_device_do_suspend(pdev, mesg);
1167
1168 return 0;
1169 }
1170
1171 static int piix_pci_device_resume(struct pci_dev *pdev)
1172 {
1173 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1174 unsigned long flags;
1175 int rc;
1176
1177 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1178 spin_lock_irqsave(&host->lock, flags);
1179 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1180 spin_unlock_irqrestore(&host->lock, flags);
1181
1182 pci_set_power_state(pdev, PCI_D0);
1183 pci_restore_state(pdev);
1184
1185 /* PCI device wasn't disabled during suspend. Use
1186 * pci_reenable_device() to avoid affecting the enable
1187 * count.
1188 */
1189 rc = pci_reenable_device(pdev);
1190 if (rc)
1191 dev_printk(KERN_ERR, &pdev->dev, "failed to enable "
1192 "device after resume (%d)\n", rc);
1193 } else
1194 rc = ata_pci_device_do_resume(pdev);
1195
1196 if (rc == 0)
1197 ata_host_resume(host);
1198
1199 return rc;
1200 }
1201 #endif
1202
1203 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1204 {
1205 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1206 }
1207
1208 #define AHCI_PCI_BAR 5
1209 #define AHCI_GLOBAL_CTL 0x04
1210 #define AHCI_ENABLE (1 << 31)
1211 static int piix_disable_ahci(struct pci_dev *pdev)
1212 {
1213 void __iomem *mmio;
1214 u32 tmp;
1215 int rc = 0;
1216
1217 /* BUG: pci_enable_device has not yet been called. This
1218 * works because this device is usually set up by BIOS.
1219 */
1220
1221 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1222 !pci_resource_len(pdev, AHCI_PCI_BAR))
1223 return 0;
1224
1225 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1226 if (!mmio)
1227 return -ENOMEM;
1228
1229 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1230 if (tmp & AHCI_ENABLE) {
1231 tmp &= ~AHCI_ENABLE;
1232 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1233
1234 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1235 if (tmp & AHCI_ENABLE)
1236 rc = -EIO;
1237 }
1238
1239 pci_iounmap(pdev, mmio);
1240 return rc;
1241 }
1242
1243 /**
1244 * piix_check_450nx_errata - Check for problem 450NX setup
1245 * @ata_dev: the PCI device to check
1246 *
1247 * Check for the present of 450NX errata #19 and errata #25. If
1248 * they are found return an error code so we can turn off DMA
1249 */
1250
1251 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1252 {
1253 struct pci_dev *pdev = NULL;
1254 u16 cfg;
1255 int no_piix_dma = 0;
1256
1257 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1258 /* Look for 450NX PXB. Check for problem configurations
1259 A PCI quirk checks bit 6 already */
1260 pci_read_config_word(pdev, 0x41, &cfg);
1261 /* Only on the original revision: IDE DMA can hang */
1262 if (pdev->revision == 0x00)
1263 no_piix_dma = 1;
1264 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1265 else if (cfg & (1<<14) && pdev->revision < 5)
1266 no_piix_dma = 2;
1267 }
1268 if (no_piix_dma)
1269 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
1270 if (no_piix_dma == 2)
1271 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
1272 return no_piix_dma;
1273 }
1274
1275 static void __devinit piix_init_pcs(struct ata_host *host,
1276 const struct piix_map_db *map_db)
1277 {
1278 struct pci_dev *pdev = to_pci_dev(host->dev);
1279 u16 pcs, new_pcs;
1280
1281 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1282
1283 new_pcs = pcs | map_db->port_enable;
1284
1285 if (new_pcs != pcs) {
1286 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1287 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1288 msleep(150);
1289 }
1290 }
1291
1292 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1293 struct ata_port_info *pinfo,
1294 const struct piix_map_db *map_db)
1295 {
1296 const int *map;
1297 int i, invalid_map = 0;
1298 u8 map_value;
1299
1300 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1301
1302 map = map_db->map[map_value & map_db->mask];
1303
1304 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
1305 for (i = 0; i < 4; i++) {
1306 switch (map[i]) {
1307 case RV:
1308 invalid_map = 1;
1309 printk(" XX");
1310 break;
1311
1312 case NA:
1313 printk(" --");
1314 break;
1315
1316 case IDE:
1317 WARN_ON((i & 1) || map[i + 1] != IDE);
1318 pinfo[i / 2] = piix_port_info[ich_pata_100];
1319 i++;
1320 printk(" IDE IDE");
1321 break;
1322
1323 default:
1324 printk(" P%d", map[i]);
1325 if (i & 1)
1326 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1327 break;
1328 }
1329 }
1330 printk(" ]\n");
1331
1332 if (invalid_map)
1333 dev_printk(KERN_ERR, &pdev->dev,
1334 "invalid MAP value %u\n", map_value);
1335
1336 return map;
1337 }
1338
1339 static bool piix_no_sidpr(struct ata_host *host)
1340 {
1341 struct pci_dev *pdev = to_pci_dev(host->dev);
1342
1343 /*
1344 * Samsung DB-P70 only has three ATA ports exposed and
1345 * curiously the unconnected first port reports link online
1346 * while not responding to SRST protocol causing excessive
1347 * detection delay.
1348 *
1349 * Unfortunately, the system doesn't carry enough DMI
1350 * information to identify the machine but does have subsystem
1351 * vendor and device set. As it's unclear whether the
1352 * subsystem vendor/device is used only for this specific
1353 * board, the port can't be disabled solely with the
1354 * information; however, turning off SIDPR access works around
1355 * the problem. Turn it off.
1356 *
1357 * This problem is reported in bnc#441240.
1358 *
1359 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1360 */
1361 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1362 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1363 pdev->subsystem_device == 0xb049) {
1364 dev_printk(KERN_WARNING, host->dev,
1365 "Samsung DB-P70 detected, disabling SIDPR\n");
1366 return true;
1367 }
1368
1369 return false;
1370 }
1371
1372 static int __devinit piix_init_sidpr(struct ata_host *host)
1373 {
1374 struct pci_dev *pdev = to_pci_dev(host->dev);
1375 struct piix_host_priv *hpriv = host->private_data;
1376 struct ata_link *link0 = &host->ports[0]->link;
1377 u32 scontrol;
1378 int i, rc;
1379
1380 /* check for availability */
1381 for (i = 0; i < 4; i++)
1382 if (hpriv->map[i] == IDE)
1383 return 0;
1384
1385 /* is it blacklisted? */
1386 if (piix_no_sidpr(host))
1387 return 0;
1388
1389 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1390 return 0;
1391
1392 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1393 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1394 return 0;
1395
1396 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1397 return 0;
1398
1399 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1400
1401 /* SCR access via SIDPR doesn't work on some configurations.
1402 * Give it a test drive by inhibiting power save modes which
1403 * we'll do anyway.
1404 */
1405 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1406
1407 /* if IPM is already 3, SCR access is probably working. Don't
1408 * un-inhibit power save modes as BIOS might have inhibited
1409 * them for a reason.
1410 */
1411 if ((scontrol & 0xf00) != 0x300) {
1412 scontrol |= 0x300;
1413 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1414 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1415
1416 if ((scontrol & 0xf00) != 0x300) {
1417 dev_printk(KERN_INFO, host->dev, "SCR access via "
1418 "SIDPR is available but doesn't work\n");
1419 return 0;
1420 }
1421 }
1422
1423 /* okay, SCRs available, set ops and ask libata for slave_link */
1424 for (i = 0; i < 2; i++) {
1425 struct ata_port *ap = host->ports[i];
1426
1427 ap->ops = &piix_sidpr_sata_ops;
1428
1429 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1430 rc = ata_slave_link_init(ap);
1431 if (rc)
1432 return rc;
1433 }
1434 }
1435
1436 return 0;
1437 }
1438
1439 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1440 {
1441 static const struct dmi_system_id sysids[] = {
1442 {
1443 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1444 * isn't used to boot the system which
1445 * disables the channel.
1446 */
1447 .ident = "M570U",
1448 .matches = {
1449 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1450 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1451 },
1452 },
1453
1454 { } /* terminate list */
1455 };
1456 struct pci_dev *pdev = to_pci_dev(host->dev);
1457 struct piix_host_priv *hpriv = host->private_data;
1458
1459 if (!dmi_check_system(sysids))
1460 return;
1461
1462 /* The datasheet says that bit 18 is NOOP but certain systems
1463 * seem to use it to disable a channel. Clear the bit on the
1464 * affected systems.
1465 */
1466 if (hpriv->saved_iocfg & (1 << 18)) {
1467 dev_printk(KERN_INFO, &pdev->dev,
1468 "applying IOCFG bit18 quirk\n");
1469 pci_write_config_dword(pdev, PIIX_IOCFG,
1470 hpriv->saved_iocfg & ~(1 << 18));
1471 }
1472 }
1473
1474 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1475 {
1476 static const struct dmi_system_id broken_systems[] = {
1477 {
1478 .ident = "HP Compaq 2510p",
1479 .matches = {
1480 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1481 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1482 },
1483 /* PCI slot number of the controller */
1484 .driver_data = (void *)0x1FUL,
1485 },
1486 {
1487 .ident = "HP Compaq nc6000",
1488 .matches = {
1489 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1490 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1491 },
1492 /* PCI slot number of the controller */
1493 .driver_data = (void *)0x1FUL,
1494 },
1495
1496 { } /* terminate list */
1497 };
1498 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1499
1500 if (dmi) {
1501 unsigned long slot = (unsigned long)dmi->driver_data;
1502 /* apply the quirk only to on-board controllers */
1503 return slot == PCI_SLOT(pdev->devfn);
1504 }
1505
1506 return false;
1507 }
1508
1509 /**
1510 * piix_init_one - Register PIIX ATA PCI device with kernel services
1511 * @pdev: PCI device to register
1512 * @ent: Entry in piix_pci_tbl matching with @pdev
1513 *
1514 * Called from kernel PCI layer. We probe for combined mode (sigh),
1515 * and then hand over control to libata, for it to do the rest.
1516 *
1517 * LOCKING:
1518 * Inherited from PCI layer (may sleep).
1519 *
1520 * RETURNS:
1521 * Zero on success, or -ERRNO value.
1522 */
1523
1524 static int __devinit piix_init_one(struct pci_dev *pdev,
1525 const struct pci_device_id *ent)
1526 {
1527 static int printed_version;
1528 struct device *dev = &pdev->dev;
1529 struct ata_port_info port_info[2];
1530 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1531 unsigned long port_flags;
1532 struct ata_host *host;
1533 struct piix_host_priv *hpriv;
1534 int rc;
1535
1536 if (!printed_version++)
1537 dev_printk(KERN_DEBUG, &pdev->dev,
1538 "version " DRV_VERSION "\n");
1539
1540 /* no hotplugging support for later devices (FIXME) */
1541 if (!in_module_init && ent->driver_data >= ich5_sata)
1542 return -ENODEV;
1543
1544 if (piix_broken_system_poweroff(pdev)) {
1545 piix_port_info[ent->driver_data].flags |=
1546 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1547 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1548 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1549 "on poweroff and hibernation\n");
1550 }
1551
1552 port_info[0] = piix_port_info[ent->driver_data];
1553 port_info[1] = piix_port_info[ent->driver_data];
1554
1555 port_flags = port_info[0].flags;
1556
1557 /* enable device and prepare host */
1558 rc = pcim_enable_device(pdev);
1559 if (rc)
1560 return rc;
1561
1562 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1563 if (!hpriv)
1564 return -ENOMEM;
1565 spin_lock_init(&hpriv->sidpr_lock);
1566
1567 /* Save IOCFG, this will be used for cable detection, quirk
1568 * detection and restoration on detach. This is necessary
1569 * because some ACPI implementations mess up cable related
1570 * bits on _STM. Reported on kernel bz#11879.
1571 */
1572 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1573
1574 /* ICH6R may be driven by either ata_piix or ahci driver
1575 * regardless of BIOS configuration. Make sure AHCI mode is
1576 * off.
1577 */
1578 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1579 rc = piix_disable_ahci(pdev);
1580 if (rc)
1581 return rc;
1582 }
1583
1584 /* SATA map init can change port_info, do it before prepping host */
1585 if (port_flags & ATA_FLAG_SATA)
1586 hpriv->map = piix_init_sata_map(pdev, port_info,
1587 piix_map_db_table[ent->driver_data]);
1588
1589 rc = ata_pci_sff_prepare_host(pdev, ppi, &host);
1590 if (rc)
1591 return rc;
1592 host->private_data = hpriv;
1593
1594 /* initialize controller */
1595 if (port_flags & ATA_FLAG_SATA) {
1596 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1597 rc = piix_init_sidpr(host);
1598 if (rc)
1599 return rc;
1600 }
1601
1602 /* apply IOCFG bit18 quirk */
1603 piix_iocfg_bit18_quirk(host);
1604
1605 /* On ICH5, some BIOSen disable the interrupt using the
1606 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1607 * On ICH6, this bit has the same effect, but only when
1608 * MSI is disabled (and it is disabled, as we don't use
1609 * message-signalled interrupts currently).
1610 */
1611 if (port_flags & PIIX_FLAG_CHECKINTR)
1612 pci_intx(pdev, 1);
1613
1614 if (piix_check_450nx_errata(pdev)) {
1615 /* This writes into the master table but it does not
1616 really matter for this errata as we will apply it to
1617 all the PIIX devices on the board */
1618 host->ports[0]->mwdma_mask = 0;
1619 host->ports[0]->udma_mask = 0;
1620 host->ports[1]->mwdma_mask = 0;
1621 host->ports[1]->udma_mask = 0;
1622 }
1623 host->flags |= ATA_HOST_PARALLEL_SCAN;
1624
1625 pci_set_master(pdev);
1626 return ata_pci_sff_activate_host(host, ata_sff_interrupt, &piix_sht);
1627 }
1628
1629 static void piix_remove_one(struct pci_dev *pdev)
1630 {
1631 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1632 struct piix_host_priv *hpriv = host->private_data;
1633
1634 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1635
1636 ata_pci_remove_one(pdev);
1637 }
1638
1639 static int __init piix_init(void)
1640 {
1641 int rc;
1642
1643 DPRINTK("pci_register_driver\n");
1644 rc = pci_register_driver(&piix_pci_driver);
1645 if (rc)
1646 return rc;
1647
1648 in_module_init = 0;
1649
1650 DPRINTK("done\n");
1651 return 0;
1652 }
1653
1654 static void __exit piix_exit(void)
1655 {
1656 pci_unregister_driver(&piix_pci_driver);
1657 }
1658
1659 module_init(piix_init);
1660 module_exit(piix_exit);
Linux ARM platform port for MOXA ART SoC