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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / gpu / drm / i915 / i915_drv.h
blob97163f7f2bad0fe33316c1bce3d397719b140a55
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include "i915_reg.h"
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
36
37 /* General customization:
38 */
39
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
45
46 enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49 };
50
51 enum plane {
52 PLANE_A = 0,
53 PLANE_B,
54 };
55
56 #define I915_NUM_PIPE 2
57
58 /* Interface history:
59 *
60 * 1.1: Original.
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
67 */
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
71
72 #define WATCH_COHERENCY 0
73 #define WATCH_BUF 0
74 #define WATCH_EXEC 0
75 #define WATCH_LRU 0
76 #define WATCH_RELOC 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
79
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
84
85 struct drm_i915_gem_phys_object {
86 int id;
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
90 };
91
92 typedef struct _drm_i915_ring_buffer {
93 unsigned long Size;
94 u8 *virtual_start;
95 int head;
96 int tail;
97 int space;
98 drm_local_map_t map;
99 struct drm_gem_object *ring_obj;
100 } drm_i915_ring_buffer_t;
101
102 struct mem_block {
103 struct mem_block *next;
104 struct mem_block *prev;
105 int start;
106 int size;
107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
108 };
109
110 struct opregion_header;
111 struct opregion_acpi;
112 struct opregion_swsci;
113 struct opregion_asle;
114
115 struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
120 int enabled;
121 };
122
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
126 };
127 #define I915_FENCE_REG_NONE -1
128
129 struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
131 };
132
133 struct sdvo_device_mapping {
134 u8 dvo_port;
135 u8 slave_addr;
136 u8 dvo_wiring;
137 u8 initialized;
138 };
139
140 struct drm_i915_error_state {
141 u32 eir;
142 u32 pgtbl_er;
143 u32 pipeastat;
144 u32 pipebstat;
145 u32 ipeir;
146 u32 ipehr;
147 u32 instdone;
148 u32 acthd;
149 u32 instpm;
150 u32 instps;
151 u32 instdone1;
152 u32 seqno;
153 struct timeval time;
154 };
155
156 struct drm_i915_display_funcs {
157 void (*dpms)(struct drm_crtc *crtc, int mode);
158 bool (*fbc_enabled)(struct drm_crtc *crtc);
159 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
160 void (*disable_fbc)(struct drm_device *dev);
161 int (*get_display_clock_speed)(struct drm_device *dev);
162 int (*get_fifo_size)(struct drm_device *dev, int plane);
163 void (*update_wm)(struct drm_device *dev, int planea_clock,
164 int planeb_clock, int sr_hdisplay, int pixel_size);
165 /* clock updates for mode set */
166 /* cursor updates */
167 /* render clock increase/decrease */
168 /* display clock increase/decrease */
169 /* pll clock increase/decrease */
170 /* clock gating init */
171 };
172
173 typedef struct drm_i915_private {
174 struct drm_device *dev;
175
176 int has_gem;
177
178 void __iomem *regs;
179
180 struct pci_dev *bridge_dev;
181 drm_i915_ring_buffer_t ring;
182
183 drm_dma_handle_t *status_page_dmah;
184 void *hw_status_page;
185 dma_addr_t dma_status_page;
186 uint32_t counter;
187 unsigned int status_gfx_addr;
188 drm_local_map_t hws_map;
189 struct drm_gem_object *hws_obj;
190
191 struct resource mch_res;
192
193 unsigned int cpp;
194 int back_offset;
195 int front_offset;
196 int current_page;
197 int page_flipping;
198
199 wait_queue_head_t irq_queue;
200 atomic_t irq_received;
201 /** Protects user_irq_refcount and irq_mask_reg */
202 spinlock_t user_irq_lock;
203 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
204 int user_irq_refcount;
205 u32 trace_irq_seqno;
206 /** Cached value of IMR to avoid reads in updating the bitfield */
207 u32 irq_mask_reg;
208 u32 pipestat[2];
209 /** splitted irq regs for graphics and display engine on IGDNG,
210 irq_mask_reg is still used for display irq. */
211 u32 gt_irq_mask_reg;
212 u32 gt_irq_enable_reg;
213 u32 de_irq_enable_reg;
214
215 u32 hotplug_supported_mask;
216 struct work_struct hotplug_work;
217
218 int tex_lru_log_granularity;
219 int allow_batchbuffer;
220 struct mem_block *agp_heap;
221 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
222 int vblank_pipe;
223
224 /* For hangcheck timer */
225 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
226 struct timer_list hangcheck_timer;
227 int hangcheck_count;
228 uint32_t last_acthd;
229
230 bool cursor_needs_physical;
231
232 struct drm_mm vram;
233
234 unsigned long cfb_size;
235 unsigned long cfb_pitch;
236 int cfb_fence;
237 int cfb_plane;
238
239 int irq_enabled;
240
241 struct intel_opregion opregion;
242
243 /* LVDS info */
244 int backlight_duty_cycle; /* restore backlight to this value */
245 bool panel_wants_dither;
246 struct drm_display_mode *panel_fixed_mode;
247 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
248 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
249
250 /* Feature bits from the VBIOS */
251 unsigned int int_tv_support:1;
252 unsigned int lvds_dither:1;
253 unsigned int lvds_vbt:1;
254 unsigned int int_crt_support:1;
255 unsigned int lvds_use_ssc:1;
256 unsigned int edp_support:1;
257 int lvds_ssc_freq;
258
259 struct notifier_block lid_notifier;
260
261 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
262 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
263 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
264 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
265
266 unsigned int fsb_freq, mem_freq;
267
268 spinlock_t error_lock;
269 struct drm_i915_error_state *first_error;
270 struct work_struct error_work;
271 struct workqueue_struct *wq;
272
273 /* Display functions */
274 struct drm_i915_display_funcs display;
275
276 /* Register state */
277 bool modeset_on_lid;
278 u8 saveLBB;
279 u32 saveDSPACNTR;
280 u32 saveDSPBCNTR;
281 u32 saveDSPARB;
282 u32 saveRENDERSTANDBY;
283 u32 saveHWS;
284 u32 savePIPEACONF;
285 u32 savePIPEBCONF;
286 u32 savePIPEASRC;
287 u32 savePIPEBSRC;
288 u32 saveFPA0;
289 u32 saveFPA1;
290 u32 saveDPLL_A;
291 u32 saveDPLL_A_MD;
292 u32 saveHTOTAL_A;
293 u32 saveHBLANK_A;
294 u32 saveHSYNC_A;
295 u32 saveVTOTAL_A;
296 u32 saveVBLANK_A;
297 u32 saveVSYNC_A;
298 u32 saveBCLRPAT_A;
299 u32 saveTRANSACONF;
300 u32 saveTRANS_HTOTAL_A;
301 u32 saveTRANS_HBLANK_A;
302 u32 saveTRANS_HSYNC_A;
303 u32 saveTRANS_VTOTAL_A;
304 u32 saveTRANS_VBLANK_A;
305 u32 saveTRANS_VSYNC_A;
306 u32 savePIPEASTAT;
307 u32 saveDSPASTRIDE;
308 u32 saveDSPASIZE;
309 u32 saveDSPAPOS;
310 u32 saveDSPAADDR;
311 u32 saveDSPASURF;
312 u32 saveDSPATILEOFF;
313 u32 savePFIT_PGM_RATIOS;
314 u32 saveBLC_HIST_CTL;
315 u32 saveBLC_PWM_CTL;
316 u32 saveBLC_PWM_CTL2;
317 u32 saveBLC_CPU_PWM_CTL;
318 u32 saveBLC_CPU_PWM_CTL2;
319 u32 saveFPB0;
320 u32 saveFPB1;
321 u32 saveDPLL_B;
322 u32 saveDPLL_B_MD;
323 u32 saveHTOTAL_B;
324 u32 saveHBLANK_B;
325 u32 saveHSYNC_B;
326 u32 saveVTOTAL_B;
327 u32 saveVBLANK_B;
328 u32 saveVSYNC_B;
329 u32 saveBCLRPAT_B;
330 u32 saveTRANSBCONF;
331 u32 saveTRANS_HTOTAL_B;
332 u32 saveTRANS_HBLANK_B;
333 u32 saveTRANS_HSYNC_B;
334 u32 saveTRANS_VTOTAL_B;
335 u32 saveTRANS_VBLANK_B;
336 u32 saveTRANS_VSYNC_B;
337 u32 savePIPEBSTAT;
338 u32 saveDSPBSTRIDE;
339 u32 saveDSPBSIZE;
340 u32 saveDSPBPOS;
341 u32 saveDSPBADDR;
342 u32 saveDSPBSURF;
343 u32 saveDSPBTILEOFF;
344 u32 saveVGA0;
345 u32 saveVGA1;
346 u32 saveVGA_PD;
347 u32 saveVGACNTRL;
348 u32 saveADPA;
349 u32 saveLVDS;
350 u32 savePP_ON_DELAYS;
351 u32 savePP_OFF_DELAYS;
352 u32 saveDVOA;
353 u32 saveDVOB;
354 u32 saveDVOC;
355 u32 savePP_ON;
356 u32 savePP_OFF;
357 u32 savePP_CONTROL;
358 u32 savePP_DIVISOR;
359 u32 savePFIT_CONTROL;
360 u32 save_palette_a[256];
361 u32 save_palette_b[256];
362 u32 saveDPFC_CB_BASE;
363 u32 saveFBC_CFB_BASE;
364 u32 saveFBC_LL_BASE;
365 u32 saveFBC_CONTROL;
366 u32 saveFBC_CONTROL2;
367 u32 saveIER;
368 u32 saveIIR;
369 u32 saveIMR;
370 u32 saveDEIER;
371 u32 saveDEIMR;
372 u32 saveGTIER;
373 u32 saveGTIMR;
374 u32 saveFDI_RXA_IMR;
375 u32 saveFDI_RXB_IMR;
376 u32 saveCACHE_MODE_0;
377 u32 saveD_STATE;
378 u32 saveDSPCLK_GATE_D;
379 u32 saveMI_ARB_STATE;
380 u32 saveSWF0[16];
381 u32 saveSWF1[16];
382 u32 saveSWF2[3];
383 u8 saveMSR;
384 u8 saveSR[8];
385 u8 saveGR[25];
386 u8 saveAR_INDEX;
387 u8 saveAR[21];
388 u8 saveDACMASK;
389 u8 saveCR[37];
390 uint64_t saveFENCE[16];
391 u32 saveCURACNTR;
392 u32 saveCURAPOS;
393 u32 saveCURABASE;
394 u32 saveCURBCNTR;
395 u32 saveCURBPOS;
396 u32 saveCURBBASE;
397 u32 saveCURSIZE;
398 u32 saveDP_B;
399 u32 saveDP_C;
400 u32 saveDP_D;
401 u32 savePIPEA_GMCH_DATA_M;
402 u32 savePIPEB_GMCH_DATA_M;
403 u32 savePIPEA_GMCH_DATA_N;
404 u32 savePIPEB_GMCH_DATA_N;
405 u32 savePIPEA_DP_LINK_M;
406 u32 savePIPEB_DP_LINK_M;
407 u32 savePIPEA_DP_LINK_N;
408 u32 savePIPEB_DP_LINK_N;
409 u32 saveFDI_RXA_CTL;
410 u32 saveFDI_TXA_CTL;
411 u32 saveFDI_RXB_CTL;
412 u32 saveFDI_TXB_CTL;
413 u32 savePFA_CTL_1;
414 u32 savePFB_CTL_1;
415 u32 savePFA_WIN_SZ;
416 u32 savePFB_WIN_SZ;
417 u32 savePFA_WIN_POS;
418 u32 savePFB_WIN_POS;
419 u32 savePCH_DREF_CONTROL;
420 u32 saveDISP_ARB_CTL;
421 u32 savePIPEA_DATA_M1;
422 u32 savePIPEA_DATA_N1;
423 u32 savePIPEA_LINK_M1;
424 u32 savePIPEA_LINK_N1;
425 u32 savePIPEB_DATA_M1;
426 u32 savePIPEB_DATA_N1;
427 u32 savePIPEB_LINK_M1;
428 u32 savePIPEB_LINK_N1;
429
430 struct {
431 struct drm_mm gtt_space;
432
433 struct io_mapping *gtt_mapping;
434 int gtt_mtrr;
435
436 /**
437 * Membership on list of all loaded devices, used to evict
438 * inactive buffers under memory pressure.
439 *
440 * Modifications should only be done whilst holding the
441 * shrink_list_lock spinlock.
442 */
443 struct list_head shrink_list;
444
445 /**
446 * List of objects currently involved in rendering from the
447 * ringbuffer.
448 *
449 * Includes buffers having the contents of their GPU caches
450 * flushed, not necessarily primitives. last_rendering_seqno
451 * represents when the rendering involved will be completed.
452 *
453 * A reference is held on the buffer while on this list.
454 */
455 spinlock_t active_list_lock;
456 struct list_head active_list;
457
458 /**
459 * List of objects which are not in the ringbuffer but which
460 * still have a write_domain which needs to be flushed before
461 * unbinding.
462 *
463 * last_rendering_seqno is 0 while an object is in this list.
464 *
465 * A reference is held on the buffer while on this list.
466 */
467 struct list_head flushing_list;
468
469 /**
470 * List of objects currently pending a GPU write flush.
471 *
472 * All elements on this list will belong to either the
473 * active_list or flushing_list, last_rendering_seqno can
474 * be used to differentiate between the two elements.
475 */
476 struct list_head gpu_write_list;
477
478 /**
479 * LRU list of objects which are not in the ringbuffer and
480 * are ready to unbind, but are still in the GTT.
481 *
482 * last_rendering_seqno is 0 while an object is in this list.
483 *
484 * A reference is not held on the buffer while on this list,
485 * as merely being GTT-bound shouldn't prevent its being
486 * freed, and we'll pull it off the list in the free path.
487 */
488 struct list_head inactive_list;
489
490 /** LRU list of objects with fence regs on them. */
491 struct list_head fence_list;
492
493 /**
494 * List of breadcrumbs associated with GPU requests currently
495 * outstanding.
496 */
497 struct list_head request_list;
498
499 /**
500 * We leave the user IRQ off as much as possible,
501 * but this means that requests will finish and never
502 * be retired once the system goes idle. Set a timer to
503 * fire periodically while the ring is running. When it
504 * fires, go retire requests.
505 */
506 struct delayed_work retire_work;
507
508 uint32_t next_gem_seqno;
509
510 /**
511 * Waiting sequence number, if any
512 */
513 uint32_t waiting_gem_seqno;
514
515 /**
516 * Last seq seen at irq time
517 */
518 uint32_t irq_gem_seqno;
519
520 /**
521 * Flag if the X Server, and thus DRM, is not currently in
522 * control of the device.
523 *
524 * This is set between LeaveVT and EnterVT. It needs to be
525 * replaced with a semaphore. It also needs to be
526 * transitioned away from for kernel modesetting.
527 */
528 int suspended;
529
530 /**
531 * Flag if the hardware appears to be wedged.
532 *
533 * This is set when attempts to idle the device timeout.
534 * It prevents command submission from occuring and makes
535 * every pending request fail
536 */
537 atomic_t wedged;
538
539 /** Bit 6 swizzling required for X tiling */
540 uint32_t bit_6_swizzle_x;
541 /** Bit 6 swizzling required for Y tiling */
542 uint32_t bit_6_swizzle_y;
543
544 /* storage for physical objects */
545 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
546 } mm;
547 struct sdvo_device_mapping sdvo_mappings[2];
548 /* indicate whether the LVDS_BORDER should be enabled or not */
549 unsigned int lvds_border_bits;
550
551 /* Reclocking support */
552 bool render_reclock_avail;
553 bool lvds_downclock_avail;
554 struct work_struct idle_work;
555 struct timer_list idle_timer;
556 bool busy;
557 u16 orig_clock;
558 int child_dev_num;
559 struct child_device_config *child_dev;
560 struct drm_connector *int_lvds_connector;
561 } drm_i915_private_t;
562
563 /** driver private structure attached to each drm_gem_object */
564 struct drm_i915_gem_object {
565 struct drm_gem_object *obj;
566
567 /** Current space allocated to this object in the GTT, if any. */
568 struct drm_mm_node *gtt_space;
569
570 /** This object's place on the active/flushing/inactive lists */
571 struct list_head list;
572 /** This object's place on GPU write list */
573 struct list_head gpu_write_list;
574
575 /** This object's place on the fenced object LRU */
576 struct list_head fence_list;
577
578 /**
579 * This is set if the object is on the active or flushing lists
580 * (has pending rendering), and is not set if it's on inactive (ready
581 * to be unbound).
582 */
583 int active;
584
585 /**
586 * This is set if the object has been written to since last bound
587 * to the GTT
588 */
589 int dirty;
590
591 /** AGP memory structure for our GTT binding. */
592 DRM_AGP_MEM *agp_mem;
593
594 struct page **pages;
595 int pages_refcount;
596
597 /**
598 * Current offset of the object in GTT space.
599 *
600 * This is the same as gtt_space->start
601 */
602 uint32_t gtt_offset;
603
604 /**
605 * Fake offset for use by mmap(2)
606 */
607 uint64_t mmap_offset;
608
609 /**
610 * Fence register bits (if any) for this object. Will be set
611 * as needed when mapped into the GTT.
612 * Protected by dev->struct_mutex.
613 */
614 int fence_reg;
615
616 /** How many users have pinned this object in GTT space */
617 int pin_count;
618
619 /** Breadcrumb of last rendering to the buffer. */
620 uint32_t last_rendering_seqno;
621
622 /** Current tiling mode for the object. */
623 uint32_t tiling_mode;
624 uint32_t stride;
625
626 /** Record of address bit 17 of each page at last unbind. */
627 long *bit_17;
628
629 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
630 uint32_t agp_type;
631
632 /**
633 * If present, while GEM_DOMAIN_CPU is in the read domain this array
634 * flags which individual pages are valid.
635 */
636 uint8_t *page_cpu_valid;
637
638 /** User space pin count and filp owning the pin */
639 uint32_t user_pin_count;
640 struct drm_file *pin_filp;
641
642 /** for phy allocated objects */
643 struct drm_i915_gem_phys_object *phys_obj;
644
645 /**
646 * Used for checking the object doesn't appear more than once
647 * in an execbuffer object list.
648 */
649 int in_execbuffer;
650
651 /**
652 * Advice: are the backing pages purgeable?
653 */
654 int madv;
655 };
656
657 /**
658 * Request queue structure.
659 *
660 * The request queue allows us to note sequence numbers that have been emitted
661 * and may be associated with active buffers to be retired.
662 *
663 * By keeping this list, we can avoid having to do questionable
664 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
665 * an emission time with seqnos for tracking how far ahead of the GPU we are.
666 */
667 struct drm_i915_gem_request {
668 /** GEM sequence number associated with this request. */
669 uint32_t seqno;
670
671 /** Time at which this request was emitted, in jiffies. */
672 unsigned long emitted_jiffies;
673
674 /** global list entry for this request */
675 struct list_head list;
676
677 /** file_priv list entry for this request */
678 struct list_head client_list;
679 };
680
681 struct drm_i915_file_private {
682 struct {
683 struct list_head request_list;
684 } mm;
685 };
686
687 enum intel_chip_family {
688 CHIP_I8XX = 0x01,
689 CHIP_I9XX = 0x02,
690 CHIP_I915 = 0x04,
691 CHIP_I965 = 0x08,
692 };
693
694 extern struct drm_ioctl_desc i915_ioctls[];
695 extern int i915_max_ioctl;
696 extern unsigned int i915_fbpercrtc;
697 extern unsigned int i915_powersave;
698
699 extern void i915_save_display(struct drm_device *dev);
700 extern void i915_restore_display(struct drm_device *dev);
701 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
702 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
703
704 /* i915_dma.c */
705 extern void i915_kernel_lost_context(struct drm_device * dev);
706 extern int i915_driver_load(struct drm_device *, unsigned long flags);
707 extern int i915_driver_unload(struct drm_device *);
708 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
709 extern void i915_driver_lastclose(struct drm_device * dev);
710 extern void i915_driver_preclose(struct drm_device *dev,
711 struct drm_file *file_priv);
712 extern void i915_driver_postclose(struct drm_device *dev,
713 struct drm_file *file_priv);
714 extern int i915_driver_device_is_agp(struct drm_device * dev);
715 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
716 unsigned long arg);
717 extern int i915_emit_box(struct drm_device *dev,
718 struct drm_clip_rect *boxes,
719 int i, int DR1, int DR4);
720 extern int i965_reset(struct drm_device *dev, u8 flags);
721
722 /* i915_irq.c */
723 void i915_hangcheck_elapsed(unsigned long data);
724 extern int i915_irq_emit(struct drm_device *dev, void *data,
725 struct drm_file *file_priv);
726 extern int i915_irq_wait(struct drm_device *dev, void *data,
727 struct drm_file *file_priv);
728 void i915_user_irq_get(struct drm_device *dev);
729 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
730 void i915_user_irq_put(struct drm_device *dev);
731 extern void i915_enable_interrupt (struct drm_device *dev);
732
733 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
734 extern void i915_driver_irq_preinstall(struct drm_device * dev);
735 extern int i915_driver_irq_postinstall(struct drm_device *dev);
736 extern void i915_driver_irq_uninstall(struct drm_device * dev);
737 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
738 struct drm_file *file_priv);
739 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
740 struct drm_file *file_priv);
741 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
742 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
743 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
744 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
745 extern int i915_vblank_swap(struct drm_device *dev, void *data,
746 struct drm_file *file_priv);
747 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
748
749 void
750 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
751
752 void
753 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
754
755
756 /* i915_mem.c */
757 extern int i915_mem_alloc(struct drm_device *dev, void *data,
758 struct drm_file *file_priv);
759 extern int i915_mem_free(struct drm_device *dev, void *data,
760 struct drm_file *file_priv);
761 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
762 struct drm_file *file_priv);
763 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
764 struct drm_file *file_priv);
765 extern void i915_mem_takedown(struct mem_block **heap);
766 extern void i915_mem_release(struct drm_device * dev,
767 struct drm_file *file_priv, struct mem_block *heap);
768 /* i915_gem.c */
769 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
770 struct drm_file *file_priv);
771 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
772 struct drm_file *file_priv);
773 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
774 struct drm_file *file_priv);
775 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
776 struct drm_file *file_priv);
777 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
778 struct drm_file *file_priv);
779 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
780 struct drm_file *file_priv);
781 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
782 struct drm_file *file_priv);
783 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
784 struct drm_file *file_priv);
785 int i915_gem_execbuffer(struct drm_device *dev, void *data,
786 struct drm_file *file_priv);
787 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
788 struct drm_file *file_priv);
789 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
790 struct drm_file *file_priv);
791 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
792 struct drm_file *file_priv);
793 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
794 struct drm_file *file_priv);
795 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
796 struct drm_file *file_priv);
797 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
798 struct drm_file *file_priv);
799 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
800 struct drm_file *file_priv);
801 int i915_gem_set_tiling(struct drm_device *dev, void *data,
802 struct drm_file *file_priv);
803 int i915_gem_get_tiling(struct drm_device *dev, void *data,
804 struct drm_file *file_priv);
805 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
806 struct drm_file *file_priv);
807 void i915_gem_load(struct drm_device *dev);
808 int i915_gem_init_object(struct drm_gem_object *obj);
809 void i915_gem_free_object(struct drm_gem_object *obj);
810 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
811 void i915_gem_object_unpin(struct drm_gem_object *obj);
812 int i915_gem_object_unbind(struct drm_gem_object *obj);
813 void i915_gem_release_mmap(struct drm_gem_object *obj);
814 void i915_gem_lastclose(struct drm_device *dev);
815 uint32_t i915_get_gem_seqno(struct drm_device *dev);
816 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
817 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
818 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
819 void i915_gem_retire_requests(struct drm_device *dev);
820 void i915_gem_retire_work_handler(struct work_struct *work);
821 void i915_gem_clflush_object(struct drm_gem_object *obj);
822 int i915_gem_object_set_domain(struct drm_gem_object *obj,
823 uint32_t read_domains,
824 uint32_t write_domain);
825 int i915_gem_init_ringbuffer(struct drm_device *dev);
826 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
827 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
828 unsigned long end);
829 int i915_gem_idle(struct drm_device *dev);
830 int i915_lp_ring_sync(struct drm_device *dev);
831 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
832 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
833 int write);
834 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
835 int i915_gem_attach_phys_object(struct drm_device *dev,
836 struct drm_gem_object *obj, int id);
837 void i915_gem_detach_phys_object(struct drm_device *dev,
838 struct drm_gem_object *obj);
839 void i915_gem_free_all_phys_object(struct drm_device *dev);
840 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
841 void i915_gem_object_put_pages(struct drm_gem_object *obj);
842 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
843
844 void i915_gem_shrinker_init(void);
845 void i915_gem_shrinker_exit(void);
846
847 /* i915_gem_tiling.c */
848 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
849 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
850 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
851
852 /* i915_gem_debug.c */
853 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
854 const char *where, uint32_t mark);
855 #if WATCH_INACTIVE
856 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
857 #else
858 #define i915_verify_inactive(dev, file, line)
859 #endif
860 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
861 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
862 const char *where, uint32_t mark);
863 void i915_dump_lru(struct drm_device *dev, const char *where);
864
865 /* i915_debugfs.c */
866 int i915_debugfs_init(struct drm_minor *minor);
867 void i915_debugfs_cleanup(struct drm_minor *minor);
868
869 /* i915_suspend.c */
870 extern int i915_save_state(struct drm_device *dev);
871 extern int i915_restore_state(struct drm_device *dev);
872
873 /* i915_suspend.c */
874 extern int i915_save_state(struct drm_device *dev);
875 extern int i915_restore_state(struct drm_device *dev);
876
877 #ifdef CONFIG_ACPI
878 /* i915_opregion.c */
879 extern int intel_opregion_init(struct drm_device *dev, int resume);
880 extern void intel_opregion_free(struct drm_device *dev, int suspend);
881 extern void opregion_asle_intr(struct drm_device *dev);
882 extern void opregion_enable_asle(struct drm_device *dev);
883 #else
884 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
885 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
886 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
887 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
888 #endif
889
890 /* modesetting */
891 extern void intel_modeset_init(struct drm_device *dev);
892 extern void intel_modeset_cleanup(struct drm_device *dev);
893 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
894 extern void i8xx_disable_fbc(struct drm_device *dev);
895 extern void g4x_disable_fbc(struct drm_device *dev);
896
897 /**
898 * Lock test for when it's just for synchronization of ring access.
899 *
900 * In that case, we don't need to do it when GEM is initialized as nobody else
901 * has access to the ring.
902 */
903 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
904 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
905 LOCK_TEST_WITH_RETURN(dev, file_priv); \
906 } while (0)
907
908 #define I915_READ(reg) readl(dev_priv->regs + (reg))
909 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
910 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
911 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
912 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
913 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
914 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
915 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
916 #define POSTING_READ(reg) (void)I915_READ(reg)
917
918 #define I915_VERBOSE 0
919
920 #define RING_LOCALS volatile unsigned int *ring_virt__;
921
922 #define BEGIN_LP_RING(n) do { \
923 int bytes__ = 4*(n); \
924 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
925 /* a wrap must occur between instructions so pad beforehand */ \
926 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
927 i915_wrap_ring(dev); \
928 if (unlikely (dev_priv->ring.space < bytes__)) \
929 i915_wait_ring(dev, bytes__, __func__); \
930 ring_virt__ = (unsigned int *) \
931 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
932 dev_priv->ring.tail += bytes__; \
933 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
934 dev_priv->ring.space -= bytes__; \
935 } while (0)
936
937 #define OUT_RING(n) do { \
938 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
939 *ring_virt__++ = (n); \
940 } while (0)
941
942 #define ADVANCE_LP_RING() do { \
943 if (I915_VERBOSE) \
944 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
945 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
946 } while(0)
947
948 /**
949 * Reads a dword out of the status page, which is written to from the command
950 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
951 * MI_STORE_DATA_IMM.
952 *
953 * The following dwords have a reserved meaning:
954 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
955 * 0x04: ring 0 head pointer
956 * 0x05: ring 1 head pointer (915-class)
957 * 0x06: ring 2 head pointer (915-class)
958 * 0x10-0x1b: Context status DWords (GM45)
959 * 0x1f: Last written status offset. (GM45)
960 *
961 * The area from dword 0x20 to 0x3ff is available for driver usage.
962 */
963 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
964 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
965 #define I915_GEM_HWS_INDEX 0x20
966 #define I915_BREADCRUMB_INDEX 0x21
967
968 extern int i915_wrap_ring(struct drm_device * dev);
969 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
970
971 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
972 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
973 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
974 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
975 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
976 #define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || IS_I865G(dev))
977
978 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
979 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
980 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
981 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
982 (dev)->pci_device == 0x27AE)
983 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
984 (dev)->pci_device == 0x2982 || \
985 (dev)->pci_device == 0x2992 || \
986 (dev)->pci_device == 0x29A2 || \
987 (dev)->pci_device == 0x2A02 || \
988 (dev)->pci_device == 0x2A12 || \
989 (dev)->pci_device == 0x2A42 || \
990 (dev)->pci_device == 0x2E02 || \
991 (dev)->pci_device == 0x2E12 || \
992 (dev)->pci_device == 0x2E22 || \
993 (dev)->pci_device == 0x2E32 || \
994 (dev)->pci_device == 0x2E42 || \
995 (dev)->pci_device == 0x0042 || \
996 (dev)->pci_device == 0x0046)
997
998 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
999 (dev)->pci_device == 0x2A12)
1000
1001 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1002
1003 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
1004 (dev)->pci_device == 0x2E12 || \
1005 (dev)->pci_device == 0x2E22 || \
1006 (dev)->pci_device == 0x2E32 || \
1007 (dev)->pci_device == 0x2E42 || \
1008 IS_GM45(dev))
1009
1010 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
1011 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
1012 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
1013
1014 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1015 (dev)->pci_device == 0x29B2 || \
1016 (dev)->pci_device == 0x29D2 || \
1017 (IS_IGD(dev)))
1018
1019 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
1020 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
1021 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
1022
1023 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1024 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
1025 IS_IGDNG(dev))
1026
1027 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1028 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
1029 IS_IGD(dev) || IS_IGDNG_M(dev))
1030
1031 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
1032 IS_IGDNG(dev))
1033 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1034 * rows, which changed the alignment requirements and fence programming.
1035 */
1036 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1037 IS_I915GM(dev)))
1038 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_IGD(dev))
1039 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1040 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1041 #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
1042 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1043 !IS_IGDNG(dev) && !IS_IGD(dev))
1044 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
1045 /* dsparb controlled by hw only */
1046 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1047
1048 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
1049 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1050 #define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
1051 (IS_I9XX(dev) || IS_GM45(dev)) && \
1052 !IS_IGD(dev) && \
1053 !IS_IGDNG(dev))
1054
1055 #define PRIMARY_RINGBUFFER_SIZE (128*1024)
1056
1057 #endif
Linux ARM platform port for MOXA ART SoC