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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / gpu / drm / i915 / i915_irq.c
blob63f28adf65093fa95f383830c6a59173a67f76c8
1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include <linux/sysrq.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drm.h"
33 #include "i915_drv.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 #define MAX_NOPID ((u32)~0)
38
39 /**
40 * Interrupts that are always left unmasked.
41 *
42 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
43 * we leave them always unmasked in IMR and then control enabling them through
44 * PIPESTAT alone.
45 */
46 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
47 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
48 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
49 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
50
51 /** Interrupts that we mask and unmask at runtime. */
52 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
53
54 #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
55 PIPE_VBLANK_INTERRUPT_STATUS)
56
57 #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
58 PIPE_VBLANK_INTERRUPT_ENABLE)
59
60 #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
61 DRM_I915_VBLANK_PIPE_B)
62
63 void
64 igdng_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
65 {
66 if ((dev_priv->gt_irq_mask_reg & mask) != 0) {
67 dev_priv->gt_irq_mask_reg &= ~mask;
68 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
69 (void) I915_READ(GTIMR);
70 }
71 }
72
73 static inline void
74 igdng_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask)
75 {
76 if ((dev_priv->gt_irq_mask_reg & mask) != mask) {
77 dev_priv->gt_irq_mask_reg |= mask;
78 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
79 (void) I915_READ(GTIMR);
80 }
81 }
82
83 /* For display hotplug interrupt */
84 void
85 igdng_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
86 {
87 if ((dev_priv->irq_mask_reg & mask) != 0) {
88 dev_priv->irq_mask_reg &= ~mask;
89 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
90 (void) I915_READ(DEIMR);
91 }
92 }
93
94 static inline void
95 igdng_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
96 {
97 if ((dev_priv->irq_mask_reg & mask) != mask) {
98 dev_priv->irq_mask_reg |= mask;
99 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
100 (void) I915_READ(DEIMR);
101 }
102 }
103
104 void
105 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
106 {
107 if ((dev_priv->irq_mask_reg & mask) != 0) {
108 dev_priv->irq_mask_reg &= ~mask;
109 I915_WRITE(IMR, dev_priv->irq_mask_reg);
110 (void) I915_READ(IMR);
111 }
112 }
113
114 static inline void
115 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
116 {
117 if ((dev_priv->irq_mask_reg & mask) != mask) {
118 dev_priv->irq_mask_reg |= mask;
119 I915_WRITE(IMR, dev_priv->irq_mask_reg);
120 (void) I915_READ(IMR);
121 }
122 }
123
124 static inline u32
125 i915_pipestat(int pipe)
126 {
127 if (pipe == 0)
128 return PIPEASTAT;
129 if (pipe == 1)
130 return PIPEBSTAT;
131 BUG();
132 }
133
134 void
135 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
136 {
137 if ((dev_priv->pipestat[pipe] & mask) != mask) {
138 u32 reg = i915_pipestat(pipe);
139
140 dev_priv->pipestat[pipe] |= mask;
141 /* Enable the interrupt, clear any pending status */
142 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
143 (void) I915_READ(reg);
144 }
145 }
146
147 void
148 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
149 {
150 if ((dev_priv->pipestat[pipe] & mask) != 0) {
151 u32 reg = i915_pipestat(pipe);
152
153 dev_priv->pipestat[pipe] &= ~mask;
154 I915_WRITE(reg, dev_priv->pipestat[pipe]);
155 (void) I915_READ(reg);
156 }
157 }
158
159 /**
160 * i915_pipe_enabled - check if a pipe is enabled
161 * @dev: DRM device
162 * @pipe: pipe to check
163 *
164 * Reading certain registers when the pipe is disabled can hang the chip.
165 * Use this routine to make sure the PLL is running and the pipe is active
166 * before reading such registers if unsure.
167 */
168 static int
169 i915_pipe_enabled(struct drm_device *dev, int pipe)
170 {
171 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
172 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
173
174 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
175 return 1;
176
177 return 0;
178 }
179
180 /* Called from drm generic code, passed a 'crtc', which
181 * we use as a pipe index
182 */
183 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
184 {
185 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
186 unsigned long high_frame;
187 unsigned long low_frame;
188 u32 high1, high2, low, count;
189
190 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
191 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
192
193 if (!i915_pipe_enabled(dev, pipe)) {
194 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
195 return 0;
196 }
197
198 /*
199 * High & low register fields aren't synchronized, so make sure
200 * we get a low value that's stable across two reads of the high
201 * register.
202 */
203 do {
204 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
205 PIPE_FRAME_HIGH_SHIFT);
206 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
207 PIPE_FRAME_LOW_SHIFT);
208 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
209 PIPE_FRAME_HIGH_SHIFT);
210 } while (high1 != high2);
211
212 count = (high1 << 8) | low;
213
214 return count;
215 }
216
217 u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
218 {
219 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
220 int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45;
221
222 if (!i915_pipe_enabled(dev, pipe)) {
223 DRM_DEBUG("trying to get vblank count for disabled pipe %d\n", pipe);
224 return 0;
225 }
226
227 return I915_READ(reg);
228 }
229
230 /*
231 * Handle hotplug events outside the interrupt handler proper.
232 */
233 static void i915_hotplug_work_func(struct work_struct *work)
234 {
235 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
236 hotplug_work);
237 struct drm_device *dev = dev_priv->dev;
238 struct drm_mode_config *mode_config = &dev->mode_config;
239 struct drm_connector *connector;
240
241 if (mode_config->num_connector) {
242 list_for_each_entry(connector, &mode_config->connector_list, head) {
243 struct intel_output *intel_output = to_intel_output(connector);
244
245 if (intel_output->hot_plug)
246 (*intel_output->hot_plug) (intel_output);
247 }
248 }
249 /* Just fire off a uevent and let userspace tell us what to do */
250 drm_sysfs_hotplug_event(dev);
251 }
252
253 irqreturn_t igdng_irq_handler(struct drm_device *dev)
254 {
255 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
256 int ret = IRQ_NONE;
257 u32 de_iir, gt_iir, de_ier;
258 struct drm_i915_master_private *master_priv;
259
260 /* disable master interrupt before clearing iir */
261 de_ier = I915_READ(DEIER);
262 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
263 (void)I915_READ(DEIER);
264
265 de_iir = I915_READ(DEIIR);
266 gt_iir = I915_READ(GTIIR);
267
268 if (de_iir == 0 && gt_iir == 0)
269 goto done;
270
271 ret = IRQ_HANDLED;
272
273 if (dev->primary->master) {
274 master_priv = dev->primary->master->driver_priv;
275 if (master_priv->sarea_priv)
276 master_priv->sarea_priv->last_dispatch =
277 READ_BREADCRUMB(dev_priv);
278 }
279
280 if (gt_iir & GT_USER_INTERRUPT) {
281 u32 seqno = i915_get_gem_seqno(dev);
282 dev_priv->mm.irq_gem_seqno = seqno;
283 trace_i915_gem_request_complete(dev, seqno);
284 DRM_WAKEUP(&dev_priv->irq_queue);
285 dev_priv->hangcheck_count = 0;
286 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
287 }
288
289 I915_WRITE(GTIIR, gt_iir);
290 I915_WRITE(DEIIR, de_iir);
291
292 done:
293 I915_WRITE(DEIER, de_ier);
294 (void)I915_READ(DEIER);
295
296 return ret;
297 }
298
299 /**
300 * i915_error_work_func - do process context error handling work
301 * @work: work struct
302 *
303 * Fire an error uevent so userspace can see that a hang or error
304 * was detected.
305 */
306 static void i915_error_work_func(struct work_struct *work)
307 {
308 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
309 error_work);
310 struct drm_device *dev = dev_priv->dev;
311 char *error_event[] = { "ERROR=1", NULL };
312 char *reset_event[] = { "RESET=1", NULL };
313 char *reset_done_event[] = { "ERROR=0", NULL };
314
315 DRM_DEBUG("generating error event\n");
316 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
317
318 if (atomic_read(&dev_priv->mm.wedged)) {
319 if (IS_I965G(dev)) {
320 DRM_DEBUG("resetting chip\n");
321 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
322 if (!i965_reset(dev, GDRST_RENDER)) {
323 atomic_set(&dev_priv->mm.wedged, 0);
324 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
325 }
326 } else {
327 printk("reboot required\n");
328 }
329 }
330 }
331
332 /**
333 * i915_capture_error_state - capture an error record for later analysis
334 * @dev: drm device
335 *
336 * Should be called when an error is detected (either a hang or an error
337 * interrupt) to capture error state from the time of the error. Fills
338 * out a structure which becomes available in debugfs for user level tools
339 * to pick up.
340 */
341 static void i915_capture_error_state(struct drm_device *dev)
342 {
343 struct drm_i915_private *dev_priv = dev->dev_private;
344 struct drm_i915_error_state *error;
345 unsigned long flags;
346
347 spin_lock_irqsave(&dev_priv->error_lock, flags);
348 if (dev_priv->first_error)
349 goto out;
350
351 error = kmalloc(sizeof(*error), GFP_ATOMIC);
352 if (!error) {
353 DRM_DEBUG("out ot memory, not capturing error state\n");
354 goto out;
355 }
356
357 error->eir = I915_READ(EIR);
358 error->pgtbl_er = I915_READ(PGTBL_ER);
359 error->pipeastat = I915_READ(PIPEASTAT);
360 error->pipebstat = I915_READ(PIPEBSTAT);
361 error->instpm = I915_READ(INSTPM);
362 if (!IS_I965G(dev)) {
363 error->ipeir = I915_READ(IPEIR);
364 error->ipehr = I915_READ(IPEHR);
365 error->instdone = I915_READ(INSTDONE);
366 error->acthd = I915_READ(ACTHD);
367 } else {
368 error->ipeir = I915_READ(IPEIR_I965);
369 error->ipehr = I915_READ(IPEHR_I965);
370 error->instdone = I915_READ(INSTDONE_I965);
371 error->instps = I915_READ(INSTPS);
372 error->instdone1 = I915_READ(INSTDONE1);
373 error->acthd = I915_READ(ACTHD_I965);
374 }
375
376 do_gettimeofday(&error->time);
377
378 dev_priv->first_error = error;
379
380 out:
381 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
382 }
383
384 /**
385 * i915_handle_error - handle an error interrupt
386 * @dev: drm device
387 *
388 * Do some basic checking of regsiter state at error interrupt time and
389 * dump it to the syslog. Also call i915_capture_error_state() to make
390 * sure we get a record and make it available in debugfs. Fire a uevent
391 * so userspace knows something bad happened (should trigger collection
392 * of a ring dump etc.).
393 */
394 static void i915_handle_error(struct drm_device *dev, bool wedged)
395 {
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 u32 eir = I915_READ(EIR);
398 u32 pipea_stats = I915_READ(PIPEASTAT);
399 u32 pipeb_stats = I915_READ(PIPEBSTAT);
400
401 i915_capture_error_state(dev);
402
403 printk(KERN_ERR "render error detected, EIR: 0x%08x\n",
404 eir);
405
406 if (IS_G4X(dev)) {
407 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
408 u32 ipeir = I915_READ(IPEIR_I965);
409
410 printk(KERN_ERR " IPEIR: 0x%08x\n",
411 I915_READ(IPEIR_I965));
412 printk(KERN_ERR " IPEHR: 0x%08x\n",
413 I915_READ(IPEHR_I965));
414 printk(KERN_ERR " INSTDONE: 0x%08x\n",
415 I915_READ(INSTDONE_I965));
416 printk(KERN_ERR " INSTPS: 0x%08x\n",
417 I915_READ(INSTPS));
418 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
419 I915_READ(INSTDONE1));
420 printk(KERN_ERR " ACTHD: 0x%08x\n",
421 I915_READ(ACTHD_I965));
422 I915_WRITE(IPEIR_I965, ipeir);
423 (void)I915_READ(IPEIR_I965);
424 }
425 if (eir & GM45_ERROR_PAGE_TABLE) {
426 u32 pgtbl_err = I915_READ(PGTBL_ER);
427 printk(KERN_ERR "page table error\n");
428 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
429 pgtbl_err);
430 I915_WRITE(PGTBL_ER, pgtbl_err);
431 (void)I915_READ(PGTBL_ER);
432 }
433 }
434
435 if (IS_I9XX(dev)) {
436 if (eir & I915_ERROR_PAGE_TABLE) {
437 u32 pgtbl_err = I915_READ(PGTBL_ER);
438 printk(KERN_ERR "page table error\n");
439 printk(KERN_ERR " PGTBL_ER: 0x%08x\n",
440 pgtbl_err);
441 I915_WRITE(PGTBL_ER, pgtbl_err);
442 (void)I915_READ(PGTBL_ER);
443 }
444 }
445
446 if (eir & I915_ERROR_MEMORY_REFRESH) {
447 printk(KERN_ERR "memory refresh error\n");
448 printk(KERN_ERR "PIPEASTAT: 0x%08x\n",
449 pipea_stats);
450 printk(KERN_ERR "PIPEBSTAT: 0x%08x\n",
451 pipeb_stats);
452 /* pipestat has already been acked */
453 }
454 if (eir & I915_ERROR_INSTRUCTION) {
455 printk(KERN_ERR "instruction error\n");
456 printk(KERN_ERR " INSTPM: 0x%08x\n",
457 I915_READ(INSTPM));
458 if (!IS_I965G(dev)) {
459 u32 ipeir = I915_READ(IPEIR);
460
461 printk(KERN_ERR " IPEIR: 0x%08x\n",
462 I915_READ(IPEIR));
463 printk(KERN_ERR " IPEHR: 0x%08x\n",
464 I915_READ(IPEHR));
465 printk(KERN_ERR " INSTDONE: 0x%08x\n",
466 I915_READ(INSTDONE));
467 printk(KERN_ERR " ACTHD: 0x%08x\n",
468 I915_READ(ACTHD));
469 I915_WRITE(IPEIR, ipeir);
470 (void)I915_READ(IPEIR);
471 } else {
472 u32 ipeir = I915_READ(IPEIR_I965);
473
474 printk(KERN_ERR " IPEIR: 0x%08x\n",
475 I915_READ(IPEIR_I965));
476 printk(KERN_ERR " IPEHR: 0x%08x\n",
477 I915_READ(IPEHR_I965));
478 printk(KERN_ERR " INSTDONE: 0x%08x\n",
479 I915_READ(INSTDONE_I965));
480 printk(KERN_ERR " INSTPS: 0x%08x\n",
481 I915_READ(INSTPS));
482 printk(KERN_ERR " INSTDONE1: 0x%08x\n",
483 I915_READ(INSTDONE1));
484 printk(KERN_ERR " ACTHD: 0x%08x\n",
485 I915_READ(ACTHD_I965));
486 I915_WRITE(IPEIR_I965, ipeir);
487 (void)I915_READ(IPEIR_I965);
488 }
489 }
490
491 I915_WRITE(EIR, eir);
492 (void)I915_READ(EIR);
493 eir = I915_READ(EIR);
494 if (eir) {
495 /*
496 * some errors might have become stuck,
497 * mask them.
498 */
499 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
500 I915_WRITE(EMR, I915_READ(EMR) | eir);
501 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
502 }
503
504 if (wedged) {
505 atomic_set(&dev_priv->mm.wedged, 1);
506
507 /*
508 * Wakeup waiting processes so they don't hang
509 */
510 printk("i915: Waking up sleeping processes\n");
511 DRM_WAKEUP(&dev_priv->irq_queue);
512 }
513
514 queue_work(dev_priv->wq, &dev_priv->error_work);
515 }
516
517 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
518 {
519 struct drm_device *dev = (struct drm_device *) arg;
520 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
521 struct drm_i915_master_private *master_priv;
522 u32 iir, new_iir;
523 u32 pipea_stats, pipeb_stats;
524 u32 vblank_status;
525 u32 vblank_enable;
526 int vblank = 0;
527 unsigned long irqflags;
528 int irq_received;
529 int ret = IRQ_NONE;
530
531 atomic_inc(&dev_priv->irq_received);
532
533 if (IS_IGDNG(dev))
534 return igdng_irq_handler(dev);
535
536 iir = I915_READ(IIR);
537
538 if (IS_I965G(dev)) {
539 vblank_status = I915_START_VBLANK_INTERRUPT_STATUS;
540 vblank_enable = PIPE_START_VBLANK_INTERRUPT_ENABLE;
541 } else {
542 vblank_status = I915_VBLANK_INTERRUPT_STATUS;
543 vblank_enable = I915_VBLANK_INTERRUPT_ENABLE;
544 }
545
546 for (;;) {
547 irq_received = iir != 0;
548
549 /* Can't rely on pipestat interrupt bit in iir as it might
550 * have been cleared after the pipestat interrupt was received.
551 * It doesn't set the bit in iir again, but it still produces
552 * interrupts (for non-MSI).
553 */
554 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
555 pipea_stats = I915_READ(PIPEASTAT);
556 pipeb_stats = I915_READ(PIPEBSTAT);
557
558 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
559 i915_handle_error(dev, false);
560
561 /*
562 * Clear the PIPE(A|B)STAT regs before the IIR
563 */
564 if (pipea_stats & 0x8000ffff) {
565 if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS)
566 DRM_DEBUG("pipe a underrun\n");
567 I915_WRITE(PIPEASTAT, pipea_stats);
568 irq_received = 1;
569 }
570
571 if (pipeb_stats & 0x8000ffff) {
572 if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS)
573 DRM_DEBUG("pipe b underrun\n");
574 I915_WRITE(PIPEBSTAT, pipeb_stats);
575 irq_received = 1;
576 }
577 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
578
579 if (!irq_received)
580 break;
581
582 ret = IRQ_HANDLED;
583
584 /* Consume port. Then clear IIR or we'll miss events */
585 if ((I915_HAS_HOTPLUG(dev)) &&
586 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
587 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
588
589 DRM_DEBUG("hotplug event received, stat 0x%08x\n",
590 hotplug_status);
591 if (hotplug_status & dev_priv->hotplug_supported_mask)
592 queue_work(dev_priv->wq,
593 &dev_priv->hotplug_work);
594
595 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
596 I915_READ(PORT_HOTPLUG_STAT);
597
598 /* EOS interrupts occurs */
599 if (IS_IGD(dev) &&
600 (hotplug_status & CRT_EOS_INT_STATUS)) {
601 u32 temp;
602
603 DRM_DEBUG("EOS interrupt occurs\n");
604 /* status is already cleared */
605 temp = I915_READ(ADPA);
606 temp &= ~ADPA_DAC_ENABLE;
607 I915_WRITE(ADPA, temp);
608
609 temp = I915_READ(PORT_HOTPLUG_EN);
610 temp &= ~CRT_EOS_INT_EN;
611 I915_WRITE(PORT_HOTPLUG_EN, temp);
612
613 temp = I915_READ(PORT_HOTPLUG_STAT);
614 if (temp & CRT_EOS_INT_STATUS)
615 I915_WRITE(PORT_HOTPLUG_STAT,
616 CRT_EOS_INT_STATUS);
617 }
618 }
619
620 I915_WRITE(IIR, iir);
621 new_iir = I915_READ(IIR); /* Flush posted writes */
622
623 if (dev->primary->master) {
624 master_priv = dev->primary->master->driver_priv;
625 if (master_priv->sarea_priv)
626 master_priv->sarea_priv->last_dispatch =
627 READ_BREADCRUMB(dev_priv);
628 }
629
630 if (iir & I915_USER_INTERRUPT) {
631 u32 seqno = i915_get_gem_seqno(dev);
632 dev_priv->mm.irq_gem_seqno = seqno;
633 trace_i915_gem_request_complete(dev, seqno);
634 DRM_WAKEUP(&dev_priv->irq_queue);
635 dev_priv->hangcheck_count = 0;
636 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
637 }
638
639 if (pipea_stats & vblank_status) {
640 vblank++;
641 drm_handle_vblank(dev, 0);
642 }
643
644 if (pipeb_stats & vblank_status) {
645 vblank++;
646 drm_handle_vblank(dev, 1);
647 }
648
649 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
650 (iir & I915_ASLE_INTERRUPT))
651 opregion_asle_intr(dev);
652
653 /* With MSI, interrupts are only generated when iir
654 * transitions from zero to nonzero. If another bit got
655 * set while we were handling the existing iir bits, then
656 * we would never get another interrupt.
657 *
658 * This is fine on non-MSI as well, as if we hit this path
659 * we avoid exiting the interrupt handler only to generate
660 * another one.
661 *
662 * Note that for MSI this could cause a stray interrupt report
663 * if an interrupt landed in the time between writing IIR and
664 * the posting read. This should be rare enough to never
665 * trigger the 99% of 100,000 interrupts test for disabling
666 * stray interrupts.
667 */
668 iir = new_iir;
669 }
670
671 return ret;
672 }
673
674 static int i915_emit_irq(struct drm_device * dev)
675 {
676 drm_i915_private_t *dev_priv = dev->dev_private;
677 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
678 RING_LOCALS;
679
680 i915_kernel_lost_context(dev);
681
682 DRM_DEBUG("\n");
683
684 dev_priv->counter++;
685 if (dev_priv->counter > 0x7FFFFFFFUL)
686 dev_priv->counter = 1;
687 if (master_priv->sarea_priv)
688 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
689
690 BEGIN_LP_RING(4);
691 OUT_RING(MI_STORE_DWORD_INDEX);
692 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
693 OUT_RING(dev_priv->counter);
694 OUT_RING(MI_USER_INTERRUPT);
695 ADVANCE_LP_RING();
696
697 return dev_priv->counter;
698 }
699
700 void i915_user_irq_get(struct drm_device *dev)
701 {
702 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
703 unsigned long irqflags;
704
705 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
706 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
707 if (IS_IGDNG(dev))
708 igdng_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
709 else
710 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
711 }
712 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
713 }
714
715 void i915_user_irq_put(struct drm_device *dev)
716 {
717 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
718 unsigned long irqflags;
719
720 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
721 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
722 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
723 if (IS_IGDNG(dev))
724 igdng_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
725 else
726 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
727 }
728 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
729 }
730
731 void i915_trace_irq_get(struct drm_device *dev, u32 seqno)
732 {
733 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
734
735 if (dev_priv->trace_irq_seqno == 0)
736 i915_user_irq_get(dev);
737
738 dev_priv->trace_irq_seqno = seqno;
739 }
740
741 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
742 {
743 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
744 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
745 int ret = 0;
746
747 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
748 READ_BREADCRUMB(dev_priv));
749
750 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
751 if (master_priv->sarea_priv)
752 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
753 return 0;
754 }
755
756 if (master_priv->sarea_priv)
757 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
758
759 i915_user_irq_get(dev);
760 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
761 READ_BREADCRUMB(dev_priv) >= irq_nr);
762 i915_user_irq_put(dev);
763
764 if (ret == -EBUSY) {
765 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
766 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
767 }
768
769 return ret;
770 }
771
772 /* Needs the lock as it touches the ring.
773 */
774 int i915_irq_emit(struct drm_device *dev, void *data,
775 struct drm_file *file_priv)
776 {
777 drm_i915_private_t *dev_priv = dev->dev_private;
778 drm_i915_irq_emit_t *emit = data;
779 int result;
780
781 if (!dev_priv || !dev_priv->ring.virtual_start) {
782 DRM_ERROR("called with no initialization\n");
783 return -EINVAL;
784 }
785
786 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
787
788 mutex_lock(&dev->struct_mutex);
789 result = i915_emit_irq(dev);
790 mutex_unlock(&dev->struct_mutex);
791
792 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
793 DRM_ERROR("copy_to_user\n");
794 return -EFAULT;
795 }
796
797 return 0;
798 }
799
800 /* Doesn't need the hardware lock.
801 */
802 int i915_irq_wait(struct drm_device *dev, void *data,
803 struct drm_file *file_priv)
804 {
805 drm_i915_private_t *dev_priv = dev->dev_private;
806 drm_i915_irq_wait_t *irqwait = data;
807
808 if (!dev_priv) {
809 DRM_ERROR("called with no initialization\n");
810 return -EINVAL;
811 }
812
813 return i915_wait_irq(dev, irqwait->irq_seq);
814 }
815
816 /* Called from drm generic code, passed 'crtc' which
817 * we use as a pipe index
818 */
819 int i915_enable_vblank(struct drm_device *dev, int pipe)
820 {
821 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
822 unsigned long irqflags;
823 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
824 u32 pipeconf;
825
826 pipeconf = I915_READ(pipeconf_reg);
827 if (!(pipeconf & PIPEACONF_ENABLE))
828 return -EINVAL;
829
830 if (IS_IGDNG(dev))
831 return 0;
832
833 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
834 if (IS_I965G(dev))
835 i915_enable_pipestat(dev_priv, pipe,
836 PIPE_START_VBLANK_INTERRUPT_ENABLE);
837 else
838 i915_enable_pipestat(dev_priv, pipe,
839 PIPE_VBLANK_INTERRUPT_ENABLE);
840 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
841 return 0;
842 }
843
844 /* Called from drm generic code, passed 'crtc' which
845 * we use as a pipe index
846 */
847 void i915_disable_vblank(struct drm_device *dev, int pipe)
848 {
849 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
850 unsigned long irqflags;
851
852 if (IS_IGDNG(dev))
853 return;
854
855 spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
856 i915_disable_pipestat(dev_priv, pipe,
857 PIPE_VBLANK_INTERRUPT_ENABLE |
858 PIPE_START_VBLANK_INTERRUPT_ENABLE);
859 spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
860 }
861
862 void i915_enable_interrupt (struct drm_device *dev)
863 {
864 struct drm_i915_private *dev_priv = dev->dev_private;
865
866 if (!IS_IGDNG(dev))
867 opregion_enable_asle(dev);
868 dev_priv->irq_enabled = 1;
869 }
870
871
872 /* Set the vblank monitor pipe
873 */
874 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
875 struct drm_file *file_priv)
876 {
877 drm_i915_private_t *dev_priv = dev->dev_private;
878
879 if (!dev_priv) {
880 DRM_ERROR("called with no initialization\n");
881 return -EINVAL;
882 }
883
884 return 0;
885 }
886
887 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
888 struct drm_file *file_priv)
889 {
890 drm_i915_private_t *dev_priv = dev->dev_private;
891 drm_i915_vblank_pipe_t *pipe = data;
892
893 if (!dev_priv) {
894 DRM_ERROR("called with no initialization\n");
895 return -EINVAL;
896 }
897
898 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
899
900 return 0;
901 }
902
903 /**
904 * Schedule buffer swap at given vertical blank.
905 */
906 int i915_vblank_swap(struct drm_device *dev, void *data,
907 struct drm_file *file_priv)
908 {
909 /* The delayed swap mechanism was fundamentally racy, and has been
910 * removed. The model was that the client requested a delayed flip/swap
911 * from the kernel, then waited for vblank before continuing to perform
912 * rendering. The problem was that the kernel might wake the client
913 * up before it dispatched the vblank swap (since the lock has to be
914 * held while touching the ringbuffer), in which case the client would
915 * clear and start the next frame before the swap occurred, and
916 * flicker would occur in addition to likely missing the vblank.
917 *
918 * In the absence of this ioctl, userland falls back to a correct path
919 * of waiting for a vblank, then dispatching the swap on its own.
920 * Context switching to userland and back is plenty fast enough for
921 * meeting the requirements of vblank swapping.
922 */
923 return -EINVAL;
924 }
925
926 struct drm_i915_gem_request *i915_get_tail_request(struct drm_device *dev) {
927 drm_i915_private_t *dev_priv = dev->dev_private;
928 return list_entry(dev_priv->mm.request_list.prev, struct drm_i915_gem_request, list);
929 }
930
931 /**
932 * This is called when the chip hasn't reported back with completed
933 * batchbuffers in a long time. The first time this is called we simply record
934 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
935 * again, we assume the chip is wedged and try to fix it.
936 */
937 void i915_hangcheck_elapsed(unsigned long data)
938 {
939 struct drm_device *dev = (struct drm_device *)data;
940 drm_i915_private_t *dev_priv = dev->dev_private;
941 uint32_t acthd;
942
943 if (!IS_I965G(dev))
944 acthd = I915_READ(ACTHD);
945 else
946 acthd = I915_READ(ACTHD_I965);
947
948 /* If all work is done then ACTHD clearly hasn't advanced. */
949 if (list_empty(&dev_priv->mm.request_list) ||
950 i915_seqno_passed(i915_get_gem_seqno(dev), i915_get_tail_request(dev)->seqno)) {
951 dev_priv->hangcheck_count = 0;
952 return;
953 }
954
955 if (dev_priv->last_acthd == acthd && dev_priv->hangcheck_count > 0) {
956 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
957 i915_handle_error(dev, true);
958 return;
959 }
960
961 /* Reset timer case chip hangs without another request being added */
962 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
963
964 if (acthd != dev_priv->last_acthd)
965 dev_priv->hangcheck_count = 0;
966 else
967 dev_priv->hangcheck_count++;
968
969 dev_priv->last_acthd = acthd;
970 }
971
972 /* drm_dma.h hooks
973 */
974 static void igdng_irq_preinstall(struct drm_device *dev)
975 {
976 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
977
978 I915_WRITE(HWSTAM, 0xeffe);
979
980 /* XXX hotplug from PCH */
981
982 I915_WRITE(DEIMR, 0xffffffff);
983 I915_WRITE(DEIER, 0x0);
984 (void) I915_READ(DEIER);
985
986 /* and GT */
987 I915_WRITE(GTIMR, 0xffffffff);
988 I915_WRITE(GTIER, 0x0);
989 (void) I915_READ(GTIER);
990 }
991
992 static int igdng_irq_postinstall(struct drm_device *dev)
993 {
994 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
995 /* enable kind of interrupts always enabled */
996 u32 display_mask = DE_MASTER_IRQ_CONTROL /*| DE_PCH_EVENT */;
997 u32 render_mask = GT_USER_INTERRUPT;
998
999 dev_priv->irq_mask_reg = ~display_mask;
1000 dev_priv->de_irq_enable_reg = display_mask;
1001
1002 /* should always can generate irq */
1003 I915_WRITE(DEIIR, I915_READ(DEIIR));
1004 I915_WRITE(DEIMR, dev_priv->irq_mask_reg);
1005 I915_WRITE(DEIER, dev_priv->de_irq_enable_reg);
1006 (void) I915_READ(DEIER);
1007
1008 /* user interrupt should be enabled, but masked initial */
1009 dev_priv->gt_irq_mask_reg = 0xffffffff;
1010 dev_priv->gt_irq_enable_reg = render_mask;
1011
1012 I915_WRITE(GTIIR, I915_READ(GTIIR));
1013 I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg);
1014 I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg);
1015 (void) I915_READ(GTIER);
1016
1017 return 0;
1018 }
1019
1020 void i915_driver_irq_preinstall(struct drm_device * dev)
1021 {
1022 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1023
1024 atomic_set(&dev_priv->irq_received, 0);
1025
1026 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
1027 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
1028
1029 if (IS_IGDNG(dev)) {
1030 igdng_irq_preinstall(dev);
1031 return;
1032 }
1033
1034 if (I915_HAS_HOTPLUG(dev)) {
1035 I915_WRITE(PORT_HOTPLUG_EN, 0);
1036 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1037 }
1038
1039 I915_WRITE(HWSTAM, 0xeffe);
1040 I915_WRITE(PIPEASTAT, 0);
1041 I915_WRITE(PIPEBSTAT, 0);
1042 I915_WRITE(IMR, 0xffffffff);
1043 I915_WRITE(IER, 0x0);
1044 (void) I915_READ(IER);
1045 }
1046
1047 /*
1048 * Must be called after intel_modeset_init or hotplug interrupts won't be
1049 * enabled correctly.
1050 */
1051 int i915_driver_irq_postinstall(struct drm_device *dev)
1052 {
1053 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1054 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
1055 u32 error_mask;
1056
1057 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
1058
1059 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1060
1061 if (IS_IGDNG(dev))
1062 return igdng_irq_postinstall(dev);
1063
1064 /* Unmask the interrupts that we always want on. */
1065 dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
1066
1067 dev_priv->pipestat[0] = 0;
1068 dev_priv->pipestat[1] = 0;
1069
1070 if (I915_HAS_HOTPLUG(dev)) {
1071 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1072
1073 /* Note HDMI and DP share bits */
1074 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1075 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1076 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1077 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1078 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1079 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1080 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1081 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1082 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1083 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1084 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS)
1085 hotplug_en |= CRT_HOTPLUG_INT_EN;
1086 /* Ignore TV since it's buggy */
1087
1088 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1089
1090 /* Enable in IER... */
1091 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
1092 /* and unmask in IMR */
1093 i915_enable_irq(dev_priv, I915_DISPLAY_PORT_INTERRUPT);
1094 }
1095
1096 /*
1097 * Enable some error detection, note the instruction error mask
1098 * bit is reserved, so we leave it masked.
1099 */
1100 if (IS_G4X(dev)) {
1101 error_mask = ~(GM45_ERROR_PAGE_TABLE |
1102 GM45_ERROR_MEM_PRIV |
1103 GM45_ERROR_CP_PRIV |
1104 I915_ERROR_MEMORY_REFRESH);
1105 } else {
1106 error_mask = ~(I915_ERROR_PAGE_TABLE |
1107 I915_ERROR_MEMORY_REFRESH);
1108 }
1109 I915_WRITE(EMR, error_mask);
1110
1111 /* Disable pipe interrupt enables, clear pending pipe status */
1112 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1113 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1114 /* Clear pending interrupt status */
1115 I915_WRITE(IIR, I915_READ(IIR));
1116
1117 I915_WRITE(IER, enable_mask);
1118 I915_WRITE(IMR, dev_priv->irq_mask_reg);
1119 (void) I915_READ(IER);
1120
1121 opregion_enable_asle(dev);
1122
1123 return 0;
1124 }
1125
1126 static void igdng_irq_uninstall(struct drm_device *dev)
1127 {
1128 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1129 I915_WRITE(HWSTAM, 0xffffffff);
1130
1131 I915_WRITE(DEIMR, 0xffffffff);
1132 I915_WRITE(DEIER, 0x0);
1133 I915_WRITE(DEIIR, I915_READ(DEIIR));
1134
1135 I915_WRITE(GTIMR, 0xffffffff);
1136 I915_WRITE(GTIER, 0x0);
1137 I915_WRITE(GTIIR, I915_READ(GTIIR));
1138 }
1139
1140 void i915_driver_irq_uninstall(struct drm_device * dev)
1141 {
1142 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1143
1144 if (!dev_priv)
1145 return;
1146
1147 dev_priv->vblank_pipe = 0;
1148
1149 if (IS_IGDNG(dev)) {
1150 igdng_irq_uninstall(dev);
1151 return;
1152 }
1153
1154 if (I915_HAS_HOTPLUG(dev)) {
1155 I915_WRITE(PORT_HOTPLUG_EN, 0);
1156 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1157 }
1158
1159 I915_WRITE(HWSTAM, 0xffffffff);
1160 I915_WRITE(PIPEASTAT, 0);
1161 I915_WRITE(PIPEBSTAT, 0);
1162 I915_WRITE(IMR, 0xffffffff);
1163 I915_WRITE(IER, 0x0);
1164
1165 I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
1166 I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
1167 I915_WRITE(IIR, I915_READ(IIR));
1168 }
Linux ARM platform port for MOXA ART SoC