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initial commit with v2.6.32.60
[linux-2.6.32.60-moxart.git] / drivers / gpu / drm / i915 / intel_sdvo.c
blob5d9c6a7a6ed55574e5c60ee1c7ad7e8150a0846a
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28 #include <linux/i2c.h>
29 #include <linux/delay.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "intel_drv.h"
34 #include "drm_edid.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "intel_sdvo_regs.h"
38 #include <linux/dmi.h>
39
40 #undef SDVO_DEBUG
41
42 static char *tv_format_names[] = {
43 "NTSC_M" , "NTSC_J" , "NTSC_443",
44 "PAL_B" , "PAL_D" , "PAL_G" ,
45 "PAL_H" , "PAL_I" , "PAL_M" ,
46 "PAL_N" , "PAL_NC" , "PAL_60" ,
47 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
48 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
49 "SECAM_60"
50 };
51
52 #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
53
54 struct intel_sdvo_priv {
55 u8 slave_addr;
56
57 /* Register for the SDVO device: SDVOB or SDVOC */
58 int output_device;
59
60 /* Active outputs controlled by this SDVO output */
61 uint16_t controlled_output;
62
63 /*
64 * Capabilities of the SDVO device returned by
65 * i830_sdvo_get_capabilities()
66 */
67 struct intel_sdvo_caps caps;
68
69 /* Pixel clock limitations reported by the SDVO device, in kHz */
70 int pixel_clock_min, pixel_clock_max;
71
72 /*
73 * For multiple function SDVO device,
74 * this is for current attached outputs.
75 */
76 uint16_t attached_output;
77
78 /**
79 * This is set if we're going to treat the device as TV-out.
80 *
81 * While we have these nice friendly flags for output types that ought
82 * to decide this for us, the S-Video output on our HDMI+S-Video card
83 * shows up as RGB1 (VGA).
84 */
85 bool is_tv;
86
87 /* This is for current tv format name */
88 char *tv_format_name;
89
90 /* This contains all current supported TV format */
91 char *tv_format_supported[TV_FORMAT_NUM];
92 int format_supported_num;
93 struct drm_property *tv_format_property;
94 struct drm_property *tv_format_name_property[TV_FORMAT_NUM];
95
96 /**
97 * This is set if we treat the device as HDMI, instead of DVI.
98 */
99 bool is_hdmi;
100
101 /**
102 * This is set if we detect output of sdvo device as LVDS.
103 */
104 bool is_lvds;
105
106 /**
107 * This is sdvo flags for input timing.
108 */
109 uint8_t sdvo_flags;
110
111 /**
112 * This is sdvo fixed pannel mode pointer
113 */
114 struct drm_display_mode *sdvo_lvds_fixed_mode;
115
116 /**
117 * Returned SDTV resolutions allowed for the current format, if the
118 * device reported it.
119 */
120 struct intel_sdvo_sdtv_resolution_reply sdtv_resolutions;
121
122 /*
123 * supported encoding mode, used to determine whether HDMI is
124 * supported
125 */
126 struct intel_sdvo_encode encode;
127
128 /* DDC bus used by this SDVO output */
129 uint8_t ddc_bus;
130
131 /* Mac mini hack -- use the same DDC as the analog connector */
132 struct i2c_adapter *analog_ddc_bus;
133
134 int save_sdvo_mult;
135 u16 save_active_outputs;
136 struct intel_sdvo_dtd save_input_dtd_1, save_input_dtd_2;
137 struct intel_sdvo_dtd save_output_dtd[16];
138 u32 save_SDVOX;
139 /* add the property for the SDVO-TV */
140 struct drm_property *left_property;
141 struct drm_property *right_property;
142 struct drm_property *top_property;
143 struct drm_property *bottom_property;
144 struct drm_property *hpos_property;
145 struct drm_property *vpos_property;
146
147 /* add the property for the SDVO-TV/LVDS */
148 struct drm_property *brightness_property;
149 struct drm_property *contrast_property;
150 struct drm_property *saturation_property;
151 struct drm_property *hue_property;
152
153 /* Add variable to record current setting for the above property */
154 u32 left_margin, right_margin, top_margin, bottom_margin;
155 /* this is to get the range of margin.*/
156 u32 max_hscan, max_vscan;
157 u32 max_hpos, cur_hpos;
158 u32 max_vpos, cur_vpos;
159 u32 cur_brightness, max_brightness;
160 u32 cur_contrast, max_contrast;
161 u32 cur_saturation, max_saturation;
162 u32 cur_hue, max_hue;
163 };
164
165 static bool
166 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags);
167
168 /**
169 * Writes the SDVOB or SDVOC with the given value, but always writes both
170 * SDVOB and SDVOC to work around apparent hardware issues (according to
171 * comments in the BIOS).
172 */
173 static void intel_sdvo_write_sdvox(struct intel_output *intel_output, u32 val)
174 {
175 struct drm_device *dev = intel_output->base.dev;
176 struct drm_i915_private *dev_priv = dev->dev_private;
177 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
178 u32 bval = val, cval = val;
179 int i;
180
181 if (sdvo_priv->output_device == SDVOB) {
182 cval = I915_READ(SDVOC);
183 } else {
184 bval = I915_READ(SDVOB);
185 }
186 /*
187 * Write the registers twice for luck. Sometimes,
188 * writing them only once doesn't appear to 'stick'.
189 * The BIOS does this too. Yay, magic
190 */
191 for (i = 0; i < 2; i++)
192 {
193 I915_WRITE(SDVOB, bval);
194 I915_READ(SDVOB);
195 I915_WRITE(SDVOC, cval);
196 I915_READ(SDVOC);
197 }
198 }
199
200 static bool intel_sdvo_read_byte(struct intel_output *intel_output, u8 addr,
201 u8 *ch)
202 {
203 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
204 u8 out_buf[2];
205 u8 buf[2];
206 int ret;
207
208 struct i2c_msg msgs[] = {
209 {
210 .addr = sdvo_priv->slave_addr >> 1,
211 .flags = 0,
212 .len = 1,
213 .buf = out_buf,
214 },
215 {
216 .addr = sdvo_priv->slave_addr >> 1,
217 .flags = I2C_M_RD,
218 .len = 1,
219 .buf = buf,
220 }
221 };
222
223 out_buf[0] = addr;
224 out_buf[1] = 0;
225
226 if ((ret = i2c_transfer(intel_output->i2c_bus, msgs, 2)) == 2)
227 {
228 *ch = buf[0];
229 return true;
230 }
231
232 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
233 return false;
234 }
235
236 static bool intel_sdvo_write_byte(struct intel_output *intel_output, int addr,
237 u8 ch)
238 {
239 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
240 u8 out_buf[2];
241 struct i2c_msg msgs[] = {
242 {
243 .addr = sdvo_priv->slave_addr >> 1,
244 .flags = 0,
245 .len = 2,
246 .buf = out_buf,
247 }
248 };
249
250 out_buf[0] = addr;
251 out_buf[1] = ch;
252
253 if (i2c_transfer(intel_output->i2c_bus, msgs, 1) == 1)
254 {
255 return true;
256 }
257 return false;
258 }
259
260 #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
261 /** Mapping of command numbers to names, for debug output */
262 static const struct _sdvo_cmd_name {
263 u8 cmd;
264 char *name;
265 } sdvo_cmd_names[] = {
266 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
267 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
268 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
269 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
270 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
271 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
272 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
273 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
274 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
275 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
276 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
277 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
278 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
279 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
280 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
281 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
282 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
283 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
284 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
285 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
286 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
287 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
288 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
289 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
290 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
291 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
309 /* Add the op code for SDVO enhancements */
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_H),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_H),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_H),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_POSITION_V),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POSITION_V),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_POSITION_V),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
334 /* HDMI op code */
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
355 };
356
357 #define SDVO_NAME(dev_priv) ((dev_priv)->output_device == SDVOB ? "SDVOB" : "SDVOC")
358 #define SDVO_PRIV(output) ((struct intel_sdvo_priv *) (output)->dev_priv)
359
360 #ifdef SDVO_DEBUG
361 static void intel_sdvo_debug_write(struct intel_output *intel_output, u8 cmd,
362 void *args, int args_len)
363 {
364 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
365 int i;
366
367 DRM_DEBUG_KMS("%s: W: %02X ",
368 SDVO_NAME(sdvo_priv), cmd);
369 for (i = 0; i < args_len; i++)
370 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
371 for (; i < 8; i++)
372 DRM_LOG_KMS(" ");
373 for (i = 0; i < sizeof(sdvo_cmd_names) / sizeof(sdvo_cmd_names[0]); i++) {
374 if (cmd == sdvo_cmd_names[i].cmd) {
375 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
376 break;
377 }
378 }
379 if (i == sizeof(sdvo_cmd_names)/ sizeof(sdvo_cmd_names[0]))
380 DRM_LOG_KMS("(%02X)", cmd);
381 DRM_LOG_KMS("\n");
382 }
383 #else
384 #define intel_sdvo_debug_write(o, c, a, l)
385 #endif
386
387 static void intel_sdvo_write_cmd(struct intel_output *intel_output, u8 cmd,
388 void *args, int args_len)
389 {
390 int i;
391
392 intel_sdvo_debug_write(intel_output, cmd, args, args_len);
393
394 for (i = 0; i < args_len; i++) {
395 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0 - i,
396 ((u8*)args)[i]);
397 }
398
399 intel_sdvo_write_byte(intel_output, SDVO_I2C_OPCODE, cmd);
400 }
401
402 #ifdef SDVO_DEBUG
403 static const char *cmd_status_names[] = {
404 "Power on",
405 "Success",
406 "Not supported",
407 "Invalid arg",
408 "Pending",
409 "Target not specified",
410 "Scaling not supported"
411 };
412
413 static void intel_sdvo_debug_response(struct intel_output *intel_output,
414 void *response, int response_len,
415 u8 status)
416 {
417 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
418 int i;
419
420 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(sdvo_priv));
421 for (i = 0; i < response_len; i++)
422 DRM_LOG_KMS("%02X ", ((u8 *)response)[i]);
423 for (; i < 8; i++)
424 DRM_LOG_KMS(" ");
425 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
426 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
427 else
428 DRM_LOG_KMS("(??? %d)", status);
429 DRM_LOG_KMS("\n");
430 }
431 #else
432 #define intel_sdvo_debug_response(o, r, l, s)
433 #endif
434
435 static u8 intel_sdvo_read_response(struct intel_output *intel_output,
436 void *response, int response_len)
437 {
438 int i;
439 u8 status;
440 u8 retry = 50;
441
442 while (retry--) {
443 /* Read the command response */
444 for (i = 0; i < response_len; i++) {
445 intel_sdvo_read_byte(intel_output,
446 SDVO_I2C_RETURN_0 + i,
447 &((u8 *)response)[i]);
448 }
449
450 /* read the return status */
451 intel_sdvo_read_byte(intel_output, SDVO_I2C_CMD_STATUS,
452 &status);
453
454 intel_sdvo_debug_response(intel_output, response, response_len,
455 status);
456 if (status != SDVO_CMD_STATUS_PENDING)
457 return status;
458
459 mdelay(50);
460 }
461
462 return status;
463 }
464
465 static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
466 {
467 if (mode->clock >= 100000)
468 return 1;
469 else if (mode->clock >= 50000)
470 return 2;
471 else
472 return 4;
473 }
474
475 /**
476 * Try to read the response after issuie the DDC switch command. But it
477 * is noted that we must do the action of reading response and issuing DDC
478 * switch command in one I2C transaction. Otherwise when we try to start
479 * another I2C transaction after issuing the DDC bus switch, it will be
480 * switched to the internal SDVO register.
481 */
482 static void intel_sdvo_set_control_bus_switch(struct intel_output *intel_output,
483 u8 target)
484 {
485 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
486 u8 out_buf[2], cmd_buf[2], ret_value[2], ret;
487 struct i2c_msg msgs[] = {
488 {
489 .addr = sdvo_priv->slave_addr >> 1,
490 .flags = 0,
491 .len = 2,
492 .buf = out_buf,
493 },
494 /* the following two are to read the response */
495 {
496 .addr = sdvo_priv->slave_addr >> 1,
497 .flags = 0,
498 .len = 1,
499 .buf = cmd_buf,
500 },
501 {
502 .addr = sdvo_priv->slave_addr >> 1,
503 .flags = I2C_M_RD,
504 .len = 1,
505 .buf = ret_value,
506 },
507 };
508
509 intel_sdvo_debug_write(intel_output, SDVO_CMD_SET_CONTROL_BUS_SWITCH,
510 &target, 1);
511 /* write the DDC switch command argument */
512 intel_sdvo_write_byte(intel_output, SDVO_I2C_ARG_0, target);
513
514 out_buf[0] = SDVO_I2C_OPCODE;
515 out_buf[1] = SDVO_CMD_SET_CONTROL_BUS_SWITCH;
516 cmd_buf[0] = SDVO_I2C_CMD_STATUS;
517 cmd_buf[1] = 0;
518 ret_value[0] = 0;
519 ret_value[1] = 0;
520
521 ret = i2c_transfer(intel_output->i2c_bus, msgs, 3);
522 if (ret != 3) {
523 /* failure in I2C transfer */
524 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
525 return;
526 }
527 if (ret_value[0] != SDVO_CMD_STATUS_SUCCESS) {
528 DRM_DEBUG_KMS("DDC switch command returns response %d\n",
529 ret_value[0]);
530 return;
531 }
532 return;
533 }
534
535 static bool intel_sdvo_set_target_input(struct intel_output *intel_output, bool target_0, bool target_1)
536 {
537 struct intel_sdvo_set_target_input_args targets = {0};
538 u8 status;
539
540 if (target_0 && target_1)
541 return SDVO_CMD_STATUS_NOTSUPP;
542
543 if (target_1)
544 targets.target_1 = 1;
545
546 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_INPUT, &targets,
547 sizeof(targets));
548
549 status = intel_sdvo_read_response(intel_output, NULL, 0);
550
551 return (status == SDVO_CMD_STATUS_SUCCESS);
552 }
553
554 /**
555 * Return whether each input is trained.
556 *
557 * This function is making an assumption about the layout of the response,
558 * which should be checked against the docs.
559 */
560 static bool intel_sdvo_get_trained_inputs(struct intel_output *intel_output, bool *input_1, bool *input_2)
561 {
562 struct intel_sdvo_get_trained_inputs_response response;
563 u8 status;
564
565 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_TRAINED_INPUTS, NULL, 0);
566 status = intel_sdvo_read_response(intel_output, &response, sizeof(response));
567 if (status != SDVO_CMD_STATUS_SUCCESS)
568 return false;
569
570 *input_1 = response.input0_trained;
571 *input_2 = response.input1_trained;
572 return true;
573 }
574
575 static bool intel_sdvo_get_active_outputs(struct intel_output *intel_output,
576 u16 *outputs)
577 {
578 u8 status;
579
580 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_OUTPUTS, NULL, 0);
581 status = intel_sdvo_read_response(intel_output, outputs, sizeof(*outputs));
582
583 return (status == SDVO_CMD_STATUS_SUCCESS);
584 }
585
586 static bool intel_sdvo_set_active_outputs(struct intel_output *intel_output,
587 u16 outputs)
588 {
589 u8 status;
590
591 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_OUTPUTS, &outputs,
592 sizeof(outputs));
593 status = intel_sdvo_read_response(intel_output, NULL, 0);
594 return (status == SDVO_CMD_STATUS_SUCCESS);
595 }
596
597 static bool intel_sdvo_set_encoder_power_state(struct intel_output *intel_output,
598 int mode)
599 {
600 u8 status, state = SDVO_ENCODER_STATE_ON;
601
602 switch (mode) {
603 case DRM_MODE_DPMS_ON:
604 state = SDVO_ENCODER_STATE_ON;
605 break;
606 case DRM_MODE_DPMS_STANDBY:
607 state = SDVO_ENCODER_STATE_STANDBY;
608 break;
609 case DRM_MODE_DPMS_SUSPEND:
610 state = SDVO_ENCODER_STATE_SUSPEND;
611 break;
612 case DRM_MODE_DPMS_OFF:
613 state = SDVO_ENCODER_STATE_OFF;
614 break;
615 }
616
617 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ENCODER_POWER_STATE, &state,
618 sizeof(state));
619 status = intel_sdvo_read_response(intel_output, NULL, 0);
620
621 return (status == SDVO_CMD_STATUS_SUCCESS);
622 }
623
624 static bool intel_sdvo_get_input_pixel_clock_range(struct intel_output *intel_output,
625 int *clock_min,
626 int *clock_max)
627 {
628 struct intel_sdvo_pixel_clock_range clocks;
629 u8 status;
630
631 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
632 NULL, 0);
633
634 status = intel_sdvo_read_response(intel_output, &clocks, sizeof(clocks));
635
636 if (status != SDVO_CMD_STATUS_SUCCESS)
637 return false;
638
639 /* Convert the values from units of 10 kHz to kHz. */
640 *clock_min = clocks.min * 10;
641 *clock_max = clocks.max * 10;
642
643 return true;
644 }
645
646 static bool intel_sdvo_set_target_output(struct intel_output *intel_output,
647 u16 outputs)
648 {
649 u8 status;
650
651 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_TARGET_OUTPUT, &outputs,
652 sizeof(outputs));
653
654 status = intel_sdvo_read_response(intel_output, NULL, 0);
655 return (status == SDVO_CMD_STATUS_SUCCESS);
656 }
657
658 static bool intel_sdvo_get_timing(struct intel_output *intel_output, u8 cmd,
659 struct intel_sdvo_dtd *dtd)
660 {
661 u8 status;
662
663 intel_sdvo_write_cmd(intel_output, cmd, NULL, 0);
664 status = intel_sdvo_read_response(intel_output, &dtd->part1,
665 sizeof(dtd->part1));
666 if (status != SDVO_CMD_STATUS_SUCCESS)
667 return false;
668
669 intel_sdvo_write_cmd(intel_output, cmd + 1, NULL, 0);
670 status = intel_sdvo_read_response(intel_output, &dtd->part2,
671 sizeof(dtd->part2));
672 if (status != SDVO_CMD_STATUS_SUCCESS)
673 return false;
674
675 return true;
676 }
677
678 static bool intel_sdvo_get_input_timing(struct intel_output *intel_output,
679 struct intel_sdvo_dtd *dtd)
680 {
681 return intel_sdvo_get_timing(intel_output,
682 SDVO_CMD_GET_INPUT_TIMINGS_PART1, dtd);
683 }
684
685 static bool intel_sdvo_get_output_timing(struct intel_output *intel_output,
686 struct intel_sdvo_dtd *dtd)
687 {
688 return intel_sdvo_get_timing(intel_output,
689 SDVO_CMD_GET_OUTPUT_TIMINGS_PART1, dtd);
690 }
691
692 static bool intel_sdvo_set_timing(struct intel_output *intel_output, u8 cmd,
693 struct intel_sdvo_dtd *dtd)
694 {
695 u8 status;
696
697 intel_sdvo_write_cmd(intel_output, cmd, &dtd->part1, sizeof(dtd->part1));
698 status = intel_sdvo_read_response(intel_output, NULL, 0);
699 if (status != SDVO_CMD_STATUS_SUCCESS)
700 return false;
701
702 intel_sdvo_write_cmd(intel_output, cmd + 1, &dtd->part2, sizeof(dtd->part2));
703 status = intel_sdvo_read_response(intel_output, NULL, 0);
704 if (status != SDVO_CMD_STATUS_SUCCESS)
705 return false;
706
707 return true;
708 }
709
710 static bool intel_sdvo_set_input_timing(struct intel_output *intel_output,
711 struct intel_sdvo_dtd *dtd)
712 {
713 return intel_sdvo_set_timing(intel_output,
714 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
715 }
716
717 static bool intel_sdvo_set_output_timing(struct intel_output *intel_output,
718 struct intel_sdvo_dtd *dtd)
719 {
720 return intel_sdvo_set_timing(intel_output,
721 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
722 }
723
724 static bool
725 intel_sdvo_create_preferred_input_timing(struct intel_output *output,
726 uint16_t clock,
727 uint16_t width,
728 uint16_t height)
729 {
730 struct intel_sdvo_preferred_input_timing_args args;
731 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
732 uint8_t status;
733
734 memset(&args, 0, sizeof(args));
735 args.clock = clock;
736 args.width = width;
737 args.height = height;
738 args.interlace = 0;
739
740 if (sdvo_priv->is_lvds &&
741 (sdvo_priv->sdvo_lvds_fixed_mode->hdisplay != width ||
742 sdvo_priv->sdvo_lvds_fixed_mode->vdisplay != height))
743 args.scaled = 1;
744
745 intel_sdvo_write_cmd(output, SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
746 &args, sizeof(args));
747 status = intel_sdvo_read_response(output, NULL, 0);
748 if (status != SDVO_CMD_STATUS_SUCCESS)
749 return false;
750
751 return true;
752 }
753
754 static bool intel_sdvo_get_preferred_input_timing(struct intel_output *output,
755 struct intel_sdvo_dtd *dtd)
756 {
757 bool status;
758
759 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
760 NULL, 0);
761
762 status = intel_sdvo_read_response(output, &dtd->part1,
763 sizeof(dtd->part1));
764 if (status != SDVO_CMD_STATUS_SUCCESS)
765 return false;
766
767 intel_sdvo_write_cmd(output, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
768 NULL, 0);
769
770 status = intel_sdvo_read_response(output, &dtd->part2,
771 sizeof(dtd->part2));
772 if (status != SDVO_CMD_STATUS_SUCCESS)
773 return false;
774
775 return false;
776 }
777
778 static int intel_sdvo_get_clock_rate_mult(struct intel_output *intel_output)
779 {
780 u8 response, status;
781
782 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_CLOCK_RATE_MULT, NULL, 0);
783 status = intel_sdvo_read_response(intel_output, &response, 1);
784
785 if (status != SDVO_CMD_STATUS_SUCCESS) {
786 DRM_DEBUG_KMS("Couldn't get SDVO clock rate multiplier\n");
787 return SDVO_CLOCK_RATE_MULT_1X;
788 } else {
789 DRM_DEBUG_KMS("Current clock rate multiplier: %d\n", response);
790 }
791
792 return response;
793 }
794
795 static bool intel_sdvo_set_clock_rate_mult(struct intel_output *intel_output, u8 val)
796 {
797 u8 status;
798
799 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
800 status = intel_sdvo_read_response(intel_output, NULL, 0);
801 if (status != SDVO_CMD_STATUS_SUCCESS)
802 return false;
803
804 return true;
805 }
806
807 static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
808 struct drm_display_mode *mode)
809 {
810 uint16_t width, height;
811 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
812 uint16_t h_sync_offset, v_sync_offset;
813
814 width = mode->crtc_hdisplay;
815 height = mode->crtc_vdisplay;
816
817 /* do some mode translations */
818 h_blank_len = mode->crtc_hblank_end - mode->crtc_hblank_start;
819 h_sync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
820
821 v_blank_len = mode->crtc_vblank_end - mode->crtc_vblank_start;
822 v_sync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
823
824 h_sync_offset = mode->crtc_hsync_start - mode->crtc_hblank_start;
825 v_sync_offset = mode->crtc_vsync_start - mode->crtc_vblank_start;
826
827 dtd->part1.clock = mode->clock / 10;
828 dtd->part1.h_active = width & 0xff;
829 dtd->part1.h_blank = h_blank_len & 0xff;
830 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
831 ((h_blank_len >> 8) & 0xf);
832 dtd->part1.v_active = height & 0xff;
833 dtd->part1.v_blank = v_blank_len & 0xff;
834 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
835 ((v_blank_len >> 8) & 0xf);
836
837 dtd->part2.h_sync_off = h_sync_offset & 0xff;
838 dtd->part2.h_sync_width = h_sync_len & 0xff;
839 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
840 (v_sync_len & 0xf);
841 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
842 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
843 ((v_sync_len & 0x30) >> 4);
844
845 dtd->part2.dtd_flags = 0x18;
846 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
847 dtd->part2.dtd_flags |= 0x2;
848 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
849 dtd->part2.dtd_flags |= 0x4;
850
851 dtd->part2.sdvo_flags = 0;
852 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
853 dtd->part2.reserved = 0;
854 }
855
856 static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
857 struct intel_sdvo_dtd *dtd)
858 {
859 mode->hdisplay = dtd->part1.h_active;
860 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
861 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
862 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
863 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
864 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
865 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
866 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
867
868 mode->vdisplay = dtd->part1.v_active;
869 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
870 mode->vsync_start = mode->vdisplay;
871 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
872 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
873 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
874 mode->vsync_end = mode->vsync_start +
875 (dtd->part2.v_sync_off_width & 0xf);
876 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
877 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
878 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
879
880 mode->clock = dtd->part1.clock * 10;
881
882 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
883 if (dtd->part2.dtd_flags & 0x2)
884 mode->flags |= DRM_MODE_FLAG_PHSYNC;
885 if (dtd->part2.dtd_flags & 0x4)
886 mode->flags |= DRM_MODE_FLAG_PVSYNC;
887 }
888
889 static bool intel_sdvo_get_supp_encode(struct intel_output *output,
890 struct intel_sdvo_encode *encode)
891 {
892 uint8_t status;
893
894 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SUPP_ENCODE, NULL, 0);
895 status = intel_sdvo_read_response(output, encode, sizeof(*encode));
896 if (status != SDVO_CMD_STATUS_SUCCESS) { /* non-support means DVI */
897 memset(encode, 0, sizeof(*encode));
898 return false;
899 }
900
901 return true;
902 }
903
904 static bool intel_sdvo_set_encode(struct intel_output *output, uint8_t mode)
905 {
906 uint8_t status;
907
908 intel_sdvo_write_cmd(output, SDVO_CMD_SET_ENCODE, &mode, 1);
909 status = intel_sdvo_read_response(output, NULL, 0);
910
911 return (status == SDVO_CMD_STATUS_SUCCESS);
912 }
913
914 static bool intel_sdvo_set_colorimetry(struct intel_output *output,
915 uint8_t mode)
916 {
917 uint8_t status;
918
919 intel_sdvo_write_cmd(output, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
920 status = intel_sdvo_read_response(output, NULL, 0);
921
922 return (status == SDVO_CMD_STATUS_SUCCESS);
923 }
924
925 #if 0
926 static void intel_sdvo_dump_hdmi_buf(struct intel_output *output)
927 {
928 int i, j;
929 uint8_t set_buf_index[2];
930 uint8_t av_split;
931 uint8_t buf_size;
932 uint8_t buf[48];
933 uint8_t *pos;
934
935 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_AV_SPLIT, NULL, 0);
936 intel_sdvo_read_response(output, &av_split, 1);
937
938 for (i = 0; i <= av_split; i++) {
939 set_buf_index[0] = i; set_buf_index[1] = 0;
940 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX,
941 set_buf_index, 2);
942 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
943 intel_sdvo_read_response(output, &buf_size, 1);
944
945 pos = buf;
946 for (j = 0; j <= buf_size; j += 8) {
947 intel_sdvo_write_cmd(output, SDVO_CMD_GET_HBUF_DATA,
948 NULL, 0);
949 intel_sdvo_read_response(output, pos, 8);
950 pos += 8;
951 }
952 }
953 }
954 #endif
955
956 static void intel_sdvo_set_hdmi_buf(struct intel_output *output, int index,
957 uint8_t *data, int8_t size, uint8_t tx_rate)
958 {
959 uint8_t set_buf_index[2];
960
961 set_buf_index[0] = index;
962 set_buf_index[1] = 0;
963
964 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_INDEX, set_buf_index, 2);
965
966 for (; size > 0; size -= 8) {
967 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_DATA, data, 8);
968 data += 8;
969 }
970
971 intel_sdvo_write_cmd(output, SDVO_CMD_SET_HBUF_TXRATE, &tx_rate, 1);
972 }
973
974 static uint8_t intel_sdvo_calc_hbuf_csum(uint8_t *data, uint8_t size)
975 {
976 uint8_t csum = 0;
977 int i;
978
979 for (i = 0; i < size; i++)
980 csum += data[i];
981
982 return 0x100 - csum;
983 }
984
985 #define DIP_TYPE_AVI 0x82
986 #define DIP_VERSION_AVI 0x2
987 #define DIP_LEN_AVI 13
988
989 struct dip_infoframe {
990 uint8_t type;
991 uint8_t version;
992 uint8_t len;
993 uint8_t checksum;
994 union {
995 struct {
996 /* Packet Byte #1 */
997 uint8_t S:2;
998 uint8_t B:2;
999 uint8_t A:1;
1000 uint8_t Y:2;
1001 uint8_t rsvd1:1;
1002 /* Packet Byte #2 */
1003 uint8_t R:4;
1004 uint8_t M:2;
1005 uint8_t C:2;
1006 /* Packet Byte #3 */
1007 uint8_t SC:2;
1008 uint8_t Q:2;
1009 uint8_t EC:3;
1010 uint8_t ITC:1;
1011 /* Packet Byte #4 */
1012 uint8_t VIC:7;
1013 uint8_t rsvd2:1;
1014 /* Packet Byte #5 */
1015 uint8_t PR:4;
1016 uint8_t rsvd3:4;
1017 /* Packet Byte #6~13 */
1018 uint16_t top_bar_end;
1019 uint16_t bottom_bar_start;
1020 uint16_t left_bar_end;
1021 uint16_t right_bar_start;
1022 } avi;
1023 struct {
1024 /* Packet Byte #1 */
1025 uint8_t channel_count:3;
1026 uint8_t rsvd1:1;
1027 uint8_t coding_type:4;
1028 /* Packet Byte #2 */
1029 uint8_t sample_size:2; /* SS0, SS1 */
1030 uint8_t sample_frequency:3;
1031 uint8_t rsvd2:3;
1032 /* Packet Byte #3 */
1033 uint8_t coding_type_private:5;
1034 uint8_t rsvd3:3;
1035 /* Packet Byte #4 */
1036 uint8_t channel_allocation;
1037 /* Packet Byte #5 */
1038 uint8_t rsvd4:3;
1039 uint8_t level_shift:4;
1040 uint8_t downmix_inhibit:1;
1041 } audio;
1042 uint8_t payload[28];
1043 } __attribute__ ((packed)) u;
1044 } __attribute__((packed));
1045
1046 static void intel_sdvo_set_avi_infoframe(struct intel_output *output,
1047 struct drm_display_mode * mode)
1048 {
1049 struct dip_infoframe avi_if = {
1050 .type = DIP_TYPE_AVI,
1051 .version = DIP_VERSION_AVI,
1052 .len = DIP_LEN_AVI,
1053 };
1054
1055 avi_if.checksum = intel_sdvo_calc_hbuf_csum((uint8_t *)&avi_if,
1056 4 + avi_if.len);
1057 intel_sdvo_set_hdmi_buf(output, 1, (uint8_t *)&avi_if, 4 + avi_if.len,
1058 SDVO_HBUF_TX_VSYNC);
1059 }
1060
1061 static void intel_sdvo_set_tv_format(struct intel_output *output)
1062 {
1063
1064 struct intel_sdvo_tv_format format;
1065 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1066 uint32_t format_map, i;
1067 uint8_t status;
1068
1069 for (i = 0; i < TV_FORMAT_NUM; i++)
1070 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1071 break;
1072
1073 format_map = 1 << i;
1074 memset(&format, 0, sizeof(format));
1075 memcpy(&format, &format_map, sizeof(format_map) > sizeof(format) ?
1076 sizeof(format) : sizeof(format_map));
1077
1078 intel_sdvo_write_cmd(output, SDVO_CMD_SET_TV_FORMAT, &format_map,
1079 sizeof(format));
1080
1081 status = intel_sdvo_read_response(output, NULL, 0);
1082 if (status != SDVO_CMD_STATUS_SUCCESS)
1083 DRM_DEBUG_KMS("%s: Failed to set TV format\n",
1084 SDVO_NAME(sdvo_priv));
1085 }
1086
1087 static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
1088 struct drm_display_mode *mode,
1089 struct drm_display_mode *adjusted_mode)
1090 {
1091 struct intel_output *output = enc_to_intel_output(encoder);
1092 struct intel_sdvo_priv *dev_priv = output->dev_priv;
1093
1094 if (dev_priv->is_tv) {
1095 struct intel_sdvo_dtd output_dtd;
1096 bool success;
1097
1098 /* We need to construct preferred input timings based on our
1099 * output timings. To do that, we have to set the output
1100 * timings, even though this isn't really the right place in
1101 * the sequence to do it. Oh well.
1102 */
1103
1104
1105 /* Set output timings */
1106 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1107 intel_sdvo_set_target_output(output,
1108 dev_priv->controlled_output);
1109 intel_sdvo_set_output_timing(output, &output_dtd);
1110
1111 /* Set the input timing to the screen. Assume always input 0. */
1112 intel_sdvo_set_target_input(output, true, false);
1113
1114
1115 success = intel_sdvo_create_preferred_input_timing(output,
1116 mode->clock / 10,
1117 mode->hdisplay,
1118 mode->vdisplay);
1119 if (success) {
1120 struct intel_sdvo_dtd input_dtd;
1121
1122 intel_sdvo_get_preferred_input_timing(output,
1123 &input_dtd);
1124 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1125 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1126
1127 drm_mode_set_crtcinfo(adjusted_mode, 0);
1128
1129 mode->clock = adjusted_mode->clock;
1130
1131 adjusted_mode->clock *=
1132 intel_sdvo_get_pixel_multiplier(mode);
1133 } else {
1134 return false;
1135 }
1136 } else if (dev_priv->is_lvds) {
1137 struct intel_sdvo_dtd output_dtd;
1138 bool success;
1139
1140 drm_mode_set_crtcinfo(dev_priv->sdvo_lvds_fixed_mode, 0);
1141 /* Set output timings */
1142 intel_sdvo_get_dtd_from_mode(&output_dtd,
1143 dev_priv->sdvo_lvds_fixed_mode);
1144
1145 intel_sdvo_set_target_output(output,
1146 dev_priv->controlled_output);
1147 intel_sdvo_set_output_timing(output, &output_dtd);
1148
1149 /* Set the input timing to the screen. Assume always input 0. */
1150 intel_sdvo_set_target_input(output, true, false);
1151
1152
1153 success = intel_sdvo_create_preferred_input_timing(
1154 output,
1155 mode->clock / 10,
1156 mode->hdisplay,
1157 mode->vdisplay);
1158
1159 if (success) {
1160 struct intel_sdvo_dtd input_dtd;
1161
1162 intel_sdvo_get_preferred_input_timing(output,
1163 &input_dtd);
1164 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
1165 dev_priv->sdvo_flags = input_dtd.part2.sdvo_flags;
1166
1167 drm_mode_set_crtcinfo(adjusted_mode, 0);
1168
1169 mode->clock = adjusted_mode->clock;
1170
1171 adjusted_mode->clock *=
1172 intel_sdvo_get_pixel_multiplier(mode);
1173 } else {
1174 return false;
1175 }
1176
1177 } else {
1178 /* Make the CRTC code factor in the SDVO pixel multiplier. The
1179 * SDVO device will be told of the multiplier during mode_set.
1180 */
1181 adjusted_mode->clock *= intel_sdvo_get_pixel_multiplier(mode);
1182 }
1183 return true;
1184 }
1185
1186 static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1187 struct drm_display_mode *mode,
1188 struct drm_display_mode *adjusted_mode)
1189 {
1190 struct drm_device *dev = encoder->dev;
1191 struct drm_i915_private *dev_priv = dev->dev_private;
1192 struct drm_crtc *crtc = encoder->crtc;
1193 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1194 struct intel_output *output = enc_to_intel_output(encoder);
1195 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1196 u32 sdvox = 0;
1197 int sdvo_pixel_multiply;
1198 struct intel_sdvo_in_out_map in_out;
1199 struct intel_sdvo_dtd input_dtd;
1200 u8 status;
1201
1202 if (!mode)
1203 return;
1204
1205 /* First, set the input mapping for the first input to our controlled
1206 * output. This is only correct if we're a single-input device, in
1207 * which case the first input is the output from the appropriate SDVO
1208 * channel on the motherboard. In a two-input device, the first input
1209 * will be SDVOB and the second SDVOC.
1210 */
1211 in_out.in0 = sdvo_priv->controlled_output;
1212 in_out.in1 = 0;
1213
1214 intel_sdvo_write_cmd(output, SDVO_CMD_SET_IN_OUT_MAP,
1215 &in_out, sizeof(in_out));
1216 status = intel_sdvo_read_response(output, NULL, 0);
1217
1218 if (sdvo_priv->is_hdmi) {
1219 intel_sdvo_set_avi_infoframe(output, mode);
1220 sdvox |= SDVO_AUDIO_ENABLE;
1221 }
1222
1223 /* We have tried to get input timing in mode_fixup, and filled into
1224 adjusted_mode */
1225 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1226 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
1227 input_dtd.part2.sdvo_flags = sdvo_priv->sdvo_flags;
1228 } else
1229 intel_sdvo_get_dtd_from_mode(&input_dtd, mode);
1230
1231 /* If it's a TV, we already set the output timing in mode_fixup.
1232 * Otherwise, the output timing is equal to the input timing.
1233 */
1234 if (!sdvo_priv->is_tv && !sdvo_priv->is_lvds) {
1235 /* Set the output timing to the screen */
1236 intel_sdvo_set_target_output(output,
1237 sdvo_priv->controlled_output);
1238 intel_sdvo_set_output_timing(output, &input_dtd);
1239 }
1240
1241 /* Set the input timing to the screen. Assume always input 0. */
1242 intel_sdvo_set_target_input(output, true, false);
1243
1244 if (sdvo_priv->is_tv)
1245 intel_sdvo_set_tv_format(output);
1246
1247 /* We would like to use intel_sdvo_create_preferred_input_timing() to
1248 * provide the device with a timing it can support, if it supports that
1249 * feature. However, presumably we would need to adjust the CRTC to
1250 * output the preferred timing, and we don't support that currently.
1251 */
1252 #if 0
1253 success = intel_sdvo_create_preferred_input_timing(output, clock,
1254 width, height);
1255 if (success) {
1256 struct intel_sdvo_dtd *input_dtd;
1257
1258 intel_sdvo_get_preferred_input_timing(output, &input_dtd);
1259 intel_sdvo_set_input_timing(output, &input_dtd);
1260 }
1261 #else
1262 intel_sdvo_set_input_timing(output, &input_dtd);
1263 #endif
1264
1265 switch (intel_sdvo_get_pixel_multiplier(mode)) {
1266 case 1:
1267 intel_sdvo_set_clock_rate_mult(output,
1268 SDVO_CLOCK_RATE_MULT_1X);
1269 break;
1270 case 2:
1271 intel_sdvo_set_clock_rate_mult(output,
1272 SDVO_CLOCK_RATE_MULT_2X);
1273 break;
1274 case 4:
1275 intel_sdvo_set_clock_rate_mult(output,
1276 SDVO_CLOCK_RATE_MULT_4X);
1277 break;
1278 }
1279
1280 /* Set the SDVO control regs. */
1281 if (IS_I965G(dev)) {
1282 sdvox |= SDVO_BORDER_ENABLE |
1283 SDVO_VSYNC_ACTIVE_HIGH |
1284 SDVO_HSYNC_ACTIVE_HIGH;
1285 } else {
1286 sdvox |= I915_READ(sdvo_priv->output_device);
1287 switch (sdvo_priv->output_device) {
1288 case SDVOB:
1289 sdvox &= SDVOB_PRESERVE_MASK;
1290 break;
1291 case SDVOC:
1292 sdvox &= SDVOC_PRESERVE_MASK;
1293 break;
1294 }
1295 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1296 }
1297 if (intel_crtc->pipe == 1)
1298 sdvox |= SDVO_PIPE_B_SELECT;
1299
1300 sdvo_pixel_multiply = intel_sdvo_get_pixel_multiplier(mode);
1301 if (IS_I965G(dev)) {
1302 /* done in crtc_mode_set as the dpll_md reg must be written early */
1303 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1304 /* done in crtc_mode_set as it lives inside the dpll register */
1305 } else {
1306 sdvox |= (sdvo_pixel_multiply - 1) << SDVO_PORT_MULTIPLY_SHIFT;
1307 }
1308
1309 if (sdvo_priv->sdvo_flags & SDVO_NEED_TO_STALL)
1310 sdvox |= SDVO_STALL_SELECT;
1311 intel_sdvo_write_sdvox(output, sdvox);
1312 }
1313
1314 static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1315 {
1316 struct drm_device *dev = encoder->dev;
1317 struct drm_i915_private *dev_priv = dev->dev_private;
1318 struct intel_output *intel_output = enc_to_intel_output(encoder);
1319 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1320 u32 temp;
1321
1322 if (mode != DRM_MODE_DPMS_ON) {
1323 intel_sdvo_set_active_outputs(intel_output, 0);
1324 if (0)
1325 intel_sdvo_set_encoder_power_state(intel_output, mode);
1326
1327 if (mode == DRM_MODE_DPMS_OFF) {
1328 temp = I915_READ(sdvo_priv->output_device);
1329 if ((temp & SDVO_ENABLE) != 0) {
1330 intel_sdvo_write_sdvox(intel_output, temp & ~SDVO_ENABLE);
1331 }
1332 }
1333 } else {
1334 bool input1, input2;
1335 int i;
1336 u8 status;
1337
1338 temp = I915_READ(sdvo_priv->output_device);
1339 if ((temp & SDVO_ENABLE) == 0)
1340 intel_sdvo_write_sdvox(intel_output, temp | SDVO_ENABLE);
1341 for (i = 0; i < 2; i++)
1342 intel_wait_for_vblank(dev);
1343
1344 status = intel_sdvo_get_trained_inputs(intel_output, &input1,
1345 &input2);
1346
1347
1348 /* Warn if the device reported failure to sync.
1349 * A lot of SDVO devices fail to notify of sync, but it's
1350 * a given it the status is a success, we succeeded.
1351 */
1352 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
1353 DRM_DEBUG_KMS("First %s output reported failure to "
1354 "sync\n", SDVO_NAME(sdvo_priv));
1355 }
1356
1357 if (0)
1358 intel_sdvo_set_encoder_power_state(intel_output, mode);
1359 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->controlled_output);
1360 }
1361 return;
1362 }
1363
1364 static void intel_sdvo_save(struct drm_connector *connector)
1365 {
1366 struct drm_device *dev = connector->dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 struct intel_output *intel_output = to_intel_output(connector);
1369 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1370 int o;
1371
1372 sdvo_priv->save_sdvo_mult = intel_sdvo_get_clock_rate_mult(intel_output);
1373 intel_sdvo_get_active_outputs(intel_output, &sdvo_priv->save_active_outputs);
1374
1375 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1376 intel_sdvo_set_target_input(intel_output, true, false);
1377 intel_sdvo_get_input_timing(intel_output,
1378 &sdvo_priv->save_input_dtd_1);
1379 }
1380
1381 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1382 intel_sdvo_set_target_input(intel_output, false, true);
1383 intel_sdvo_get_input_timing(intel_output,
1384 &sdvo_priv->save_input_dtd_2);
1385 }
1386
1387 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1388 {
1389 u16 this_output = (1 << o);
1390 if (sdvo_priv->caps.output_flags & this_output)
1391 {
1392 intel_sdvo_set_target_output(intel_output, this_output);
1393 intel_sdvo_get_output_timing(intel_output,
1394 &sdvo_priv->save_output_dtd[o]);
1395 }
1396 }
1397 if (sdvo_priv->is_tv) {
1398 /* XXX: Save TV format/enhancements. */
1399 }
1400
1401 sdvo_priv->save_SDVOX = I915_READ(sdvo_priv->output_device);
1402 }
1403
1404 static void intel_sdvo_restore(struct drm_connector *connector)
1405 {
1406 struct drm_device *dev = connector->dev;
1407 struct intel_output *intel_output = to_intel_output(connector);
1408 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1409 int o;
1410 int i;
1411 bool input1, input2;
1412 u8 status;
1413
1414 intel_sdvo_set_active_outputs(intel_output, 0);
1415
1416 for (o = SDVO_OUTPUT_FIRST; o <= SDVO_OUTPUT_LAST; o++)
1417 {
1418 u16 this_output = (1 << o);
1419 if (sdvo_priv->caps.output_flags & this_output) {
1420 intel_sdvo_set_target_output(intel_output, this_output);
1421 intel_sdvo_set_output_timing(intel_output, &sdvo_priv->save_output_dtd[o]);
1422 }
1423 }
1424
1425 if (sdvo_priv->caps.sdvo_inputs_mask & 0x1) {
1426 intel_sdvo_set_target_input(intel_output, true, false);
1427 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_1);
1428 }
1429
1430 if (sdvo_priv->caps.sdvo_inputs_mask & 0x2) {
1431 intel_sdvo_set_target_input(intel_output, false, true);
1432 intel_sdvo_set_input_timing(intel_output, &sdvo_priv->save_input_dtd_2);
1433 }
1434
1435 intel_sdvo_set_clock_rate_mult(intel_output, sdvo_priv->save_sdvo_mult);
1436
1437 if (sdvo_priv->is_tv) {
1438 /* XXX: Restore TV format/enhancements. */
1439 }
1440
1441 intel_sdvo_write_sdvox(intel_output, sdvo_priv->save_SDVOX);
1442
1443 if (sdvo_priv->save_SDVOX & SDVO_ENABLE)
1444 {
1445 for (i = 0; i < 2; i++)
1446 intel_wait_for_vblank(dev);
1447 status = intel_sdvo_get_trained_inputs(intel_output, &input1, &input2);
1448 if (status == SDVO_CMD_STATUS_SUCCESS && !input1)
1449 DRM_DEBUG_KMS("First %s output reported failure to "
1450 "sync\n", SDVO_NAME(sdvo_priv));
1451 }
1452
1453 intel_sdvo_set_active_outputs(intel_output, sdvo_priv->save_active_outputs);
1454 }
1455
1456 static int intel_sdvo_mode_valid(struct drm_connector *connector,
1457 struct drm_display_mode *mode)
1458 {
1459 struct intel_output *intel_output = to_intel_output(connector);
1460 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1461
1462 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1463 return MODE_NO_DBLESCAN;
1464
1465 if (sdvo_priv->pixel_clock_min > mode->clock)
1466 return MODE_CLOCK_LOW;
1467
1468 if (sdvo_priv->pixel_clock_max < mode->clock)
1469 return MODE_CLOCK_HIGH;
1470
1471 if (sdvo_priv->is_lvds == true) {
1472 if (sdvo_priv->sdvo_lvds_fixed_mode == NULL)
1473 return MODE_PANEL;
1474
1475 if (mode->hdisplay > sdvo_priv->sdvo_lvds_fixed_mode->hdisplay)
1476 return MODE_PANEL;
1477
1478 if (mode->vdisplay > sdvo_priv->sdvo_lvds_fixed_mode->vdisplay)
1479 return MODE_PANEL;
1480 }
1481
1482 return MODE_OK;
1483 }
1484
1485 static bool intel_sdvo_get_capabilities(struct intel_output *intel_output, struct intel_sdvo_caps *caps)
1486 {
1487 u8 status;
1488
1489 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_DEVICE_CAPS, NULL, 0);
1490 status = intel_sdvo_read_response(intel_output, caps, sizeof(*caps));
1491 if (status != SDVO_CMD_STATUS_SUCCESS)
1492 return false;
1493
1494 return true;
1495 }
1496
1497 struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB)
1498 {
1499 struct drm_connector *connector = NULL;
1500 struct intel_output *iout = NULL;
1501 struct intel_sdvo_priv *sdvo;
1502
1503 /* find the sdvo connector */
1504 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1505 iout = to_intel_output(connector);
1506
1507 if (iout->type != INTEL_OUTPUT_SDVO)
1508 continue;
1509
1510 sdvo = iout->dev_priv;
1511
1512 if (sdvo->output_device == SDVOB && sdvoB)
1513 return connector;
1514
1515 if (sdvo->output_device == SDVOC && !sdvoB)
1516 return connector;
1517
1518 }
1519
1520 return NULL;
1521 }
1522
1523 int intel_sdvo_supports_hotplug(struct drm_connector *connector)
1524 {
1525 u8 response[2];
1526 u8 status;
1527 struct intel_output *intel_output;
1528 DRM_DEBUG_KMS("\n");
1529
1530 if (!connector)
1531 return 0;
1532
1533 intel_output = to_intel_output(connector);
1534
1535 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1536 status = intel_sdvo_read_response(intel_output, &response, 2);
1537
1538 if (response[0] !=0)
1539 return 1;
1540
1541 return 0;
1542 }
1543
1544 void intel_sdvo_set_hotplug(struct drm_connector *connector, int on)
1545 {
1546 u8 response[2];
1547 u8 status;
1548 struct intel_output *intel_output = to_intel_output(connector);
1549
1550 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1551 intel_sdvo_read_response(intel_output, &response, 2);
1552
1553 if (on) {
1554 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_HOT_PLUG_SUPPORT, NULL, 0);
1555 status = intel_sdvo_read_response(intel_output, &response, 2);
1556
1557 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1558 } else {
1559 response[0] = 0;
1560 response[1] = 0;
1561 intel_sdvo_write_cmd(intel_output, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &response, 2);
1562 }
1563
1564 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_ACTIVE_HOT_PLUG, NULL, 0);
1565 intel_sdvo_read_response(intel_output, &response, 2);
1566 }
1567
1568 static bool
1569 intel_sdvo_multifunc_encoder(struct intel_output *intel_output)
1570 {
1571 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1572 int caps = 0;
1573
1574 if (sdvo_priv->caps.output_flags &
1575 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1576 caps++;
1577 if (sdvo_priv->caps.output_flags &
1578 (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1))
1579 caps++;
1580 if (sdvo_priv->caps.output_flags &
1581 (SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_SVID1))
1582 caps++;
1583 if (sdvo_priv->caps.output_flags &
1584 (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_CVBS1))
1585 caps++;
1586 if (sdvo_priv->caps.output_flags &
1587 (SDVO_OUTPUT_YPRPB0 | SDVO_OUTPUT_YPRPB1))
1588 caps++;
1589
1590 if (sdvo_priv->caps.output_flags &
1591 (SDVO_OUTPUT_SCART0 | SDVO_OUTPUT_SCART1))
1592 caps++;
1593
1594 if (sdvo_priv->caps.output_flags &
1595 (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1))
1596 caps++;
1597
1598 return (caps > 1);
1599 }
1600
1601 static struct drm_connector *
1602 intel_find_analog_connector(struct drm_device *dev)
1603 {
1604 struct drm_connector *connector;
1605 struct intel_output *intel_output;
1606
1607 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1608 intel_output = to_intel_output(connector);
1609 if (intel_output->type == INTEL_OUTPUT_ANALOG)
1610 return connector;
1611 }
1612 return NULL;
1613 }
1614
1615 static int
1616 intel_analog_is_connected(struct drm_device *dev)
1617 {
1618 struct drm_connector *analog_connector;
1619 analog_connector = intel_find_analog_connector(dev);
1620
1621 if (!analog_connector)
1622 return false;
1623
1624 if (analog_connector->funcs->detect(analog_connector) ==
1625 connector_status_disconnected)
1626 return false;
1627
1628 return true;
1629 }
1630
1631 enum drm_connector_status
1632 intel_sdvo_hdmi_sink_detect(struct drm_connector *connector, u16 response)
1633 {
1634 struct intel_output *intel_output = to_intel_output(connector);
1635 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1636 enum drm_connector_status status = connector_status_connected;
1637 struct edid *edid = NULL;
1638
1639 edid = drm_get_edid(&intel_output->base,
1640 intel_output->ddc_bus);
1641
1642 /* This is only applied to SDVO cards with multiple outputs */
1643 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_output)) {
1644 uint8_t saved_ddc, temp_ddc;
1645 saved_ddc = sdvo_priv->ddc_bus;
1646 temp_ddc = sdvo_priv->ddc_bus >> 1;
1647 /*
1648 * Don't use the 1 as the argument of DDC bus switch to get
1649 * the EDID. It is used for SDVO SPD ROM.
1650 */
1651 while(temp_ddc > 1) {
1652 sdvo_priv->ddc_bus = temp_ddc;
1653 edid = drm_get_edid(&intel_output->base,
1654 intel_output->ddc_bus);
1655 if (edid) {
1656 /*
1657 * When we can get the EDID, maybe it is the
1658 * correct DDC bus. Update it.
1659 */
1660 sdvo_priv->ddc_bus = temp_ddc;
1661 break;
1662 }
1663 temp_ddc >>= 1;
1664 }
1665 if (edid == NULL)
1666 sdvo_priv->ddc_bus = saved_ddc;
1667 }
1668 /* when there is no edid and no monitor is connected with VGA
1669 * port, try to use the CRT ddc to read the EDID for DVI-connector
1670 */
1671 if (edid == NULL &&
1672 sdvo_priv->analog_ddc_bus &&
1673 !intel_analog_is_connected(intel_output->base.dev))
1674 edid = drm_get_edid(&intel_output->base,
1675 sdvo_priv->analog_ddc_bus);
1676 if (edid != NULL) {
1677 /* Don't report the output as connected if it's a DVI-I
1678 * connector with a non-digital EDID coming out.
1679 */
1680 if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
1681 if (edid->input & DRM_EDID_INPUT_DIGITAL)
1682 sdvo_priv->is_hdmi =
1683 drm_detect_hdmi_monitor(edid);
1684 else
1685 status = connector_status_disconnected;
1686 }
1687
1688 kfree(edid);
1689 intel_output->base.display_info.raw_edid = NULL;
1690
1691 } else if (response & (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1))
1692 status = connector_status_disconnected;
1693
1694 return status;
1695 }
1696
1697 static enum drm_connector_status intel_sdvo_detect(struct drm_connector *connector)
1698 {
1699 uint16_t response;
1700 u8 status;
1701 struct intel_output *intel_output = to_intel_output(connector);
1702 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1703
1704 intel_sdvo_write_cmd(intel_output,
1705 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0);
1706 status = intel_sdvo_read_response(intel_output, &response, 2);
1707
1708 DRM_DEBUG_KMS("SDVO response %d %d\n", response & 0xff, response >> 8);
1709
1710 if (status != SDVO_CMD_STATUS_SUCCESS)
1711 return connector_status_unknown;
1712
1713 if (response == 0)
1714 return connector_status_disconnected;
1715
1716 if (intel_sdvo_multifunc_encoder(intel_output) &&
1717 sdvo_priv->attached_output != response) {
1718 if (sdvo_priv->controlled_output != response &&
1719 intel_sdvo_output_setup(intel_output, response) != true)
1720 return connector_status_unknown;
1721 sdvo_priv->attached_output = response;
1722 }
1723 return intel_sdvo_hdmi_sink_detect(connector, response);
1724 }
1725
1726 static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
1727 {
1728 struct intel_output *intel_output = to_intel_output(connector);
1729 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1730 int num_modes;
1731
1732 /* set the bus switch and get the modes */
1733 num_modes = intel_ddc_get_modes(intel_output);
1734
1735 /*
1736 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1737 * link between analog and digital outputs. So, if the regular SDVO
1738 * DDC fails, check to see if the analog output is disconnected, in
1739 * which case we'll look there for the digital DDC data.
1740 */
1741 if (num_modes == 0 &&
1742 sdvo_priv->analog_ddc_bus &&
1743 !intel_analog_is_connected(intel_output->base.dev)) {
1744 struct i2c_adapter *digital_ddc_bus;
1745
1746 /* Switch to the analog ddc bus and try that
1747 */
1748 digital_ddc_bus = intel_output->ddc_bus;
1749 intel_output->ddc_bus = sdvo_priv->analog_ddc_bus;
1750
1751 (void) intel_ddc_get_modes(intel_output);
1752
1753 intel_output->ddc_bus = digital_ddc_bus;
1754 }
1755 }
1756
1757 /*
1758 * Set of SDVO TV modes.
1759 * Note! This is in reply order (see loop in get_tv_modes).
1760 * XXX: all 60Hz refresh?
1761 */
1762 struct drm_display_mode sdvo_tv_modes[] = {
1763 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1764 416, 0, 200, 201, 232, 233, 0,
1765 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1766 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1767 416, 0, 240, 241, 272, 273, 0,
1768 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1769 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1770 496, 0, 300, 301, 332, 333, 0,
1771 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1772 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1773 736, 0, 350, 351, 382, 383, 0,
1774 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1775 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1776 736, 0, 400, 401, 432, 433, 0,
1777 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1778 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1779 736, 0, 480, 481, 512, 513, 0,
1780 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1781 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1782 800, 0, 480, 481, 512, 513, 0,
1783 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1784 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1785 800, 0, 576, 577, 608, 609, 0,
1786 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1787 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1788 816, 0, 350, 351, 382, 383, 0,
1789 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1790 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1791 816, 0, 400, 401, 432, 433, 0,
1792 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1793 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1794 816, 0, 480, 481, 512, 513, 0,
1795 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1796 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1797 816, 0, 540, 541, 572, 573, 0,
1798 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1799 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1800 816, 0, 576, 577, 608, 609, 0,
1801 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1802 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1803 864, 0, 576, 577, 608, 609, 0,
1804 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1805 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1806 896, 0, 600, 601, 632, 633, 0,
1807 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1808 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1809 928, 0, 624, 625, 656, 657, 0,
1810 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1811 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1812 1016, 0, 766, 767, 798, 799, 0,
1813 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1814 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1815 1120, 0, 768, 769, 800, 801, 0,
1816 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1817 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1818 1376, 0, 1024, 1025, 1056, 1057, 0,
1819 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1820 };
1821
1822 static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1823 {
1824 struct intel_output *output = to_intel_output(connector);
1825 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1826 struct intel_sdvo_sdtv_resolution_request tv_res;
1827 uint32_t reply = 0, format_map = 0;
1828 int i;
1829 uint8_t status;
1830
1831
1832 /* Read the list of supported input resolutions for the selected TV
1833 * format.
1834 */
1835 for (i = 0; i < TV_FORMAT_NUM; i++)
1836 if (tv_format_names[i] == sdvo_priv->tv_format_name)
1837 break;
1838
1839 format_map = (1 << i);
1840 memcpy(&tv_res, &format_map,
1841 sizeof(struct intel_sdvo_sdtv_resolution_request) >
1842 sizeof(format_map) ? sizeof(format_map) :
1843 sizeof(struct intel_sdvo_sdtv_resolution_request));
1844
1845 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
1846
1847 intel_sdvo_write_cmd(output, SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
1848 &tv_res, sizeof(tv_res));
1849 status = intel_sdvo_read_response(output, &reply, 3);
1850 if (status != SDVO_CMD_STATUS_SUCCESS)
1851 return;
1852
1853 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
1854 if (reply & (1 << i)) {
1855 struct drm_display_mode *nmode;
1856 nmode = drm_mode_duplicate(connector->dev,
1857 &sdvo_tv_modes[i]);
1858 if (nmode)
1859 drm_mode_probed_add(connector, nmode);
1860 }
1861
1862 }
1863
1864 static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1865 {
1866 struct intel_output *intel_output = to_intel_output(connector);
1867 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1868 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1869 struct drm_display_mode *newmode;
1870
1871 /*
1872 * Attempt to get the mode list from DDC.
1873 * Assume that the preferred modes are
1874 * arranged in priority order.
1875 */
1876 intel_ddc_get_modes(intel_output);
1877 if (list_empty(&connector->probed_modes) == false)
1878 goto end;
1879
1880 /* Fetch modes from VBT */
1881 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
1882 newmode = drm_mode_duplicate(connector->dev,
1883 dev_priv->sdvo_lvds_vbt_mode);
1884 if (newmode != NULL) {
1885 /* Guarantee the mode is preferred */
1886 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1887 DRM_MODE_TYPE_DRIVER);
1888 drm_mode_probed_add(connector, newmode);
1889 }
1890 }
1891
1892 end:
1893 list_for_each_entry(newmode, &connector->probed_modes, head) {
1894 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1895 sdvo_priv->sdvo_lvds_fixed_mode =
1896 drm_mode_duplicate(connector->dev, newmode);
1897 break;
1898 }
1899 }
1900
1901 }
1902
1903 static int intel_sdvo_get_modes(struct drm_connector *connector)
1904 {
1905 struct intel_output *output = to_intel_output(connector);
1906 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
1907
1908 if (sdvo_priv->is_tv)
1909 intel_sdvo_get_tv_modes(connector);
1910 else if (sdvo_priv->is_lvds == true)
1911 intel_sdvo_get_lvds_modes(connector);
1912 else
1913 intel_sdvo_get_ddc_modes(connector);
1914
1915 if (list_empty(&connector->probed_modes))
1916 return 0;
1917 return 1;
1918 }
1919
1920 static
1921 void intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
1922 {
1923 struct intel_output *intel_output = to_intel_output(connector);
1924 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1925 struct drm_device *dev = connector->dev;
1926
1927 if (sdvo_priv->is_tv) {
1928 if (sdvo_priv->left_property)
1929 drm_property_destroy(dev, sdvo_priv->left_property);
1930 if (sdvo_priv->right_property)
1931 drm_property_destroy(dev, sdvo_priv->right_property);
1932 if (sdvo_priv->top_property)
1933 drm_property_destroy(dev, sdvo_priv->top_property);
1934 if (sdvo_priv->bottom_property)
1935 drm_property_destroy(dev, sdvo_priv->bottom_property);
1936 if (sdvo_priv->hpos_property)
1937 drm_property_destroy(dev, sdvo_priv->hpos_property);
1938 if (sdvo_priv->vpos_property)
1939 drm_property_destroy(dev, sdvo_priv->vpos_property);
1940 }
1941 if (sdvo_priv->is_tv) {
1942 if (sdvo_priv->saturation_property)
1943 drm_property_destroy(dev,
1944 sdvo_priv->saturation_property);
1945 if (sdvo_priv->contrast_property)
1946 drm_property_destroy(dev,
1947 sdvo_priv->contrast_property);
1948 if (sdvo_priv->hue_property)
1949 drm_property_destroy(dev, sdvo_priv->hue_property);
1950 }
1951 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
1952 if (sdvo_priv->brightness_property)
1953 drm_property_destroy(dev,
1954 sdvo_priv->brightness_property);
1955 }
1956 return;
1957 }
1958
1959 static void intel_sdvo_destroy(struct drm_connector *connector)
1960 {
1961 struct intel_output *intel_output = to_intel_output(connector);
1962 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1963
1964 if (intel_output->i2c_bus)
1965 intel_i2c_destroy(intel_output->i2c_bus);
1966 if (intel_output->ddc_bus)
1967 intel_i2c_destroy(intel_output->ddc_bus);
1968 if (sdvo_priv->analog_ddc_bus)
1969 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
1970
1971 if (sdvo_priv->sdvo_lvds_fixed_mode != NULL)
1972 drm_mode_destroy(connector->dev,
1973 sdvo_priv->sdvo_lvds_fixed_mode);
1974
1975 if (sdvo_priv->tv_format_property)
1976 drm_property_destroy(connector->dev,
1977 sdvo_priv->tv_format_property);
1978
1979 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
1980 intel_sdvo_destroy_enhance_property(connector);
1981
1982 drm_sysfs_connector_remove(connector);
1983 drm_connector_cleanup(connector);
1984
1985 kfree(intel_output);
1986 }
1987
1988 static int
1989 intel_sdvo_set_property(struct drm_connector *connector,
1990 struct drm_property *property,
1991 uint64_t val)
1992 {
1993 struct intel_output *intel_output = to_intel_output(connector);
1994 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
1995 struct drm_encoder *encoder = &intel_output->enc;
1996 struct drm_crtc *crtc = encoder->crtc;
1997 int ret = 0;
1998 bool changed = false;
1999 uint8_t cmd, status;
2000 uint16_t temp_value;
2001
2002 ret = drm_connector_property_set_value(connector, property, val);
2003 if (ret < 0)
2004 goto out;
2005
2006 if (property == sdvo_priv->tv_format_property) {
2007 if (val >= TV_FORMAT_NUM) {
2008 ret = -EINVAL;
2009 goto out;
2010 }
2011 if (sdvo_priv->tv_format_name ==
2012 sdvo_priv->tv_format_supported[val])
2013 goto out;
2014
2015 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[val];
2016 changed = true;
2017 }
2018
2019 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
2020 cmd = 0;
2021 temp_value = val;
2022 if (sdvo_priv->left_property == property) {
2023 drm_connector_property_set_value(connector,
2024 sdvo_priv->right_property, val);
2025 if (sdvo_priv->left_margin == temp_value)
2026 goto out;
2027
2028 sdvo_priv->left_margin = temp_value;
2029 sdvo_priv->right_margin = temp_value;
2030 temp_value = sdvo_priv->max_hscan -
2031 sdvo_priv->left_margin;
2032 cmd = SDVO_CMD_SET_OVERSCAN_H;
2033 } else if (sdvo_priv->right_property == property) {
2034 drm_connector_property_set_value(connector,
2035 sdvo_priv->left_property, val);
2036 if (sdvo_priv->right_margin == temp_value)
2037 goto out;
2038
2039 sdvo_priv->left_margin = temp_value;
2040 sdvo_priv->right_margin = temp_value;
2041 temp_value = sdvo_priv->max_hscan -
2042 sdvo_priv->left_margin;
2043 cmd = SDVO_CMD_SET_OVERSCAN_H;
2044 } else if (sdvo_priv->top_property == property) {
2045 drm_connector_property_set_value(connector,
2046 sdvo_priv->bottom_property, val);
2047 if (sdvo_priv->top_margin == temp_value)
2048 goto out;
2049
2050 sdvo_priv->top_margin = temp_value;
2051 sdvo_priv->bottom_margin = temp_value;
2052 temp_value = sdvo_priv->max_vscan -
2053 sdvo_priv->top_margin;
2054 cmd = SDVO_CMD_SET_OVERSCAN_V;
2055 } else if (sdvo_priv->bottom_property == property) {
2056 drm_connector_property_set_value(connector,
2057 sdvo_priv->top_property, val);
2058 if (sdvo_priv->bottom_margin == temp_value)
2059 goto out;
2060 sdvo_priv->top_margin = temp_value;
2061 sdvo_priv->bottom_margin = temp_value;
2062 temp_value = sdvo_priv->max_vscan -
2063 sdvo_priv->top_margin;
2064 cmd = SDVO_CMD_SET_OVERSCAN_V;
2065 } else if (sdvo_priv->hpos_property == property) {
2066 if (sdvo_priv->cur_hpos == temp_value)
2067 goto out;
2068
2069 cmd = SDVO_CMD_SET_POSITION_H;
2070 sdvo_priv->cur_hpos = temp_value;
2071 } else if (sdvo_priv->vpos_property == property) {
2072 if (sdvo_priv->cur_vpos == temp_value)
2073 goto out;
2074
2075 cmd = SDVO_CMD_SET_POSITION_V;
2076 sdvo_priv->cur_vpos = temp_value;
2077 } else if (sdvo_priv->saturation_property == property) {
2078 if (sdvo_priv->cur_saturation == temp_value)
2079 goto out;
2080
2081 cmd = SDVO_CMD_SET_SATURATION;
2082 sdvo_priv->cur_saturation = temp_value;
2083 } else if (sdvo_priv->contrast_property == property) {
2084 if (sdvo_priv->cur_contrast == temp_value)
2085 goto out;
2086
2087 cmd = SDVO_CMD_SET_CONTRAST;
2088 sdvo_priv->cur_contrast = temp_value;
2089 } else if (sdvo_priv->hue_property == property) {
2090 if (sdvo_priv->cur_hue == temp_value)
2091 goto out;
2092
2093 cmd = SDVO_CMD_SET_HUE;
2094 sdvo_priv->cur_hue = temp_value;
2095 } else if (sdvo_priv->brightness_property == property) {
2096 if (sdvo_priv->cur_brightness == temp_value)
2097 goto out;
2098
2099 cmd = SDVO_CMD_SET_BRIGHTNESS;
2100 sdvo_priv->cur_brightness = temp_value;
2101 }
2102 if (cmd) {
2103 intel_sdvo_write_cmd(intel_output, cmd, &temp_value, 2);
2104 status = intel_sdvo_read_response(intel_output,
2105 NULL, 0);
2106 if (status != SDVO_CMD_STATUS_SUCCESS) {
2107 DRM_DEBUG_KMS("Incorrect SDVO command \n");
2108 return -EINVAL;
2109 }
2110 changed = true;
2111 }
2112 }
2113 if (changed && crtc)
2114 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
2115 crtc->y, crtc->fb);
2116 out:
2117 return ret;
2118 }
2119
2120 static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
2121 .dpms = intel_sdvo_dpms,
2122 .mode_fixup = intel_sdvo_mode_fixup,
2123 .prepare = intel_encoder_prepare,
2124 .mode_set = intel_sdvo_mode_set,
2125 .commit = intel_encoder_commit,
2126 };
2127
2128 static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
2129 .dpms = drm_helper_connector_dpms,
2130 .save = intel_sdvo_save,
2131 .restore = intel_sdvo_restore,
2132 .detect = intel_sdvo_detect,
2133 .fill_modes = drm_helper_probe_single_connector_modes,
2134 .set_property = intel_sdvo_set_property,
2135 .destroy = intel_sdvo_destroy,
2136 };
2137
2138 static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
2139 .get_modes = intel_sdvo_get_modes,
2140 .mode_valid = intel_sdvo_mode_valid,
2141 .best_encoder = intel_best_encoder,
2142 };
2143
2144 static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
2145 {
2146 drm_encoder_cleanup(encoder);
2147 }
2148
2149 static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
2150 .destroy = intel_sdvo_enc_destroy,
2151 };
2152
2153
2154 /**
2155 * Choose the appropriate DDC bus for control bus switch command for this
2156 * SDVO output based on the controlled output.
2157 *
2158 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
2159 * outputs, then LVDS outputs.
2160 */
2161 static void
2162 intel_sdvo_select_ddc_bus(struct intel_sdvo_priv *dev_priv)
2163 {
2164 uint16_t mask = 0;
2165 unsigned int num_bits;
2166
2167 /* Make a mask of outputs less than or equal to our own priority in the
2168 * list.
2169 */
2170 switch (dev_priv->controlled_output) {
2171 case SDVO_OUTPUT_LVDS1:
2172 mask |= SDVO_OUTPUT_LVDS1;
2173 case SDVO_OUTPUT_LVDS0:
2174 mask |= SDVO_OUTPUT_LVDS0;
2175 case SDVO_OUTPUT_TMDS1:
2176 mask |= SDVO_OUTPUT_TMDS1;
2177 case SDVO_OUTPUT_TMDS0:
2178 mask |= SDVO_OUTPUT_TMDS0;
2179 case SDVO_OUTPUT_RGB1:
2180 mask |= SDVO_OUTPUT_RGB1;
2181 case SDVO_OUTPUT_RGB0:
2182 mask |= SDVO_OUTPUT_RGB0;
2183 break;
2184 }
2185
2186 /* Count bits to find what number we are in the priority list. */
2187 mask &= dev_priv->caps.output_flags;
2188 num_bits = hweight16(mask);
2189 if (num_bits > 3) {
2190 /* if more than 3 outputs, default to DDC bus 3 for now */
2191 num_bits = 3;
2192 }
2193
2194 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
2195 dev_priv->ddc_bus = 1 << num_bits;
2196 }
2197
2198 static bool
2199 intel_sdvo_get_digital_encoding_mode(struct intel_output *output)
2200 {
2201 struct intel_sdvo_priv *sdvo_priv = output->dev_priv;
2202 uint8_t status;
2203
2204 intel_sdvo_set_target_output(output, sdvo_priv->controlled_output);
2205
2206 intel_sdvo_write_cmd(output, SDVO_CMD_GET_ENCODE, NULL, 0);
2207 status = intel_sdvo_read_response(output, &sdvo_priv->is_hdmi, 1);
2208 if (status != SDVO_CMD_STATUS_SUCCESS)
2209 return false;
2210 return true;
2211 }
2212
2213 static struct intel_output *
2214 intel_sdvo_chan_to_intel_output(struct intel_i2c_chan *chan)
2215 {
2216 struct drm_device *dev = chan->drm_dev;
2217 struct drm_connector *connector;
2218 struct intel_output *intel_output = NULL;
2219
2220 list_for_each_entry(connector,
2221 &dev->mode_config.connector_list, head) {
2222 if (to_intel_output(connector)->ddc_bus == &chan->adapter) {
2223 intel_output = to_intel_output(connector);
2224 break;
2225 }
2226 }
2227 return intel_output;
2228 }
2229
2230 static int intel_sdvo_master_xfer(struct i2c_adapter *i2c_adap,
2231 struct i2c_msg msgs[], int num)
2232 {
2233 struct intel_output *intel_output;
2234 struct intel_sdvo_priv *sdvo_priv;
2235 struct i2c_algo_bit_data *algo_data;
2236 const struct i2c_algorithm *algo;
2237
2238 algo_data = (struct i2c_algo_bit_data *)i2c_adap->algo_data;
2239 intel_output =
2240 intel_sdvo_chan_to_intel_output(
2241 (struct intel_i2c_chan *)(algo_data->data));
2242 if (intel_output == NULL)
2243 return -EINVAL;
2244
2245 sdvo_priv = intel_output->dev_priv;
2246 algo = intel_output->i2c_bus->algo;
2247
2248 intel_sdvo_set_control_bus_switch(intel_output, sdvo_priv->ddc_bus);
2249 return algo->master_xfer(i2c_adap, msgs, num);
2250 }
2251
2252 static struct i2c_algorithm intel_sdvo_i2c_bit_algo = {
2253 .master_xfer = intel_sdvo_master_xfer,
2254 };
2255
2256 static u8
2257 intel_sdvo_get_slave_addr(struct drm_device *dev, int output_device)
2258 {
2259 struct drm_i915_private *dev_priv = dev->dev_private;
2260 struct sdvo_device_mapping *my_mapping, *other_mapping;
2261
2262 if (output_device == SDVOB) {
2263 my_mapping = &dev_priv->sdvo_mappings[0];
2264 other_mapping = &dev_priv->sdvo_mappings[1];
2265 } else {
2266 my_mapping = &dev_priv->sdvo_mappings[1];
2267 other_mapping = &dev_priv->sdvo_mappings[0];
2268 }
2269
2270 /* If the BIOS described our SDVO device, take advantage of it. */
2271 if (my_mapping->slave_addr)
2272 return my_mapping->slave_addr;
2273
2274 /* If the BIOS only described a different SDVO device, use the
2275 * address that it isn't using.
2276 */
2277 if (other_mapping->slave_addr) {
2278 if (other_mapping->slave_addr == 0x70)
2279 return 0x72;
2280 else
2281 return 0x70;
2282 }
2283
2284 /* No SDVO device info is found for another DVO port,
2285 * so use mapping assumption we had before BIOS parsing.
2286 */
2287 if (output_device == SDVOB)
2288 return 0x70;
2289 else
2290 return 0x72;
2291 }
2292
2293 static int intel_sdvo_bad_tv_callback(const struct dmi_system_id *id)
2294 {
2295 DRM_DEBUG_KMS("Ignoring bad SDVO TV connector for %s\n", id->ident);
2296 return 1;
2297 }
2298
2299 static struct dmi_system_id intel_sdvo_bad_tv[] = {
2300 {
2301 .callback = intel_sdvo_bad_tv_callback,
2302 .ident = "IntelG45/ICH10R/DME1737",
2303 .matches = {
2304 DMI_MATCH(DMI_SYS_VENDOR, "IBM CORPORATION"),
2305 DMI_MATCH(DMI_PRODUCT_NAME, "4800784"),
2306 },
2307 },
2308
2309 { } /* terminating entry */
2310 };
2311
2312 static bool
2313 intel_sdvo_output_setup(struct intel_output *intel_output, uint16_t flags)
2314 {
2315 struct drm_connector *connector = &intel_output->base;
2316 struct drm_encoder *encoder = &intel_output->enc;
2317 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2318 bool ret = true, registered = false;
2319
2320 sdvo_priv->is_tv = false;
2321 intel_output->needs_tv_clock = false;
2322 sdvo_priv->is_lvds = false;
2323
2324 if (device_is_registered(&connector->kdev)) {
2325 drm_sysfs_connector_remove(connector);
2326 registered = true;
2327 }
2328
2329 if (flags &
2330 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)) {
2331 if (sdvo_priv->caps.output_flags & SDVO_OUTPUT_TMDS0)
2332 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS0;
2333 else
2334 sdvo_priv->controlled_output = SDVO_OUTPUT_TMDS1;
2335
2336 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2337 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2338
2339 if (intel_sdvo_get_supp_encode(intel_output,
2340 &sdvo_priv->encode) &&
2341 intel_sdvo_get_digital_encoding_mode(intel_output) &&
2342 sdvo_priv->is_hdmi) {
2343 /* enable hdmi encoding mode if supported */
2344 intel_sdvo_set_encode(intel_output, SDVO_ENCODE_HDMI);
2345 intel_sdvo_set_colorimetry(intel_output,
2346 SDVO_COLORIMETRY_RGB256);
2347 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
2348 intel_output->clone_mask =
2349 (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2350 (1 << INTEL_ANALOG_CLONE_BIT);
2351 }
2352 } else if ((flags & SDVO_OUTPUT_SVID0) &&
2353 !dmi_check_system(intel_sdvo_bad_tv)) {
2354
2355 sdvo_priv->controlled_output = SDVO_OUTPUT_SVID0;
2356 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2357 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
2358 sdvo_priv->is_tv = true;
2359 intel_output->needs_tv_clock = true;
2360 intel_output->clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
2361 } else if (flags & SDVO_OUTPUT_RGB0) {
2362
2363 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB0;
2364 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2365 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2366 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2367 (1 << INTEL_ANALOG_CLONE_BIT);
2368 } else if (flags & SDVO_OUTPUT_RGB1) {
2369
2370 sdvo_priv->controlled_output = SDVO_OUTPUT_RGB1;
2371 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2372 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2373 intel_output->clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2374 (1 << INTEL_ANALOG_CLONE_BIT);
2375 } else if (flags & SDVO_OUTPUT_LVDS0) {
2376
2377 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS0;
2378 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2379 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2380 sdvo_priv->is_lvds = true;
2381 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2382 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2383 } else if (flags & SDVO_OUTPUT_LVDS1) {
2384
2385 sdvo_priv->controlled_output = SDVO_OUTPUT_LVDS1;
2386 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2387 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2388 sdvo_priv->is_lvds = true;
2389 intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT) |
2390 (1 << INTEL_SDVO_LVDS_CLONE_BIT);
2391 } else {
2392
2393 unsigned char bytes[2];
2394
2395 sdvo_priv->controlled_output = 0;
2396 memcpy(bytes, &sdvo_priv->caps.output_flags, 2);
2397 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
2398 SDVO_NAME(sdvo_priv),
2399 bytes[0], bytes[1]);
2400 ret = false;
2401 }
2402 intel_output->crtc_mask = (1 << 0) | (1 << 1);
2403
2404 if (ret && registered)
2405 ret = drm_sysfs_connector_add(connector) == 0 ? true : false;
2406
2407
2408 return ret;
2409
2410 }
2411
2412 static void intel_sdvo_tv_create_property(struct drm_connector *connector)
2413 {
2414 struct intel_output *intel_output = to_intel_output(connector);
2415 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2416 struct intel_sdvo_tv_format format;
2417 uint32_t format_map, i;
2418 uint8_t status;
2419
2420 intel_sdvo_set_target_output(intel_output,
2421 sdvo_priv->controlled_output);
2422
2423 intel_sdvo_write_cmd(intel_output,
2424 SDVO_CMD_GET_SUPPORTED_TV_FORMATS, NULL, 0);
2425 status = intel_sdvo_read_response(intel_output,
2426 &format, sizeof(format));
2427 if (status != SDVO_CMD_STATUS_SUCCESS)
2428 return;
2429
2430 memcpy(&format_map, &format, sizeof(format) > sizeof(format_map) ?
2431 sizeof(format_map) : sizeof(format));
2432
2433 if (format_map == 0)
2434 return;
2435
2436 sdvo_priv->format_supported_num = 0;
2437 for (i = 0 ; i < TV_FORMAT_NUM; i++)
2438 if (format_map & (1 << i)) {
2439 sdvo_priv->tv_format_supported
2440 [sdvo_priv->format_supported_num++] =
2441 tv_format_names[i];
2442 }
2443
2444
2445 sdvo_priv->tv_format_property =
2446 drm_property_create(
2447 connector->dev, DRM_MODE_PROP_ENUM,
2448 "mode", sdvo_priv->format_supported_num);
2449
2450 for (i = 0; i < sdvo_priv->format_supported_num; i++)
2451 drm_property_add_enum(
2452 sdvo_priv->tv_format_property, i,
2453 i, sdvo_priv->tv_format_supported[i]);
2454
2455 sdvo_priv->tv_format_name = sdvo_priv->tv_format_supported[0];
2456 drm_connector_attach_property(
2457 connector, sdvo_priv->tv_format_property, 0);
2458
2459 }
2460
2461 static void intel_sdvo_create_enhance_property(struct drm_connector *connector)
2462 {
2463 struct intel_output *intel_output = to_intel_output(connector);
2464 struct intel_sdvo_priv *sdvo_priv = intel_output->dev_priv;
2465 struct intel_sdvo_enhancements_reply sdvo_data;
2466 struct drm_device *dev = connector->dev;
2467 uint8_t status;
2468 uint16_t response, data_value[2];
2469
2470 intel_sdvo_write_cmd(intel_output, SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2471 NULL, 0);
2472 status = intel_sdvo_read_response(intel_output, &sdvo_data,
2473 sizeof(sdvo_data));
2474 if (status != SDVO_CMD_STATUS_SUCCESS) {
2475 DRM_DEBUG_KMS(" incorrect response is returned\n");
2476 return;
2477 }
2478 response = *((uint16_t *)&sdvo_data);
2479 if (!response) {
2480 DRM_DEBUG_KMS("No enhancement is supported\n");
2481 return;
2482 }
2483 if (sdvo_priv->is_tv) {
2484 /* when horizontal overscan is supported, Add the left/right
2485 * property
2486 */
2487 if (sdvo_data.overscan_h) {
2488 intel_sdvo_write_cmd(intel_output,
2489 SDVO_CMD_GET_MAX_OVERSCAN_H, NULL, 0);
2490 status = intel_sdvo_read_response(intel_output,
2491 &data_value, 4);
2492 if (status != SDVO_CMD_STATUS_SUCCESS) {
2493 DRM_DEBUG_KMS("Incorrect SDVO max "
2494 "h_overscan\n");
2495 return;
2496 }
2497 intel_sdvo_write_cmd(intel_output,
2498 SDVO_CMD_GET_OVERSCAN_H, NULL, 0);
2499 status = intel_sdvo_read_response(intel_output,
2500 &response, 2);
2501 if (status != SDVO_CMD_STATUS_SUCCESS) {
2502 DRM_DEBUG_KMS("Incorrect SDVO h_overscan\n");
2503 return;
2504 }
2505 sdvo_priv->max_hscan = data_value[0];
2506 sdvo_priv->left_margin = data_value[0] - response;
2507 sdvo_priv->right_margin = sdvo_priv->left_margin;
2508 sdvo_priv->left_property =
2509 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2510 "left_margin", 2);
2511 sdvo_priv->left_property->values[0] = 0;
2512 sdvo_priv->left_property->values[1] = data_value[0];
2513 drm_connector_attach_property(connector,
2514 sdvo_priv->left_property,
2515 sdvo_priv->left_margin);
2516 sdvo_priv->right_property =
2517 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2518 "right_margin", 2);
2519 sdvo_priv->right_property->values[0] = 0;
2520 sdvo_priv->right_property->values[1] = data_value[0];
2521 drm_connector_attach_property(connector,
2522 sdvo_priv->right_property,
2523 sdvo_priv->right_margin);
2524 DRM_DEBUG_KMS("h_overscan: max %d, "
2525 "default %d, current %d\n",
2526 data_value[0], data_value[1], response);
2527 }
2528 if (sdvo_data.overscan_v) {
2529 intel_sdvo_write_cmd(intel_output,
2530 SDVO_CMD_GET_MAX_OVERSCAN_V, NULL, 0);
2531 status = intel_sdvo_read_response(intel_output,
2532 &data_value, 4);
2533 if (status != SDVO_CMD_STATUS_SUCCESS) {
2534 DRM_DEBUG_KMS("Incorrect SDVO max "
2535 "v_overscan\n");
2536 return;
2537 }
2538 intel_sdvo_write_cmd(intel_output,
2539 SDVO_CMD_GET_OVERSCAN_V, NULL, 0);
2540 status = intel_sdvo_read_response(intel_output,
2541 &response, 2);
2542 if (status != SDVO_CMD_STATUS_SUCCESS) {
2543 DRM_DEBUG_KMS("Incorrect SDVO v_overscan\n");
2544 return;
2545 }
2546 sdvo_priv->max_vscan = data_value[0];
2547 sdvo_priv->top_margin = data_value[0] - response;
2548 sdvo_priv->bottom_margin = sdvo_priv->top_margin;
2549 sdvo_priv->top_property =
2550 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2551 "top_margin", 2);
2552 sdvo_priv->top_property->values[0] = 0;
2553 sdvo_priv->top_property->values[1] = data_value[0];
2554 drm_connector_attach_property(connector,
2555 sdvo_priv->top_property,
2556 sdvo_priv->top_margin);
2557 sdvo_priv->bottom_property =
2558 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2559 "bottom_margin", 2);
2560 sdvo_priv->bottom_property->values[0] = 0;
2561 sdvo_priv->bottom_property->values[1] = data_value[0];
2562 drm_connector_attach_property(connector,
2563 sdvo_priv->bottom_property,
2564 sdvo_priv->bottom_margin);
2565 DRM_DEBUG_KMS("v_overscan: max %d, "
2566 "default %d, current %d\n",
2567 data_value[0], data_value[1], response);
2568 }
2569 if (sdvo_data.position_h) {
2570 intel_sdvo_write_cmd(intel_output,
2571 SDVO_CMD_GET_MAX_POSITION_H, NULL, 0);
2572 status = intel_sdvo_read_response(intel_output,
2573 &data_value, 4);
2574 if (status != SDVO_CMD_STATUS_SUCCESS) {
2575 DRM_DEBUG_KMS("Incorrect SDVO Max h_pos\n");
2576 return;
2577 }
2578 intel_sdvo_write_cmd(intel_output,
2579 SDVO_CMD_GET_POSITION_H, NULL, 0);
2580 status = intel_sdvo_read_response(intel_output,
2581 &response, 2);
2582 if (status != SDVO_CMD_STATUS_SUCCESS) {
2583 DRM_DEBUG_KMS("Incorrect SDVO get h_postion\n");
2584 return;
2585 }
2586 sdvo_priv->max_hpos = data_value[0];
2587 sdvo_priv->cur_hpos = response;
2588 sdvo_priv->hpos_property =
2589 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2590 "hpos", 2);
2591 sdvo_priv->hpos_property->values[0] = 0;
2592 sdvo_priv->hpos_property->values[1] = data_value[0];
2593 drm_connector_attach_property(connector,
2594 sdvo_priv->hpos_property,
2595 sdvo_priv->cur_hpos);
2596 DRM_DEBUG_KMS("h_position: max %d, "
2597 "default %d, current %d\n",
2598 data_value[0], data_value[1], response);
2599 }
2600 if (sdvo_data.position_v) {
2601 intel_sdvo_write_cmd(intel_output,
2602 SDVO_CMD_GET_MAX_POSITION_V, NULL, 0);
2603 status = intel_sdvo_read_response(intel_output,
2604 &data_value, 4);
2605 if (status != SDVO_CMD_STATUS_SUCCESS) {
2606 DRM_DEBUG_KMS("Incorrect SDVO Max v_pos\n");
2607 return;
2608 }
2609 intel_sdvo_write_cmd(intel_output,
2610 SDVO_CMD_GET_POSITION_V, NULL, 0);
2611 status = intel_sdvo_read_response(intel_output,
2612 &response, 2);
2613 if (status != SDVO_CMD_STATUS_SUCCESS) {
2614 DRM_DEBUG_KMS("Incorrect SDVO get v_postion\n");
2615 return;
2616 }
2617 sdvo_priv->max_vpos = data_value[0];
2618 sdvo_priv->cur_vpos = response;
2619 sdvo_priv->vpos_property =
2620 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2621 "vpos", 2);
2622 sdvo_priv->vpos_property->values[0] = 0;
2623 sdvo_priv->vpos_property->values[1] = data_value[0];
2624 drm_connector_attach_property(connector,
2625 sdvo_priv->vpos_property,
2626 sdvo_priv->cur_vpos);
2627 DRM_DEBUG_KMS("v_position: max %d, "
2628 "default %d, current %d\n",
2629 data_value[0], data_value[1], response);
2630 }
2631 }
2632 if (sdvo_priv->is_tv) {
2633 if (sdvo_data.saturation) {
2634 intel_sdvo_write_cmd(intel_output,
2635 SDVO_CMD_GET_MAX_SATURATION, NULL, 0);
2636 status = intel_sdvo_read_response(intel_output,
2637 &data_value, 4);
2638 if (status != SDVO_CMD_STATUS_SUCCESS) {
2639 DRM_DEBUG_KMS("Incorrect SDVO Max sat\n");
2640 return;
2641 }
2642 intel_sdvo_write_cmd(intel_output,
2643 SDVO_CMD_GET_SATURATION, NULL, 0);
2644 status = intel_sdvo_read_response(intel_output,
2645 &response, 2);
2646 if (status != SDVO_CMD_STATUS_SUCCESS) {
2647 DRM_DEBUG_KMS("Incorrect SDVO get sat\n");
2648 return;
2649 }
2650 sdvo_priv->max_saturation = data_value[0];
2651 sdvo_priv->cur_saturation = response;
2652 sdvo_priv->saturation_property =
2653 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2654 "saturation", 2);
2655 sdvo_priv->saturation_property->values[0] = 0;
2656 sdvo_priv->saturation_property->values[1] =
2657 data_value[0];
2658 drm_connector_attach_property(connector,
2659 sdvo_priv->saturation_property,
2660 sdvo_priv->cur_saturation);
2661 DRM_DEBUG_KMS("saturation: max %d, "
2662 "default %d, current %d\n",
2663 data_value[0], data_value[1], response);
2664 }
2665 if (sdvo_data.contrast) {
2666 intel_sdvo_write_cmd(intel_output,
2667 SDVO_CMD_GET_MAX_CONTRAST, NULL, 0);
2668 status = intel_sdvo_read_response(intel_output,
2669 &data_value, 4);
2670 if (status != SDVO_CMD_STATUS_SUCCESS) {
2671 DRM_DEBUG_KMS("Incorrect SDVO Max contrast\n");
2672 return;
2673 }
2674 intel_sdvo_write_cmd(intel_output,
2675 SDVO_CMD_GET_CONTRAST, NULL, 0);
2676 status = intel_sdvo_read_response(intel_output,
2677 &response, 2);
2678 if (status != SDVO_CMD_STATUS_SUCCESS) {
2679 DRM_DEBUG_KMS("Incorrect SDVO get contrast\n");
2680 return;
2681 }
2682 sdvo_priv->max_contrast = data_value[0];
2683 sdvo_priv->cur_contrast = response;
2684 sdvo_priv->contrast_property =
2685 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2686 "contrast", 2);
2687 sdvo_priv->contrast_property->values[0] = 0;
2688 sdvo_priv->contrast_property->values[1] = data_value[0];
2689 drm_connector_attach_property(connector,
2690 sdvo_priv->contrast_property,
2691 sdvo_priv->cur_contrast);
2692 DRM_DEBUG_KMS("contrast: max %d, "
2693 "default %d, current %d\n",
2694 data_value[0], data_value[1], response);
2695 }
2696 if (sdvo_data.hue) {
2697 intel_sdvo_write_cmd(intel_output,
2698 SDVO_CMD_GET_MAX_HUE, NULL, 0);
2699 status = intel_sdvo_read_response(intel_output,
2700 &data_value, 4);
2701 if (status != SDVO_CMD_STATUS_SUCCESS) {
2702 DRM_DEBUG_KMS("Incorrect SDVO Max hue\n");
2703 return;
2704 }
2705 intel_sdvo_write_cmd(intel_output,
2706 SDVO_CMD_GET_HUE, NULL, 0);
2707 status = intel_sdvo_read_response(intel_output,
2708 &response, 2);
2709 if (status != SDVO_CMD_STATUS_SUCCESS) {
2710 DRM_DEBUG_KMS("Incorrect SDVO get hue\n");
2711 return;
2712 }
2713 sdvo_priv->max_hue = data_value[0];
2714 sdvo_priv->cur_hue = response;
2715 sdvo_priv->hue_property =
2716 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2717 "hue", 2);
2718 sdvo_priv->hue_property->values[0] = 0;
2719 sdvo_priv->hue_property->values[1] =
2720 data_value[0];
2721 drm_connector_attach_property(connector,
2722 sdvo_priv->hue_property,
2723 sdvo_priv->cur_hue);
2724 DRM_DEBUG_KMS("hue: max %d, default %d, current %d\n",
2725 data_value[0], data_value[1], response);
2726 }
2727 }
2728 if (sdvo_priv->is_tv || sdvo_priv->is_lvds) {
2729 if (sdvo_data.brightness) {
2730 intel_sdvo_write_cmd(intel_output,
2731 SDVO_CMD_GET_MAX_BRIGHTNESS, NULL, 0);
2732 status = intel_sdvo_read_response(intel_output,
2733 &data_value, 4);
2734 if (status != SDVO_CMD_STATUS_SUCCESS) {
2735 DRM_DEBUG_KMS("Incorrect SDVO Max bright\n");
2736 return;
2737 }
2738 intel_sdvo_write_cmd(intel_output,
2739 SDVO_CMD_GET_BRIGHTNESS, NULL, 0);
2740 status = intel_sdvo_read_response(intel_output,
2741 &response, 2);
2742 if (status != SDVO_CMD_STATUS_SUCCESS) {
2743 DRM_DEBUG_KMS("Incorrect SDVO get brigh\n");
2744 return;
2745 }
2746 sdvo_priv->max_brightness = data_value[0];
2747 sdvo_priv->cur_brightness = response;
2748 sdvo_priv->brightness_property =
2749 drm_property_create(dev, DRM_MODE_PROP_RANGE,
2750 "brightness", 2);
2751 sdvo_priv->brightness_property->values[0] = 0;
2752 sdvo_priv->brightness_property->values[1] =
2753 data_value[0];
2754 drm_connector_attach_property(connector,
2755 sdvo_priv->brightness_property,
2756 sdvo_priv->cur_brightness);
2757 DRM_DEBUG_KMS("brightness: max %d, "
2758 "default %d, current %d\n",
2759 data_value[0], data_value[1], response);
2760 }
2761 }
2762 return;
2763 }
2764
2765 bool intel_sdvo_init(struct drm_device *dev, int output_device)
2766 {
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768 struct drm_connector *connector;
2769 struct intel_output *intel_output;
2770 struct intel_sdvo_priv *sdvo_priv;
2771
2772 u8 ch[0x40];
2773 int i;
2774
2775 intel_output = kcalloc(sizeof(struct intel_output)+sizeof(struct intel_sdvo_priv), 1, GFP_KERNEL);
2776 if (!intel_output) {
2777 return false;
2778 }
2779
2780 sdvo_priv = (struct intel_sdvo_priv *)(intel_output + 1);
2781 sdvo_priv->output_device = output_device;
2782
2783 intel_output->dev_priv = sdvo_priv;
2784 intel_output->type = INTEL_OUTPUT_SDVO;
2785
2786 /* setup the DDC bus. */
2787 if (output_device == SDVOB)
2788 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOB");
2789 else
2790 intel_output->i2c_bus = intel_i2c_create(dev, GPIOE, "SDVOCTRL_E for SDVOC");
2791
2792 if (!intel_output->i2c_bus)
2793 goto err_inteloutput;
2794
2795 sdvo_priv->slave_addr = intel_sdvo_get_slave_addr(dev, output_device);
2796
2797 /* Save the bit-banging i2c functionality for use by the DDC wrapper */
2798 intel_sdvo_i2c_bit_algo.functionality = intel_output->i2c_bus->algo->functionality;
2799
2800 /* Read the regs to test if we can talk to the device */
2801 for (i = 0; i < 0x40; i++) {
2802 if (!intel_sdvo_read_byte(intel_output, i, &ch[i])) {
2803 DRM_DEBUG_KMS("No SDVO device found on SDVO%c\n",
2804 output_device == SDVOB ? 'B' : 'C');
2805 goto err_i2c;
2806 }
2807 }
2808
2809 /* setup the DDC bus. */
2810 if (output_device == SDVOB) {
2811 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOB DDC BUS");
2812 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2813 "SDVOB/VGA DDC BUS");
2814 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
2815 } else {
2816 intel_output->ddc_bus = intel_i2c_create(dev, GPIOE, "SDVOC DDC BUS");
2817 sdvo_priv->analog_ddc_bus = intel_i2c_create(dev, GPIOA,
2818 "SDVOC/VGA DDC BUS");
2819 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
2820 }
2821
2822 if (intel_output->ddc_bus == NULL)
2823 goto err_i2c;
2824
2825 /* Wrap with our custom algo which switches to DDC mode */
2826 intel_output->ddc_bus->algo = &intel_sdvo_i2c_bit_algo;
2827
2828 /* In defaut case sdvo lvds is false */
2829 intel_sdvo_get_capabilities(intel_output, &sdvo_priv->caps);
2830
2831 if (intel_sdvo_output_setup(intel_output,
2832 sdvo_priv->caps.output_flags) != true) {
2833 DRM_DEBUG_KMS("SDVO output failed to setup on SDVO%c\n",
2834 output_device == SDVOB ? 'B' : 'C');
2835 goto err_i2c;
2836 }
2837
2838
2839 connector = &intel_output->base;
2840 drm_connector_init(dev, connector, &intel_sdvo_connector_funcs,
2841 connector->connector_type);
2842
2843 drm_connector_helper_add(connector, &intel_sdvo_connector_helper_funcs);
2844 connector->interlace_allowed = 0;
2845 connector->doublescan_allowed = 0;
2846 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
2847
2848 drm_encoder_init(dev, &intel_output->enc,
2849 &intel_sdvo_enc_funcs, intel_output->enc.encoder_type);
2850
2851 drm_encoder_helper_add(&intel_output->enc, &intel_sdvo_helper_funcs);
2852
2853 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
2854 if (sdvo_priv->is_tv)
2855 intel_sdvo_tv_create_property(connector);
2856
2857 if (sdvo_priv->is_tv || sdvo_priv->is_lvds)
2858 intel_sdvo_create_enhance_property(connector);
2859
2860 drm_sysfs_connector_add(connector);
2861
2862 intel_sdvo_select_ddc_bus(sdvo_priv);
2863
2864 /* Set the input timing to the screen. Assume always input 0. */
2865 intel_sdvo_set_target_input(intel_output, true, false);
2866
2867 intel_sdvo_get_input_pixel_clock_range(intel_output,
2868 &sdvo_priv->pixel_clock_min,
2869 &sdvo_priv->pixel_clock_max);
2870
2871
2872 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
2873 "clock range %dMHz - %dMHz, "
2874 "input 1: %c, input 2: %c, "
2875 "output 1: %c, output 2: %c\n",
2876 SDVO_NAME(sdvo_priv),
2877 sdvo_priv->caps.vendor_id, sdvo_priv->caps.device_id,
2878 sdvo_priv->caps.device_rev_id,
2879 sdvo_priv->pixel_clock_min / 1000,
2880 sdvo_priv->pixel_clock_max / 1000,
2881 (sdvo_priv->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2882 (sdvo_priv->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
2883 /* check currently supported outputs */
2884 sdvo_priv->caps.output_flags &
2885 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
2886 sdvo_priv->caps.output_flags &
2887 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
2888
2889 return true;
2890
2891 err_i2c:
2892 if (sdvo_priv->analog_ddc_bus != NULL)
2893 intel_i2c_destroy(sdvo_priv->analog_ddc_bus);
2894 if (intel_output->ddc_bus != NULL)
2895 intel_i2c_destroy(intel_output->ddc_bus);
2896 if (intel_output->i2c_bus != NULL)
2897 intel_i2c_destroy(intel_output->i2c_bus);
2898 err_inteloutput:
2899 kfree(intel_output);
2900
2901 return false;
2902 }
Linux ARM platform port for MOXA ART SoC